KR100694475B1 - Source Driver in LCD - Google Patents

Abstract

The present invention relates to a source driver of a liquid crystal display device capable of reducing chip size to reduce power consumption.

The source driver of the liquid crystal display device of the present invention comprises: a data selector for selecting predetermined bits of R, G, and B data input from the outside by an output signal from the mode selector; A data register for sequentially inputting and storing data from the data selector in accordance with an output signal from the shift register; A hold register for storing R, G, and B data sequentially stored in the data register according to a load signal for each line at a time; A level shifter for shifting the levels of R, G, and B data stored for each line in the hold register; A resistor string for inputting a reference voltage to generate a plurality of gray voltages; A gradation voltage controller for inputting a gradation voltage generated from the resistor string to control the gradation voltage in accordance with an output signal applied from the mode selector; A digital-to-analog converter for selecting one of the gradation voltages output from the gradation voltage controller according to the output signal from the level shifter; It is composed of an output buffer for providing the output of the digital analog converter to the LCD panel.

LCD, Source Driver, Data Selector, Mode Selector

Description

Source driver in liquid crystal display device             

1 is a block diagram of a source driver of a conventional liquid crystal display device;

2 is a block diagram of a source driver of a liquid crystal display according to an exemplary embodiment of the present invention;

3 is a view for explaining an operation example in the 1-bit mode in the source driver of the liquid crystal display according to the embodiment of the present invention;

* Explanation of symbols for main parts of drawings *

100: shift register 110: data register

120: hold register 130: shift register

150: digital analog converter 160: output buffer

170: data selector 180: mode selector

190: resistor string 200: gray voltage control unit

The present invention relates to a source driver of a liquid crystal display device, and more particularly, to a source driver of a liquid crystal display device capable of reducing chip size and power consumption.

A portable electronic device such as a cellular phone or a portable game machine uses a liquid crystal display (LCD) as a display device, and the power consumption of the liquid crystal display device limits the use time of the charger of the portable device. Therefore, the power consumption of the liquid crystal display device becomes a big problem as the handheld game machine becomes smaller, which is a limitation in extending the use time of the charger.

1 illustrates a configuration diagram of a source driver of a liquid crystal display device.

Referring to FIG. 1, a source driver of a conventional liquid crystal display device includes a data selector for selecting predetermined bits of R, G, and B data input from an external device by an output signal from a mode selector 18. the selector 17, the data register 11 for sequentially inputting and storing data from the data selector 17 in accordance with the output signal from the shift register 10, and the load signal LOAD. Hold registers 12 for storing R, G, and B data sequentially stored in the data register 11 by line, and R, G, and B data stored for each line in the hold register 12, respectively. A level shifter 13 for shifting the level of the input signal, and an output signal from the level shifter 13 to input 6-bit R, G, and B data according to the output signal of the mode selector 18. A digital-to-analog converter (150) for selectively outputting one of a data control unit (14) for switching and a gradation voltage output from the register string (19) in accordance with the data output from the data control unit (14), and It consists of an output buffer 160 that provides the output of the digital-to-analog converter 15 to the LCD panel.

The operation of the source driver as described above is as follows.

The data selector 17 selects only a predetermined bit among R, G, and B data of a predetermined bit input from the outside according to the output signal of the mode selector 18. For example, in case of source driver that supports maximum 6 bit mode and 3 bit mode, in case of 3 bit mode, select only the upper 3 bit among 6 bits of R, G, B data applied from the outside and the lower 3 bits are high level. Or fix it to low level.

The output of the mode selector 17 is provided to the data register 11 according to the signal output from the shift register 10 so that the data register 11 sequentially stores R, G, and B data.

The R, G, and B digital data stored in the data register 11 are stored for each line in the hold register 12 by a load signal LOAD applied from the outside. The R, G, and B data for each line stored in the hold register 12 are provided to the level shifter 13 and level converted.

The R, G, and B data level-converted through the level shifter 13 are provided to the data control unit 14 to convert back into 6-bit R, G, and B data. The data control unit 14 generates the lower 3 bits by using the upper 3 bits of data and converts the data into 6 bits.

In contrast, in the LCD source driver that supports up to 6 bits and supports at least 1 meat mode, the upper 1 bit of 6 bits of R, G, and B data is provided through the data selector 17 provided from the mode selector 18. Select only and lock the remaining low 5 bits to high or low level.

The R, G, and B data selected through the data selector 17 are provided to the data control unit 14 through the data register 11, the hold register 12, and the level shifter 13. At this time, when operating in the 1-bit mode, only the gray voltages of V0 and V63 are required among the gray voltages V0-V63 output from the register string 19.

Accordingly, the data control unit 14 inputs the R, G, and B data provided through the level shifter 13 to copy the lower 5 bits with the upper 1 bit to designate one of 000000 or 111111 as the output signal. Provided by analog converter 15.

Six bits of R, G, and B data from the data control unit 14 are provided to the multiplexer, which is a digital analog converter 15, and the multiplexer 15 is provided with 64 gray scale voltages provided from the resistor string. The corresponding one of V0-V63 is selected by the output signal provided from the data control unit 14 and provided to the output buffer 16. The output buffer 16 provides an analog gray scale voltage provided from the digital analog converter 15 to an LCD panel (not shown) to display.

The source driver having the above-described configuration has a variety of products depending on the number of bits of R, G, and B data because the number of colors to be supported varies depending on the characteristics and the application of the liquid crystal display in driving the liquid crystal display. Configure The color that the source driver can represent according to the number of bits is 8 colors for R, G, and B data of 1 bit, 64 colors for 2 bits, 512 colors for 4 bits, and 4 bits for 3 bits. It is possible to represent 4096 colors, 32768 colors for 5 bits, 262144 colors for 6 bits, 2097152 colors for 7 bits, and 16777216 colors for 8 bits.

The conventional source driver as described above is divided into a digital circuit portion consisting of a shift register 10, a data register 11, a hold register 12, and a level shifter 13, a digital analog converter 15, and an output buffer 16. It is divided into analog circuit parts composed of).

The conventional source driver can reduce the current consumption in the digital circuit part by passing only the upper bit through the data selector and fixing the remaining lower bit to the high level or the low level as described above.

However, in the conventional source driver as described above, the chip size is increased and consumed by connecting a data control unit for each channel to convert the selected data according to the data mode into R, G, B data of predetermined bits. There was a problem that the current increases. In order to solve this problem, there is a method of connecting a data control unit to the mode selector, which reduces the chip size, but consumes the same current regardless of the mode.

SUMMARY OF THE INVENTION The present invention has been made to solve the problems of the prior art as described above, and an object thereof is to provide a source driver of a liquid crystal display device capable of reducing power consumption and chip size.

The present invention for achieving the above object is a data selector for selecting a predetermined bit of R, G, B data input from the outside by the output signal from the mode selector; A data register for sequentially inputting and storing data from the data selector in accordance with an output signal from the shift register; A hold register for storing R, G, and B data sequentially stored in the data register according to a load signal for each line at a time; A level shifter for shifting the levels of R, G, and B data stored for each line in the hold register; A resistor string for inputting a reference voltage to generate a plurality of gray voltages; A gradation voltage controller for inputting a gradation voltage generated from the resistor string to control the gradation voltage in accordance with an output signal applied from the mode selector; A digital-to-analog converter for selecting one of the gradation voltages output from the gradation voltage controller according to the output signal from the level shifter; A source driver for a liquid crystal display device comprising an output buffer for providing an output of the digital analog converter to an LCD panel is provided.

The digital analog converter is characterized in that the remaining bits other than the upper bits selected from the data selector are supplied with a high level or low level fixed data through a level shifter.

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings in order to describe the present invention in more detail.

2 is a block diagram of a source driver according to an exemplary embodiment of the present invention.

2, the source driver of the liquid crystal display according to the embodiment of the present invention is a data selector for selecting a predetermined bit of R, G, B data input from the outside by the output signal from the mode selector 180 A data register 110 for sequentially inputting and storing data from the data selector 170 according to an output signal from the shift register 100, and the data register 110 by a load signal LOAD. A hold register 120 for storing the R, G, and B data sequentially stored in each line at a time, and a level shifter 130 for shifting the levels of the R, G, and B data stored for each line in the hold register 120. And the register string 190 for generating a plurality of gray voltages by inputting a reference voltage Vref, and the mode select by inputting the gray voltages generated from the register string 190. The gray voltage control unit 200 controls the gray voltage appropriately for the output signal applied from the emitter 180, and among the gray voltages output from the gray voltage control unit 200 by the output signal from the level shifter 130. Digital analog converter 150 to select one, and the output buffer 160 for providing the output of the digital analog converter 150 to the LCD panel.

The operation of the source driver as described above is as follows.

The data selector 170 selects only a predetermined bit among R, G, and B data of a predetermined bit input from the outside according to the output signal of the mode selector 180. For example, in case of source driver that supports maximum 6 bit mode and minimum 1 bit mode, in case of 1 bit mode, select only upper 1 bit among 6 bits of R, G, B data applied from outside and lower 5 bits are high Fixed to level or low level.

The output of the mode selector 170 is provided to the data register 110 according to a signal output from the shift register 100 so that the data register 110 sequentially stores R, G, and B data.

The R, G, and B digital data stored in the data register 110 are stored for each line in the hold register 120 by a load signal LOAD applied from the outside. The R, G, and B data for each line stored in the hold register 120 are provided to the level shifter 130 and level converted. The R, G, and B data level-converted through the level shifter 130 are provided to the digital analog converter 150.

For example, in the case where only one bit of 6-bit R, G, or B data is selected, conventionally, the highest 1 bit is copied by converting the most significant bit into 6-bit data through the data control unit 14. In the case of 1 ", the 6-bit data input to the data control unit 14 is 111111, which is provided to the digital analog converter 15 to select V0 or V63 among the gradation voltages.

However, in the present invention, if only the upper 1 bit is selected through the data selector 180 and the rest is fixed at a low level when the other is fixed at a high or low level, the digital shift converter 150 is connected to the digital analog converter 150 through the level shifter 130. 6-bit data of 000000 or 100000 is applied.                     

In this case, as shown in FIG. 3, the gray voltage controller 200 inputs the gray voltage generated from the resistor string 190 and controls the gray level voltage to an appropriate level by the output signal from the mode selector 170. Therefore, when the signal indicating that the 1-bit mode is selected through the mode selector 180 is applied, the gray voltage of V63 is output to the output signal V32 and the gray voltage of V0 is output to the output signal V0.

As described above, in the present invention, the gray voltage controller 200 is not directly connected to every channel, but is directly connected to the output terminal of the register string 190 that generates the gray voltage. Therefore, the gray voltage controller 200 Not only are they commonly connected to the input of the channel's multiplexer, the chip size can be significantly reduced, and power consumption can be significantly reduced by keeping unused data at high or low levels.

According to the source driver of the present invention as described above, instead of the data control unit connected to each channel, it is connected to the output terminal of the register string for generating the gradation voltage, thereby reducing the chip size and fixing the unused bits to a constant level. It has the advantage of reducing power consumption.

Although described above with reference to a preferred embodiment of the present invention, those skilled in the art will be variously modified and changed within the scope of the invention without departing from the spirit and scope of the invention described in the claims below I can understand that you can.

Claims (2)

A data selector for selecting predetermined bits of R, G, and B data input from the outside by an output signal from the mode selector; A data register for sequentially inputting and storing data from the data selector in accordance with an output signal from the shift register; A hold register for storing R, G, and B data sequentially stored in the data register by a load signal for each line at a time; A level shifter for shifting levels of R, G, and B data stored for each line in the hold register; A register string for inputting a reference voltage to generate a plurality of gray voltages; A gradation voltage controller configured to input a gradation voltage generated from the resistor string to control the gradation voltage according to an output signal applied from the mode selector; A digital-to-analog converter for selecting one of the gradation voltages output from the gradation voltage controller according to the output signal from the level shifter; And Output buffer that provides the output of the digital analog converter to the LCD panel A source driver for a liquid crystal display device, characterized in that consisting of. 2. The source driver of claim 1, wherein data fixed to a high level or a low level is applied to the digital analog converter through a level shifter except for a higher bit selected from the data selector.

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