KR100687489B1 - method for fabricating array substrate for a liquid crystal display device - Google Patents

Abstract

The present invention relates to a method for manufacturing an array substrate for a liquid crystal display device, and more particularly, to a method for manufacturing an array substrate for a liquid crystal display device using an element dispersing method, wherein the scattered element is formed on a substrate on which an etched groove is formed. By selectively sensing only the etching grooves in which the device is not seated, and filling the organic insulating material only in the etching grooves in which the device is not seated, to reduce the material cost used to planarize the substrate. Through this can increase the productivity of the product.

Description

Method for fabricating array substrate for a liquid crystal display device             

1 is an exploded perspective view of a general liquid crystal display device;

2 is a planar layout view of each terminal constituting the switching device,

3 is a circuit configuration diagram of the switching device,

4 is an exploded perspective view illustrating various modified examples of the nanoblocks that are switching devices;

5 is a cross-sectional view of a substrate on which a nanoblock and a receptor on which the nanoblocks are disposed are formed;

6 is a schematic plan view of an array substrate fabricated using a device scattering method,

7A to 7D are process cross-sectional views illustrating a planarization method of a substrate including an etching groove in which a conventional nanoblock is not mounted.

8A to 8B are cross-sectional views illustrating a planarization method of a substrate including an etching groove in which a nanoblock is not mounted according to the present invention.

<Description of Symbols for Main Parts of Drawings>

171: substrate 173: etching groove

175: nano block 179: organic insulating material

177: Inkjet Printer

BACKGROUND OF THE INVENTION 1. Field of the Invention [0001] The present invention relates to large area liquid crystal display devices, and more particularly, to large area liquid crystal display devices manufactured using fluid self assembly (FSA) technology.

1 is an exploded perspective view showing a general color liquid crystal display device.

As shown in the drawing, a general liquid crystal display 11 includes a color filter 7 including a black matrix 6, an upper substrate 5 on which a transparent common electrode 18 is formed, and a pixel region P. ) And a pixel electrode 17 formed on the pixel region, and a lower substrate 22 having a switching element T and array wiring formed therebetween, and the liquid crystal 14 between the upper substrate 5 and the lower substrate 22. Is filled.

The lower substrate 22 is also referred to as an array substrate, and the thin film transistor T, which is a switching element, is positioned in a matrix type, and the gate wiring 13 and the data wiring 15 passing through the plurality of thin film transistors cross each other. Is formed.

In this case, the pixel P area is an area defined by the gate line 13 and the data line 15 intersecting. A transparent pixel electrode 17 is formed on the pixel area as described above.

The pixel electrode 17 uses a transparent conductive metal having a relatively high light transmittance, such as indium-tin-oxide (ITO).

The thin film transistor T disposed on the array substrate performs deposition, photo-lithography, and etching for each component (gate electrode, gate wiring, insulating layer, active layer, etc.). Formed as a result of repeated iterations.

Many of these repetitive processes can cause short circuits and open circuits, and many risks such as distortion of the substrate and defects of the device must be considered during the process. There is a burden.

Therefore, the proposed method for fabricating the array substrate using a simple manufacturing process without going through such a complicated process is a fluid self assembly technique.

Briefly introducing the device scattering technology, the switching device is grown on a semiconductor material, such as silicon (Si) or gallium arsenide (GaAs) by a predetermined method, a plurality of the fabricated on a wafer made by cutting, and on the wafer A plurality of independent switching elements are formed separately from each other to form a plurality of chips, and this is a technique of forming the switching element on the array substrate by arranging it on the array substrate 22 by a predetermined method.

The process temperature of the array substrate to which the device spreading technique is applied is performed at a process temperature of 250 ^o at the maximum, thereby preventing shrinkage deformation of the substrate due to heat. The advantage is that there is no change in characteristics.

In addition, unlike conventional array substrate manufacturing process, the device manufacturing and wiring process may be disadvantageous, and thus, the factory area may be reduced by simplifying the production line, and the high yield characteristics of the large area array substrate may be obtained.

In addition, there is no deposition process for forming an active layer or insulator layer using chemical vapor deposition (CVD), which reduces the investment cost required for expensive equipment and the polymer instead of the insulating material formed by the chemical deposition. Since the organic insulating film, such as can be used to replace the insulating film, the cost is reduced.

The device scattering technology having such an advantage will be described below.

The thin film transistors used in the array substrate for the liquid crystal display device are made of a micro size on a wafer such as silicon or gallium arsenic, and are called nanoblocks because they are divided into blocks having a small size.

A receptor for preparing the transparent substrate having a predetermined size for arranging the switching device manufactured in the form of the block, and etching the portion in which the switching device is to be disposed by a predetermined method, may allow the nano block to be seated. To form. In this case, the receptor is manufactured according to the lower shape of the nanoblock. The substrate thus prepared is immersed in a fluid solution containing a surfactant, and nanoblocks are scattered on the substrate immersed in the fluid.

At this time, the nano-block flows along the fluid, thereby allowing the nanoblock to be seated on a plurality of receptors formed on the substrate, thereby forming a switching device on the substrate.

The structure and circuit diagram of the nanoblocks will be described with reference to FIGS.

2 is a schematic plan view showing a plane of a general nanoblock.

The nanoblock 20 has at least four thin film transistors.

Each symbol shown in the drawings is as shown in the table below.

TABLE 1

 P  Pixel terminal connected to pixel electrode  G1, G2, G3, G4 Gate electrode terminal corresponding to each thin film transistor Vc A common electrode terminal forming a storage capacitor together with each pixel electrode. D Source electrode terminal connected with data wiring.

Areas A, B, C, and D of FIG. 1 are independent thin film transistor areas including the above elements.

A circuit diagram and an operation of a nanoblock having a terminal as shown in Table 1 will be described with reference to FIG. 3.

3 is a circuit diagram illustrating four thin film transistors forming a nanoblock.

As shown, one data wiring terminal 33 is simultaneously connected to the four source connection wirings 25, 27, 29 and 32, and the gate electrode terminal for controlling the signal transmitted from the data wiring. G1, G2, G3, and G4 are formed, respectively.

In this case, each of the gate electrode terminals G1, G2, G3, and G4 is connected to each of the gate electrode connection wirings 13, 23, 26, and 28, and two gate electrode terminals are formed in a single thin film transistor with symmetry. . This is an expected design when the nanoblock is rotated and seated when seated on a receptor (not shown) of the substrate.

Each pixel electrode terminal P is connected to each drain electrode 31 spaced apart from the source electrode, which is then connected to a pixel electrode (not shown) formed on a substrate and transferred to the data wiring terminal 33. The data signal is transferred to the pixel electrode (not shown). A common voltage terminal Vc connected with the pixel electrode is present for each thin film transistor. The common voltage terminal Vc is a means for forming a storage capacitor 28 with the pixel electrode. If the storage capacitor 28 is not designed, a charge applied to switch the liquid crystal may leak and disappear in a short time after the signal is reached. Therefore, the design of the storage capacitor in the nanoblock is necessary.

The liquid crystal molecules are polarized according to inherent characteristics by an electric field due to a data voltage applied to the pixel electrode (not shown), and are arranged in a predetermined direction.

The shape of the nanoblock having such a configuration is shown in FIG. The nanoblocks have an area ratio between the top and bottom surfaces, and are formed in a trapezoidal shape in cross section. The nanoblock has a top and bottom surfaces having a rectangular rectangle 41, a rectangular parallelepiped 43, an ellipse or a circle 45, respectively.

The nanoblock is formed of a silicon wafer (Si wafer) or gallium arsenic wafer (GaAs wafer), and can be formed into the shape as described above by using a deposition process, a photolithography process and an etching process, respectively.

5 is a cross-sectional view showing a cross section of the nanoblock and the receptor.

As shown, the general cross-sectional shape of the nanoblock 47 is made in the shape of a trapezoid, the receptor 49 formed by etching a portion of the substrate 51 is inclined 47a of the side of the nanoblock 47 In consideration of the shape of the nanoblock is stable.

A configuration of an array substrate including a nanoblock, a gate wiring, a data wiring, and a pixel electrode having the circuit configuration of FIG. 3 will be described with reference to FIG. 6.

6 is a plan view of an array substrate using a nanoblock as a switching device.

As illustrated, the array process of the substrate 53 on which the nanoblocks (see 47 of FIG. 5) are arranged may include the pixel electrode terminal 34, the common voltage terminal 35, and the gate electrode of each of the nanoblocks 47. A process of forming a wiring connected to the terminal 24 and the source electrode terminal 33 is performed.

First, before performing the wiring process, a transparent insulating material such as benzocyclobutene (BCB) is coated on the entire surface of the substrate 53 on which the nanoblocks 47 are formed so that the nanoblocks 47 are separated from the substrate. The surface of the substrate 53 is planarized along with the prevention of the damage.

Next, a common electrode wiring connected to the common electrode terminal 35 by depositing and patterning a conductive metal material such as aluminum (Al), molybdenum (Mo), tungsten (W), and an aluminum alloy on the substrate 53. And a gate wiring 55 parallel to the common electrode wiring 54 and connected to the gate terminal 24 in one direction, and not parallel to the gate wiring 55. Forming a pixel connection wiring 61 connecting the data wiring 57 passing through the terminal 33 in one direction, the pixel terminal 29 of the nanoblock 47 and the pixel electrode 59 to be formed later;

Next, after forming the protective layer by depositing the above-described transparent insulating material on the entire surface of the substrate on which the data wiring 57, the pixel connection wiring 61, the gate wiring 55, etc. are formed, the pixel connection wiring 61 The pixel contact hole 63 is formed on the upper side of the?

Next, a transparent conductive metal such as indium tin oxide (ITO) or indium zinc oxide (IZO) is deposited and patterned on the entire surface of the substrate 53 on which the pixel contact hole 63 is formed. The pixel electrode 59 connected to the pixel terminal 34 is formed through the 63 and the pixel connection wiring 61. In this manner, an array substrate 53 for a liquid crystal display device using the nanoblock 47 as a switching element is completed.

The array process may be modified in various ways in consideration of the convenience of the process.

As described above, the array substrate for the liquid crystal display device formed by the device scattering technology is a method of fabricating and arranging the switching elements separately, so that the manufacturing process is very simple compared to the manufacturing process of the conventional thin film transistor type liquid crystal display device. have.

However, the problem of forming the receptor (see 49 in FIG. 5) for stably seating the nanoblock on the substrate on which the nanoblock is disposed, the problem of properly placing the nanoblock 47 in each receptor, and the like It is emerging as an important issue in dispersion technology.

Several methods have been proposed for seating the nanoblocks on the receptor, and during the process of mounting the nanoblocks in hundreds of thousands of receptors, a receptor in which the nanoblocks are not seated is generated.

After the nanoblocks are seated, defective disconnection of the wirings may occur due to the step difference between the receptors on which the nanoblocks are not seated while the nanoblocks are formed to connect the gate electrode terminals or the source electrode terminals.

In order to prevent this, conventionally, as described above, after the process of seating the nanoblocks on the receptor is completed, a method of repeatedly applying an organic insulating material onto the substrate on which the nanoblocks are seated is used to planarize it. It was.

Hereinafter, a description will be given with reference to FIGS. 7A to 7D.

As shown in FIG. 7A, a plurality of etching grooves (receptors) 73 are formed on the substrate 71 to seat the nanoblocks.

Next, as shown in FIG. 7B, the nanoblock 75 is seated in the etching groove 73 on the substrate 71 by using a predetermined method, in which the nanoblock 75 is not etched. Groove 73 is generated.

As described above, since the etching grooves may cause disconnection of the wiring, a step of eliminating the step by the etching grooves is necessary.

In addition, as shown in FIG. 7C, the organic blocks such as benzocyclobutene (BCB) and acryl are disposed on the substrate 71 so that the nanoblocks seated in the etching groove 71 do not escape from the substrate. The organic insulating layer 77 is formed on the substrate 71 on which the nanoblocks 75 are seated by applying and curing the material in the same manner as spin coating.

Since the spin coating method is a method of rotating the organic insulating material on the substrate 71 at high speed, the material consumption is very large, and the thickness of the coated organic insulating film is also very thin.

Therefore, since the step height of the etching grooves 73 on which the nanoblocks 75 are not seated is high, applying the organic insulating layer 77 once is insufficient to planarize the etching grooves 73.

Therefore, as shown in FIG. 7D, the substrate 71 can be planarized only by forming the organic insulating film 77 through several organic insulating material application steps.

However, this process causes a problem of lowering the price competitiveness by increasing the amount of material consumed by the process increase and spin coating.

Accordingly, in order to solve the above problems, the present invention aims to propose a method of planarizing the substrate in a simple process.

According to an aspect of the present invention, an array substrate for a liquid crystal display device includes: a substrate having a plurality of etching grooves formed therein; A plurality of nanoblocks mounted on a part of the plurality of etching grooves and configured with a plurality of switching elements; The nanoblocks of the plurality of etching grooves are filled in the etching grooves not seated, and include a planarization layer made of an organic insulating material.

The organic insulating material is characterized by being filled with an inkjet.

The method of manufacturing an array substrate for a liquid crystal display device according to the present invention is a planarization method of an array substrate for a liquid crystal display device including a switching element including a gate electrode, a drain electrode and a source electrode, and an etch groove in which a nanoblock having a capacitor is not seated. The method of claim 1, further comprising: sensing an etching groove in which the microelement block is not seated; And selectively filling the organic insulating material only in the sensed etching groove using an inkjet printer.

The organic insulating material is selected from the organic insulating material containing benzocyclobutene and acryl.

Hereinafter, exemplary embodiments of the present invention will be described with reference to the accompanying drawings.

Example

The present invention proposes a method of flattening a substrate by filling an organic insulating material directly into an etching groove in which the nanoblocks are not seated using an inkjet head.

Hereinafter, a process cross-sectional view of FIGS. 8A to 8B will be described.

As shown in FIG. 8A, after the device dispersing process is completed, an etching groove 173 in which the nanoblock 175 is not mounted is generated on the substrate 171.

As shown in FIG. 8B, the inkjet printer 177 is a means for sensing the etching groove 173 in which the nanoblock 175 is not seated and filling the etching groove 173 in which the nanoblock 175 is not seated. ).

That is, the etching groove 173 is filled with the organic insulating material 179 by using the inkjet printer 177 in the etching groove 173 in which the nanoblocks 175 are not seated to fill the etching groove 173.

As a result, the substrate 171 can be planarized in one step.

Through such a simple process, the substrate 171 on which the nanoblocks 175 are mounted may be planarized.

Next, an array substrate for a liquid crystal display device may be manufactured by forming a gate wiring, a data wiring, and a common voltage wiring connected to a terminal of the nanoblock 175 seated on the substrate 171 on the substrate.

Therefore, since the etching grooves in which the nanoblocks are not seated can be planarized in one step, a large amount of material may not be used to planarize the substrate on which the etching holes in which the nanoblocks are not seated are present. It has a reducing effect.

Claims (4)

A substrate on which a plurality of etching grooves are formed; A plurality of nanoblocks mounted on the plurality of etching grooves and configured with a plurality of switching elements; A planarization layer in which an organic insulating material is filled with an inkjet in the etching grooves in which the nanoblocks are not mounted among the etching grooves; Array substrate for a liquid crystal display device comprising a. delete A flattening method of an array substrate for a liquid crystal display device comprising a switching element including a gate electrode, a drain electrode and a source electrode, and an etch groove in which a nanoblock having a capacitor is not seated. Sensing the etch groove on which the nanoblock is not seated; Selectively filling the organic insulating material only in the etching grooves sensed using an inkjet printer; Method of manufacturing an array substrate for liquid crystal display device comprising The method of claim 3, wherein Wherein the organic insulating material is one selected from organic insulating materials including benzocyclobutene and acryl.

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