KR100684180B1 - Electro-static discharge protection circuit using silicon controlled rectifier - Google Patents

Abstract

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an electro-static discharge (ESD) protection circuit using a semiconductor controlled rectifier (SCR) applied to a semiconductor integrated circuit, wherein a first well and a second well are formed. Semiconductor substrates; First and second high concentration ion implantation regions formed on the first well; Third and fourth high concentration ion implantation regions formed on the second well; A fifth high concentration ion implantation region formed at the first well and second well interfaces; A sixth high concentration ion implantation region formed on the second well at one side of the fifth high concentration ion implantation region; A first overload in which a drain is connected to the sixth high concentration ion implantation region, a source is connected to the first and second high concentration ion implantation regions, and a gate is connected to the first and second high concentration ion implantation regions through a resistance. Prevention means; And a drain connected to the fifth high concentration ion implantation region, a source connected to the third and fourth high concentration ion implantation regions, respectively, and a gate connected to the third and fourth high concentration ion implantation regions through a resistor. 2 includes overload protection.

Electrostatic discharge (ESD), protection circuit, semiconductor controlled rectifier (SCR), zener junction diode, trigger voltage

Description

Electrostatic discharge protection circuit using silicon controlled rectifier

1 is a cross-sectional view of a device for explaining an example of a conventional electrostatic discharge protection circuit.

2 is a cross-sectional view of a device for explaining a conventional electrostatic discharge protection circuit using a semiconductor controlled rectifier.

3 is an equivalent circuit diagram of FIG. 2.

4 is a cross-sectional view of a device for explaining an electrostatic discharge protection circuit using a semiconductor controlled rectifier according to the present invention.

5 is an equivalent circuit diagram of FIG. 4.

FIG. 6 is a graph showing a change in current Ia with a change in anode voltage Va. FIG.

<Explanation of symbols for the main parts of the drawings>

1, 11, 21: semiconductor substrate

2: source

3: drain

4: gate insulating film

5: gate

6: silicide layer

12, 23: p well

13, 22: n well

14, 16, 24, 26, 28: n + region

15, 17, 25, 27, 29: p + region

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an electrostatic discharge (ESD) protection circuit for a low voltage circuit applied to a semiconductor integrated circuit, and more particularly, an electrostatic discharge using a semiconductor controlled rectifier (SCR). It relates to a protection circuit.

Electro-Static Discharge (ESD) phenomenon, in which high voltage is instantaneously introduced by electrostatic discharge generated due to contact of the human body, may be frequently generated during the production or use of semiconductor components or electronic products. When a high voltage flows into the semiconductor integrated circuit by electrostatic discharge, the device is severely affected or becomes inoperable, such as a thin insulating film being destroyed. Therefore, the electrostatic discharge phenomenon is a very important consideration in the design of semiconductor integrated circuits.

In particular, when the K sub-micron (DSM) unit is applied to the fabrication of high voltage-sensitive CMOS metal-oxide-semiconductor (CMOS) devices, the thickness of the gate oxide becomes thinner. The damage caused is expected to be more serious.

In general, an electrostatic discharge protection circuit applied to a semiconductor integrated circuit is configured to discharge through a discharge path before high voltage or high current flowing through an input terminal flows into internal circuits.

1 is a cross-sectional view of a ggNMOS (gate grounded NMOS) device for explaining an example of a conventional electrostatic discharge protection circuit.

An n + source 2 and a drain 3 having a lightly doped drain (LDD) structure are formed in the p-type semiconductor substrate 1, and a gate is formed on the semiconductor substrate 1 between the source 2 and the drain 3. A gate 5 electrically insulated from the semiconductor substrate 1 is formed by the insulating film 4. Silicide layers 6 are formed on the surfaces of the gate 5, the source 2, and the drain 3 to reduce contact resistance, and the source 2 and the drain 3 may include input / output pads S and D. ). All terminals except the drain 3 of the NMOS transistor formed as described above, that is, the gate 5 and the source 2 are connected to the ground and are discharged through the input / output pad D connected to the drain 3. ) Pulse is applied.

The electrostatic discharge protection circuit applied to the ggNMOS device includes an NPN bipolar transistor Q1 and a substrate resistor R1 formed by the source 2, the semiconductor substrate 1, and the drain 3.

The electrostatic discharge protection circuit configured as described above has a high electrostatic discharge protection effect due to the low trigger voltage and snapback operation characteristics. However, the low current discharge capability requires that the device be large in order to achieve a reliable level of electrostatic discharge protection. As the device size increases, parasitic capacitance components increase, resulting in poor driving capability and high integration.

Recently, an electrostatic discharge protection circuit using a semiconductor controlled rectifier (SCR) has been developed. Semiconductor controlled rectifiers are known for their excellent electrostatic discharge protection and low parasitic capacitor components, and are attracting attention as devices suitable for high speed and small size semiconductor integrated circuits.

FIG. 2 is a cross-sectional view of a device for describing a conventional electrostatic discharge protection circuit using a semiconductor controlled rectifier, and FIG. 3 is an equivalent circuit diagram of FIG. 2.

The p well 12 is formed in the p + type semiconductor substrate 11, and the n well 13 is formed in a predetermined portion of the p well 12. An n + region 14 and a p + region 15 are formed on the n well 13, and an n + region 14 and a p + region 15 are formed on the p well 12. The n + region 14 and the p + region 15 are used as the anode A, and the n + region 16 and the p + region 17 are used as the cathode C.

Therefore, the NPN bipolar transistor Q11 including the p + region 15, the n well 13, and the p well 12, and the n well 13, the p well 12, and the n + region 16. The semiconductor controlled rectifier is configured by the PNP bipolar transistor Q12. The resistor R11 is a resistive component of the n well 13, the resistor R12 is a resistive component of the p + type semiconductor substrate 11, and the resistor R13 is a resistive component of the p well 12.

As described above, the electrostatic discharge protection circuit using the semiconductor-controlled rectifier has much larger electrostatic discharge capacity than that of the ggNMOS device because the NPN and PNP bipolar transistors Q11 and Q12 form positive feedback. Have Therefore, it is possible to obtain an effective electrostatic discharge protection effect with a small area, and also to minimize the parasitic capacitance component has the advantage that is suitable for high frequency devices.

However, since the trigger (operating) voltage of the semiconductor controlled rectifier is high, such as 20 to 30V, it is difficult to effectively remove the electrostatic discharge pulse before the gate oxide film is destroyed in the MOSFET manufactured by the K submicron process. That is, since the endurance voltage of the integrated circuit manufactured by the process of the current K submicron unit is much smaller than 20V, when the electrostatic discharge pulse is applied, the MOSFET constituting the core circuit before the electrostatic discharge protection circuit is operated. The gate oxide film may be destroyed.

SUMMARY OF THE INVENTION An object of the present invention is to provide an electrostatic discharge protection circuit using a semiconductor controlled rectifier that can be applied to an integrated circuit of a highly integrated semiconductor device manufactured by a K submicron unit process.

Another object of the present invention is to provide an electrostatic discharge protection circuit using a semiconductor controlled rectifier which operates in a low voltage circuit and has a low trigger voltage.

Electrostatic discharge protection circuit using a semiconductor controlled rectifier according to the present invention for achieving the above object is a semiconductor substrate formed with a first well and a second well; First and second high concentration ion implantation regions formed on the first well; Third and fourth high concentration ion implantation regions formed on the second well; A fifth high concentration ion implantation region formed at the first well and second well interfaces; A sixth high concentration ion implantation region formed on the second well at one side of the fifth high concentration ion implantation region; A first overload in which a drain is connected to the sixth high concentration ion implantation region, a source is connected to the first and second high concentration ion implantation regions, and a gate is connected to the first and second high concentration ion implantation regions through a resistance. Prevention means; And a drain connected to the fifth high concentration ion implantation region, a source connected to the third and fourth high concentration ion implantation regions, respectively, and a gate connected to the third and fourth high concentration ion implantation regions through a resistor. It characterized in that it comprises two overload protection means.

Impurity ions of a first conductivity type are implanted into the first well, the first high concentration ion implantation region, the third high concentration ion implantation region, and the fifth high concentration ion implantation region, and the second well and the second high concentration ion Impurity ions of the second conductivity type are implanted into the implantation region, the fourth high concentration ion implantation region and the sixth high concentration ion implantation region.

In addition, the electrostatic discharge protection circuit using another semiconductor controlled rectifier according to the present invention for achieving the above object, the first transistor, the emitter is connected to the first terminal,

A first resistor connected between the collector and the second terminal of the first transistor,

A second resistor connected between the first terminal and the base of the first transistor,

A second transistor, an anode and a cathode connected between a base of the first transistor and the second terminal, the base of which is connected to a collector of the first transistor, and a base of the second transistor and a base of the first transistor. A Zener junction diode connected to each other, third and fourth resistors, a drain and a source connected to the first and second terminals, respectively, connected to an anode and the first terminal of the Zener junction diode, respectively, and a base connected to the first terminal. A third transistor, a drain, and a source connected to the third resistor are respectively connected to the cathode and the second terminal of the zener junction diode, and the base includes a fourth transistor connected to the fourth resistor.

The first terminal may be connected to the input / output pad, and the second terminal may be connected to the ground.

The first transistor may be a PNP bipolar transistor, the second transistor may be an NPN bipolar transistor, the third transistor may be a PMOS transistor, and the fourth transistor may be an NMOS transistor.

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings. The following embodiments are provided to those skilled in the art to fully understand the present invention, and may be modified in various forms, and the scope of the present invention is limited to the embodiments described below. no.

4 is a cross-sectional view of an element for describing an electrostatic discharge protection circuit using a semiconductor controlled rectifier according to the present invention, and FIG. 5 is an equivalent circuit diagram of FIG. 4.

The n well 22 and the p well 23, which are the first and second wells, are formed in the p-type semiconductor substrate 21. An n + region 24 that is a first high concentration ion implantation region and a p + region 25 that is a second high concentration ion implantation region are formed on the n well 22, and a third high concentration ion is formed on the p well 23. An implantation region n + region 28 and a fourth high concentration ion implantation region p + region 29 are formed. In addition, an n + region 26, which is a fifth high concentration ion implantation region, is formed on an upper surface of the n well 22 and the p well 23, and an upper portion of the p well 23 on the side of the n + region 26 is formed. 6 The p + region 27 which is a high concentration ion implantation region is formed. The n + region 24 and the p + region 25 are used as the anode A, and the n + region 28 and the p + region 29 are used as the cathode C.

Therefore, the PNP bipolar transistor Q21 including the p + region 25, the n well 22, and the p-type semiconductor substrate 21, and the n well 22, the p well 23, and the n + region 28 are formed. A semiconductor control rectifier is configured by the NPN bipolar transistor Q22 configured, and a Zener junction diode D1 composed of the p + region 27 and the n + region 26 is connected to the semiconductor control rectifier. Resistor R21 is a resistive component of the n well 22, and resistor R22 is a resistive component of the p-type semiconductor substrate 21, and biases of the PNP bipolar transistor Q11 and NPN bipolar transistor Q12, respectively. To provide.

In addition, a gate is connected between the p + region 27 and the n + region 24 and the p + region 25 through the resistor R23 to the n + region 24 and the p + region 25, and the drain is p +. In the region 27, a PMOS transistor P1 whose source is connected to the n + region 24 and the p + region 25 is connected, and the n + region 26 and the n + region 28 and the p + region 29 ) Is connected to the n + region 28 and the p + region 29 through the resistor R24, the drain is connected to the n + region 26, the source is the n + region 28 and p + region 29 The NMOS transistor N1 connected to is connected.

Semiconductor-controlled rectifiers are mainly used in power device applications because they have a property of changing from a high impedance state to a low impedance state, but when properly designed, very efficient electrostatic discharge protection can be obtained.

In FIG. 4, the semiconductor controlled rectifier including the PNP bipolar transistor Q21 and the NPN bipolar transistor Q22 has a simple PNPN structure. The P + region 25 formed in the n well 22 is used as an anode A, and the n + region 28 formed in the p well 23 is used as a cathode C. In this case, the anode A may be connected to the n + region 24 formed in the n well 22, and the cathode C may be connected to the p + region 29 formed in the p well 23. . That is, the PNP bipolar transistor Q21 includes an emitter having the anode A, a base having the n well 22 and a collector having the p-type semiconductor substrate 21. The NPN bipolar transistor Q22 includes an emitter as the cathode C, a base as the p well 23, and a collector as the n well 22.

A voltage Vc fixed to the n well 22, for example, a power supply voltage is applied, a voltage Va greater than or equal to the voltage Vc is applied to the anode A, and the cathode ( When C) and the p well 23 are connected to the ground, the change of the current Ia according to the change of the voltage Va applied to the anode A is shown in FIG. 6.

The operation of the electrostatic discharge protection circuit using the semiconductor control rectifier according to the present invention configured as described above will be described.

When an electrostatic discharge pulse flows through an input pad and the voltage Va of the anode A becomes greater than the voltage Vc, the p + region 25 and the n well 22 are forward biased. A current path is formed between the p + region 25 and the p-type semiconductor substrate 21. At this time, the emitter and the base of the PNP bipolar transistor Q21 become a forward bias due to the voltage drop through the resistor R21 of the n well 22, and the turn-on of the PNP bipolar transistor Q21 is turned on. As a result, current flows to the p-type semiconductor substrate 21. Therefore, holes supplied from the anode A move to the cathode C connected to the ground through the p-type semiconductor substrate 21 serving as a collector of the PNP bipolar transistor Q21.

In addition, when the NPN bipolar transistor Q22 is turned on due to the voltage drop caused by the resistor R22 of the p-type semiconductor substrate 21, electrons supplied from the cathode C connected to ground are thereby formed. It moves to the anode A through the NPN bipolar transistor Q22.

As the flow of electrons increases, the voltage drop caused by the resistor R21 is further increased to form a positive loop, thereby providing sufficient discharge. That is, since the NPN bipolar transistor Q22 is forward biased by the current flowing through the PNP bipolar transistor Q21 to the cathode C, the forward bias of the PNP bipolar transistor Q21 does not need to be held anymore. Thus, the voltage Va of the anode A is reduced to a minimum. At this time, the voltage Va of the anode A is called a holding voltage, and the holding voltage is determined by the current of the PNP bipolar transistor Q21.

In order to maintain the state when the semiconductor control rectifier including the PNP bipolar transistor Q21 and the NPN bipolar transistor Q22 is in the latch mode, the following condition must be satisfied.

및

는 NPN 바이폴라 트랜지스터(Q22) 및 PNP 바이폴라 트랜지스터(Q21)의 전류이득이다.here,

And

Is the current gain of the NPN bipolar transistor Q22 and the PNP bipolar transistor Q21.

Two important parameters in semiconductor controlled rectifiers are I _trig and V _h . I _trig is determined by the resistance R22 component of the p-type semiconductor substrate 21, and the resistance R22 component is determined by the thickness L and the concentration of the p-type semiconductor substrate 21. In addition, V _h is greatly influenced by the thickness L and the resistance R21 component of the n well 22. In general, CMOS devices fabricated in K submicron units have a value of 2-5V.

In order to trigger the semiconductor control rectifier, an avalanche breakdown is required in the n well 22 and the p + region 25, and the trigger voltage is the breakdown voltage of the n well 22 and the p-type semiconductor substrate 21. Is defined.

The electrostatic discharge protection circuit of the present invention includes a zener junction diode D1 connected between the gate of the PNP bipolar transistor Q21 and the gate of the NPN bipolar transistor Q22 constituting a semiconductor controlled rectifier. The zener junction diode D1, which is composed of a p + region 27 and an n + region 26 implanted with a high concentration of impurity ions, has a narrow bandgap, and thus has a breakdown voltage of about 5 to 6V lower than that of a general pn junction. Most depletion layers are formed in the p well 23. Therefore, the trigger voltage of the semiconductor controlled rectifier can be further reduced than before.

That is, when an electrostatic discharge pulse is applied to the anode A connected to the input pad, an electron hole pair is generated at a low voltage of 6 V or less by the zener junction diode D1 having a low breakdown voltage. The injected electrons and holes are injected into the n well 22 and the p well 23 to operate the PNP bipolar transistor Q21 and the NPN bipolar transistor Q22 in the forward direction to lower the trigger voltage.

In the electrostatic discharge protection circuit of the present invention, a PMOS transistor P1 is connected between the anode of the zener junction diode D1 and the anode A, and the cathode and the cathode of the zener junction diode D1 are connected. The NMOS transistor N1 is connected between (C). Thus, the drain is at the anode of the zener junction diode D1, the source is at the anode A, and the gate is at the n + region of the anode A and the n well 22 through the resistor R23. An overload (overcurrent) caused by a negative electrostatic discharge pulse is discharged by the PMOS transistor P1 connected to the 24 and p + regions 25, and the drain is supplied to the cathode of the zener junction diode D1. The NMOS transistor N1 having a source connected to the cathode C and a gate connected to the n + region 28 and the p + region 29 of the cathode C and the p well 23 through a resistor R24. This prevents overload (overcurrent) due to positive electrostatic discharge pulses.

In the absence of the PMOS transistor P1 and the NMOS transistor N1, the discharge path is formed when the voltage difference between the anode A and the cathode C is greater than the breakdown voltage of the zener junction diode D1. However, when the PMOS transistor P1 and the NMOS transistor N1 are added, a discharge path is formed even when the voltage difference between the anode A and the cathode C is smaller than the breakdown voltage of the zener junction diode D1. Can be. That is, when a discharge path is first formed through the PMOS transistor P1 and the NMOS transistor N1 having a low threshold voltage, and a voltage drop caused by the resistor R21 occurs, the PNP bipolar transistor Q21 and the NPN are as described above. A discharge path through the bipolar transistor Q22 is formed.

As described above, the preferred embodiment of the present invention has been disclosed through the detailed description and the drawings. The terms are used only for the purpose of describing the present invention and are not used to limit the scope of the present invention as defined in the meaning or claims. Therefore, those skilled in the art will understand that various modifications and equivalent other embodiments are possible from this. Therefore, the true technical protection scope of the present invention will be defined by the technical spirit of the appended claims.

Recently, as the K sub-micron unit process is introduced in the manufacture of semiconductor devices, the driving voltage and thickness of the insulating film are gradually decreased. Therefore, the damage caused by the electrostatic discharge is expected to be further increased. To this end, the development of an electrostatic discharge protection circuit driven at a low voltage and having a low trigger voltage is required.

Conventional electrostatic discharge protection circuits using semiconductor controlled rectifiers have high electrostatic discharge protection capability, but are difficult to apply to highly integrated devices due to the high trigger voltage. Therefore, the present invention connects a Zener junction diode between the gate of the PNP bipolar transistor and the NPN bipolar transistor constituting the semiconductor control rectifier to reduce the trigger voltage, emitters and gates of the PNP bipolar transistor and the NPN bipolar transistor and the zener The PMOS transistor and the NMOS transistor are connected to the junction diode, the anode, and the cathode, respectively, so that a discharge path can be formed even at an initial stage when an electrostatic discharge pulse is introduced. Therefore, an electrostatic discharge protection circuit having a low trigger voltage and a large discharge capacity can be easily implemented in a small area.

The present invention can be applied to nanoscale semiconductor integrated circuits to which a process of a K submicron unit is applied.

Claims (8)

A semiconductor substrate on which first wells and second wells are formed; First and second high concentration ion implantation regions formed on the first well; Third and fourth high concentration ion implantation regions formed on the second well; A fifth high concentration ion implantation region formed at the first well and second well interfaces; A sixth high concentration ion implantation region formed on the second well at one side of the fifth high concentration ion implantation region; A first overload in which a drain is connected to the sixth high concentration ion implantation region, a source is connected to the first and second high concentration ion implantation regions, and a gate is connected to the first and second high concentration ion implantation regions through a resistance. Prevention means; And A drain connected to the fifth high concentration ion implantation region, a source connected to the third and fourth high concentration ion implantation regions, respectively, and a gate connected to the third and fourth high concentration ion implantation regions through a resistor; Overload protection Electrostatic discharge protection circuit using a semiconductor controlled rectifier comprising a. The method of claim 1, wherein a first conductivity type impurity ions are implanted into the first well, the first high concentration ion implantation region, the third high concentration ion implantation region, and the fifth high concentration ion implantation region, and the second well. And an impurity ion of a second conductivity type is implanted into the second high concentration ion implantation region, the fourth high concentration ion implantation region, and the sixth high concentration ion implantation region. 3. The electrostatic discharge protection circuit according to claim 2, wherein the first conductivity type is n-type and the second conductivity type is p-type. 2. The electrostatic discharge protection circuit using a semiconductor controlled rectifier according to claim 1, wherein said first overload preventing means comprises a PMOS transistor and said second overload preventing means comprises an NMOS transistor. The electrostatic discharge protection circuit of claim 1, wherein the first and second high concentration ion implantation regions are connected to an input / output pad, and the third and fourth high concentration ion implantation regions are connected to ground. . A first transistor having an emitter connected to the first terminal, A first resistor connected between the collector and the second terminal of the first transistor, A second resistor connected between the first terminal and the base of the first transistor, A second transistor connected between the base of the first transistor and the second terminal, the base of which is connected to a collector of the first transistor, A zener junction diode having an anode and a cathode connected to a base of the second transistor and a base of the first transistor, respectively; Third and fourth resistors connected to the first and second terminals, respectively, A third transistor having a drain and a source connected to the anode of the zener junction diode and the first terminal, respectively, and a base of which is connected to the third resistor; And a fourth transistor having a drain and a source connected to a cathode of the Zener junction diode and the second terminal, respectively, and a base of which is connected to the fourth resistor. 7. The electrostatic discharge protection circuit of claim 6, wherein the first terminal is connected to an input / output pad and the second terminal is connected to ground. 7. The semiconductor controlled rectifier of claim 6, wherein the first transistor is a PNP bipolar transistor, the second transistor is an NPN bipolar transistor, the third transistor is a PMOS transistor, and the fourth transistor is an NMOS transistor. Electrostatic discharge protection circuit.

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