KR100672932B1 - Soi transistor and method of forming the same - Google Patents

Abstract

Disclosed are a silicon on insulator (SOI) transistor having a structure capable of maximizing a reduction in junction capacitance and minimizing parasitic components between devices, and a method of manufacturing the same. The SOI transistor of the new structure includes a buried insulating layer, a semiconductor region formed in a semiconductor layer stacked on the buried insulating layer, a gate electrode formed through a gate insulating film on the semiconductor layer, and semiconductor layers on both sides of the gate electrode. And a field insulating film formed around the source region and the drain region, and surrounding the source region and the drain region, wherein the source region and the drain region are in contact with the buried insulating layer so as to be separated from the semiconductor region.

Description

Silicon on insulator transistor and its manufacturing method {SOI TRANSISTOR AND METHOD OF FORMING THE SAME}

1 is a plan view illustrating an example of a conventional SOI transistor.

FIG. 2 is a cross-sectional view of the SOI transistor illustrated in FIG. 1 in the II-II 'direction.

3 is a cross-sectional view taken along the line III-III 'of the SOI transistor shown in FIG. 1.

4 is a plan view of an SOI transistor according to the present invention.

FIG. 5 is a cross-sectional view taken along the line VV ′ of the SOI transistor of the present invention shown in FIG. 4.

FIG. 6 is a cross-sectional view of the VI-VI ′ direction of the SOI transistor of the present invention shown in FIG. 4.

7A to 7D are cross-sectional views illustrating a method of manufacturing an SOI transistor according to the present invention.

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device and a method for manufacturing the same, and more particularly, to a silicon in insulator (SOI) transistor and a method for manufacturing the same.                         

In general, junction isolation is not suitable for high voltage devices due to the limitation of junction breakdown voltage, and is a high radiation environment due to the current generated at the PN junction by gamma rays (γ ray). Ineffective at Therefore, in a high performance device such as a central processing unit (CPU), a silicon on insulator (hereinafter referred to as " SOI ") technology is widely used to completely cover an electronic device with an insulator.

SOI technology is a technique for more effectively separating the semiconductor devices formed on the semiconductor substrate, forming a buried oxide layer on the silicon substrate, and then partially forming the upper silicon layer on the buried oxide layer, and then It is a technique of forming a semiconductor element in this upper silicon layer. This SOI technology can provide excellent radiation resistance and excellent high voltage resistance compared to semiconductor devices formed by junction isolation technology. In addition, there are generally fewer processes requiring semiconductor devices formed on SOI than semiconductor devices formed on bulk silicon, and reduced capacitive coupling between semiconductor devices formed in IC chips. There is this.

1 is a plan view illustrating an example of a conventional SOI transistor, and illustrates an example in which the design of a bulk transistor is applied to an SOI transistor. Reference numeral 2 denotes a well contact region for supplying a specific bias voltage to the well, “4” indicates a source region, “6” indicates a drain region, and “8” indicates a gate electrode.

FIG. 2 is a cross-sectional view in the II-II 'direction of the conventional SOI transistor shown in FIG. 1, and FIG. 3 is a cross-sectional view in the III-III' direction.

2 and 3, a P-type body region 14 made of a silicon layer formed on the buried oxide layer 12 is formed, and the gate electrode is interposed on the body region 14 via a gate insulating film 16. 18 is formed. The spacer 20 made of an insulator is formed on the side of the gate electrode. In addition, a source region 24 and a drain region 26 are formed in each of the silicon layers below both sides of the gate electrode 18, and a field oxide film 28 is formed on the outside thereof to insulate the devices. Further, at one end of the silicon layer, a well contact region 22 for applying a predetermined bias to the silicon layer is formed.

As shown, all transistors are conventionally formed on the body region 14 by floating the source region, the drain region and the field oxide film from the buried oxide layer to form a contact also through the side of the device. Is connected. Therefore, compared with the device formed on the bulk silicon layer, the reduction of the junction capacitance is insignificant and it is difficult to expect substantial improvement in device performance. In addition, there are many difficulties in device fabrication due to latch-up or leakage current between the devices.

Accordingly, an aspect of the present invention is to provide an SOI transistor having a structure capable of maximizing a reduction in junction capacitance and minimizing parasitic components between devices.

Another object of the present invention is to provide a method of manufacturing an SOI transistor having a structure capable of maximizing a reduction in junction capacitance and minimizing parasitic components between devices.

In order to achieve the above object, a transistor of an SOI structure according to the present invention includes a buried insulating layer, a semiconductor region formed in a semiconductor layer stacked on the buried insulating layer, and a gate electrode formed on the semiconductor layer via a gate insulating film. And a source region and a drain region formed in the semiconductor layers on both sides of the gate electrode, and a periphery of the source region and the drain region, and at least part of the source region and the drain region so as to separate the source region and the drain region from the semiconductor region. And a field insulating film formed to contact the buried insulating layer.

In the present invention, bottom surfaces of the source region and the drain region contact the buried insulating layer. The field insulating layer in the periphery of the source region and the drain region is in contact with the buried insulating layer, and the field insulating layer in the region except for the source region and the drain region periphery is spaced apart from the buried insulating layer. In particular, the field insulating film around the gate electrode is preferably spaced apart from the buried insulating layer.

According to another aspect of the present invention, there is provided a method of manufacturing a SOI transistor, the method comprising: providing a SOI substrate including a buried insulating layer and a semiconductor layer formed on the buried insulating layer; Forming a first mask layer for defining an inactive region, etching a portion of the semiconductor layer of the inactive region, and forming a body contact on a result of the etching of the portion of the semiconductor layer. Forming a second mask layer defining a region, etching the semiconductor layer in an area in which the body contact is not formed among the inactive regions, exposing the buried insulating layer, and etching the semiconductor layer Forming a field insulating film in the region, forming a gate electrode through the gate insulating film on the semiconductor layer, and implanting impurities into the semiconductor layer Forming a source region, a drain region, and a well contact region.

In the present invention, the second mask layer is formed in such a manner that the semiconductor layer around the source region and the drain region is exposed by the first mask layer and the second mask layer. In particular, the second mask layer is preferably formed on the semiconductor layer around both ends of the gate electrode. The forming of the field insulating film may include forming an insulating film on the entire surface of the resultant in which the semiconductor layer is etched and planarizing an upper portion of the insulating film by using a chemical-physical polishing (CMP) process.

Hereinafter, the present invention will be described in more detail with reference to the accompanying drawings.

4 is a plan view of an SOI transistor according to the present invention, in which reference numeral “32” denotes a well contact region for applying a predetermined bias voltage to a well, and “34” and “36” denote a source region and a drain; Area, and "38" represents a gate electrode, respectively. In the figure, the area 40 indicated by a dot indicates an area where the field oxide film is in contact with the buried oxide layer. That is, the peripheral portions of the source region and the drain region represent regions covered by the field oxide film.                     

FIG. 5 is a cross-sectional view of the SOI transistor according to the present invention shown in FIG. 4 in the V-V 'direction, and FIG. 6 is a cross-sectional view in the VI-VI' direction.

5 and 6, the source region 54 and the drain region 56, and the field oxide film 58b (indicated by dots) adjacent to the source region and the drain region, respectively, are formed to contact the buried oxide layer 42. The remaining field oxide film 58a including both ends of the gate electrode 48 is formed to be spaced apart from the buried oxide layer 42. In particular, as shown in FIG. 5, the field oxide films 58a around both ends of the gate electrode 48 are formed to be spaced apart from the buried oxide layer 42, so that charges are transferred through the body region 44 of the portion.

As shown, according to the SOI transistor of the present invention, since the source region and the drain region except for the both ends of the gate electrode are not in contact with the body region by the field oxide film 58b, the charge is transferred only through both ends of the gate electrode. Delivery takes place. Therefore, the junction capacitance and the leakage current at the side of the source region and the drain region can be greatly reduced, and the latchup phenomenon can be prevented.

Unexplained reference numeral 46 designates a gate insulating film, 48 designates a gate electrode, 50 designates a spacer, and 52 designates a well contact region, respectively.

7A to 7D are cross-sectional views conveniently illustrating together a body contact region and a region where no body contact is formed in order to explain a method of manufacturing an SOI transistor according to the present invention, and the same reference numerals as in FIGS. Indicates.

Referring to FIG. 7A, first, an SOI substrate including a buried oxide layer 42 and a silicon layer 44 forming a body region is formed using a conventional method. The SOI substrate can be formed by a conventional well-known method, for example, bonding a lower substrate formed by forming a buried oxide layer on a semiconductor substrate and an upper substrate formed of a silicon layer formed by a silicon epitaxial growth method. Then, the back surface of the lower substrate may be formed by grinding.

Next, a photoresist is applied on the silicon layer 44 forming the body region, and then a photolithography process is performed to form a first photoresist pattern 45 for defining an inactive region. Next, the silicon layer 44 is etched using the first photoresist pattern 45 as a mask to form a trench. At this time, the silicon layer 44 is not completely etched to expose the surface of the buried oxide layer 42 as in the related art, but only about half of the silicon layer 44 is etched as shown.

Referring to FIG. 7B, a second photoresist pattern 47 is formed on the entire surface of the trench-formed resultant to apply photoresist again and perform a photo process to mask an area where a body contact is to be formed. . Next, using the first and second photoresist patterns 45 and 47 as masks, the silicon layer 44 in the exposed areas is completely removed to expose the surface of the buried oxide layer 42.

Referring to FIG. 7C, the first and second photoresist patterns 45 and 47 may be removed, and then an oxide layer, for example, may be deposited on the entire surface of the patterned silicon layer 44. Next, a chemical mechanical polishing (CMP) process is performed on the deposited oxide film. Then, in the region where the body contact is to be formed, the field oxide layer 58a is formed to a depth of about the middle of the silicon layer 44, and in the region where the body contact is not formed in the inactive region, the field oxide layer is in contact with the buried oxide layer 42. 58b is formed.

Referring to FIG. 7D, an oxide film is formed on the resultant on which the field oxide film is formed, and for example, a gate conductive material such as polysilicon is deposited, and then patterned sequentially to form the gate insulating film 46 and the gate electrode 48. Form. Next, a predetermined impurity ion is implanted into the silicon layer to form the body region 44, and impurities are ion implanted at a high concentration, so that a source region (not shown), a drain region (not shown), and a well contact ( 52), respectively.

Although the present invention has been described in detail above, the present invention is not limited to the above-described embodiments, and many modifications are possible by those skilled in the art within the technical idea to which the present invention pertains.

According to the SOI transistor and the manufacturing method thereof according to the present invention described above, since the source region and the drain region of the portions excluding the edges of the gate electrodes are not in contact with the body region, the junction capacitance at the side of the source region and the drain region is reduced. Can be greatly reduced. In addition, since the charge is transferred only through both ends of the gate electrode, the leakage current can be reduced and the latch-up phenomenon can be prevented.

Claims (8)

Investment insulation layer; A semiconductor layer having a semiconductor region formed on said buried insulating layer; A gate electrode formed on the semiconductor layer via a gate insulating film; Source and drain regions formed on the semiconductor layers on both sides of the gate electrode; And And a field insulating film surrounding a periphery of the source region and the drain region, the at least part of which is in contact with the buried insulating layer so as to separate the source region and the drain region from the semiconductor region. (SOI) transistor. The silicon on insulator (SOI) transistor of claim 1, wherein bottom surfaces of the source and drain regions contact the buried insulating layer. The method of claim 1, wherein the field insulating film around the source region and the drain region is in contact with the buried insulating layer, And the field insulating film in a region except the periphery of the source region and the drain region is spaced apart from the buried insulating layer. The silicon on insulator (SOI) transistor of claim 3, wherein the field insulating film around both ends of the gate electrode is spaced apart from the buried insulating layer. Providing a SOI substrate comprising a buried insulating layer and a semiconductor layer formed on the buried insulating layer; Forming a first mask layer on the semiconductor layer to define an inactive region; Etching a portion of the semiconductor layer in the inactive region; Forming a second mask layer on the resultant portion of the semiconductor layer, which defines a region where a body contact is to be formed; Etching the semiconductor layer of the inactive region, in which the body contact is not formed, to expose the buried insulating layer; Forming a field insulating film in a region where the semiconductor layer is etched; Forming a gate electrode on the semiconductor layer with a gate insulating film interposed therebetween; And And implanting impurities into the semiconductor layer to form a source region, a drain region, and a well contact region. The method of claim 5, wherein the second mask layer, And forming the semiconductor layer on the periphery of the source and drain regions so as to be exposed by the first mask layer and the second mask layer. The method of claim 6, wherein the second mask layer, And forming a silicon on insulator (SOI) transistor on the semiconductor layer around both ends of the gate electrode. The method of claim 5, wherein the forming of the field insulating film, Forming an insulating film on the entire surface of the resultant of etching the semiconductor layer; And planarizing an upper portion of the insulating layer using a chemical-physical polishing (CMP) process.

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