KR100670551B1 - Capacitor-coupled level shifter circuit for a flat panel display driving cricuit - Google Patents

Abstract

The present invention relates to a capacitor coupled level shifter circuit in a flat panel display driving circuit.

The present invention includes a high voltage output control unit for outputting a constant voltage and switching a high voltage according to an input signal; And a high voltage output unit configured to output a high voltage as an output signal by switching of the high voltage output control unit.

Accordingly, the present invention provides a flat panel display (FPD) driving circuit, by using a level shifter coupled with a capacitor charged and discharged by a constant voltage when switching the low input signal IN to a high voltage VDDH. By preventing the occurrence of short-circuit current and rising propagation delay, the level shifter speeds up data processing and reduces power consumption.

Description

CAPACCITOR-COUPLED LEVEL SHIFTER CIRCUIT FOR A FLAT PANEL DISPLAY DRIVING CRICUIT}             

1 is a circuit diagram showing the configuration of a latch level shifter circuit commonly used in conventional flat panel display driving circuits.

2 is a circuit diagram showing the configuration of a capacitor coupling level shifter circuit in the flat panel display driving circuit of the present invention;

FIG. 3 is a graph showing a simulation result of rising and falling propagation delay time and power consumption accordingly.

4A and 4B are waveform diagrams showing waveforms of respective output signals with respect to voltage and current in the capacitor coupling level shifter of the present invention and the conventional latch level shifter;

5 is a table showing the characteristics of the capacitor coupling level shifter of the present invention and a conventional latch type level shifter.

*** Description of the symbols for the main parts of the drawings ***

10: high voltage output control unit 20: high voltage output unit

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a flat panel display driving circuit. In particular, in a flat panel display (FPD) driving circuit, a capacitor charged and discharged by a constant voltage when switching an input signal IN having a low voltage to a high voltage VDDH is included. The present invention relates to a capacitor coupled level shifter circuit in a flat panel display driving circuit which prevents occurrence of short-circuit current and rising propagation delay using a coupled level shifter.

In general, the driving voltage of most flat panel display (FPD) driving circuits is at least 10V and in some cases a high voltage of at least 100V, but an input signal including image data and control signals is 2.5V. Because of the relatively low voltage of about 3.3V at, the flat panel display driving circuit requires a level shifter circuit internally to interface between the low voltage and the high voltage.

As the data processing speed in the flat panel display driving circuit increases, the number of level shifters mounted therein is increasing. For example, a TFT-LCD having an UXGA format (1600 × 3 × 1200) has 6 bits having 480 outputs. Column driving circuits are commonly used, where at least 2,880 (= 6 x 480) level shifters are integrated in the column driving circuit.

Therefore, as the data processing speed in the flat panel display driving circuit improves, the power consumption of the level shifter or whether the high speed operation thereof becomes important becomes important.

1 is a circuit diagram showing the configuration of a latch-type level shifter circuit commonly used in a conventional flat panel display (FPD) driving circuit.

When the input signal IN having the 'LOW' state is input, the low voltage transistor LP1 is 'ON' and the high voltage transistor HN2 is 'ON' by the low voltage VDDL, and the high voltage transistor is turned on. The high voltage transistor HP1 is 'on' again by (HN2), and the other high voltage transistors HN1 and HP2 are turned 'off'.

When the input signal IN rises to the HIGH state, the low voltage transistor LN1 is turned on, and the high voltage transistor HN2 is turned off, and the high voltage transistor HN1 is turned on. do.

Here, at the moment when the high voltage transistor HN1 is 'on' and the high voltage transistor HN2 is 'off', the high voltage transistors HP1 and HP2 are still in the previous state, thereby maintaining 'on'. Short-circuit current flows through the high voltage transistor HP1 and the high voltage transistor HN1, which is currently 'on'.

After that, when the input signal IN falls back to the 'low' state, the path of the short circuit current is formed through the high voltage transistor HP2 and the high voltage transistor HN2 by the same principle.

Therefore, since the transistor has a latch structure, a short-circuit current occurs when switching the input signal IN, which consumes a lot of power.

On the other hand, when the input signal IN falls to the 'low' state, the voltage starts to fall as the high voltage transistor HN2 goes 'off' in the 'node OUT', so that the high voltage transistor HP1 Becomes 'on', and finally 'node OUTB' starts to rise to 'high' state by high voltage (VDDH).

This means that 'node OUTB' (or 'node OUT') can be switched to 'high' state only after the opposite 'node OUT' (or 'node OUTB') begins to descend to the 'low' state, The propagation delay it takes for the 'node OUTB' (or 'node OUT') to rise to the 'high' state becomes very large. In addition, a short circuit current flows during the propagation delay time.

Therefore, in the conventional technology as described above, in the case of a latch-type level shifter circuit used in a flat panel display (FPD) driving circuit, the transistor has a latch structure so that the input signal ( In the switching of IN), a relatively long propagation delay time is generated, and short-circuit currents are alternately generated during the propagation delay time, thereby lowering the data processing speed of the level shifter and consuming much power on its own. There was a problem.

Accordingly, the present invention has been proposed to solve the above-mentioned conventional problems. In the flat panel display (FPD) driving circuit, the present invention has a constant voltage when switching the low voltage input signal IN to the high voltage VDDH. It is an object of the present invention to provide a circuit for preventing short-circuit current and rising propagation delay from occurring by using a level shifter coupled with a capacitor charged and discharged by the capacitor.

The present invention for achieving the above object, the high-voltage output control unit for outputting a constant voltage in accordance with the input signal to switch the high voltage; And a high voltage output unit configured to output a high voltage as an output signal by switching of the high voltage output controller.

Hereinafter, an embodiment according to the present invention will be described in detail with reference to the accompanying drawings.

FIG. 2 is a circuit diagram showing a configuration of a capacitor coupled level shifter circuit in a flat panel display driving circuit according to the present invention. As shown in FIG. 2, a high voltage output control unit outputs a constant voltage according to an input signal IN to switch a high voltage VDDH. 10; The high voltage output controller 20 outputs a high voltage as an output signal OUT by the switching of the high voltage output controller 10.

Here, the high voltage output control unit 10 may include a Zener diode ZD connected in a reverse direction with respect to the high voltage VDDH to apply a high voltage VDDH to the cathode; One side is connected to an anode of the zener diode ZD, and the other side is composed of a coupling capacitor CC connected to the input signal IN.

In addition, the high voltage output unit 20 functions as an inverter to output the high voltage VDDH with respect to the input signal IN, a source is connected to the high voltage VDDH, and a gate is connected to the zener diode ZD. A PMOS transistor HP1 connected in common to the anode and having a drain connected to the output signal OUT; A drain is connected to the drain of the PMOS transistor HP1 in common, a gate is connected to the input signal IN, and a NMOS transistor HN1 having a source grounded.

The present invention can be applied to a flat panel display (FPD) driving circuit. When the present invention is applied, a capacitor is coupled to a level shifter when switching an input signal IN of a low voltage to a high voltage VDDH. By using a coupled level shifter to prevent short-circuit currents and rising propagation delays, the level shifter speeds up data processing and reduces power consumption.

Prior to the operation of the present invention, the reset transistor HR is driven through the reset signal RESET to initialize 'node NP' in the high voltage output controller 10 to the ground level.

After initialization, the high voltage output control unit 10 outputs a constant voltage according to a low voltage input signal IN to switch the high voltage VDDH, thereby switching the high voltage output control unit 10 from the high voltage output control unit 10. Outputs the high voltage to the output signal OUT. First, when the input signal IN goes to the 'LOW' state, the high voltage VDDH and the zener diode ZD are applied to the 'node NP' which is at the ground level. A voltage corresponding to a difference (ie, VDDH-Vz) of a Zener breakdown voltage (Vz) generated by) is applied.

At this time, since the input signal IN is 'low', the coupling capacitor CC is charged by the voltage applied to the 'node NP'.

Here, when the zener breakdown voltage Vz of the zener diode ZD has a voltage level similar to that of the input signal IN, the PMOS transistor HP1 of the high voltage output unit 20 is 'ON' and output. The signal OUT is output in the 'HIGH' state by the high voltage VDDH.

On the other hand, when the input signal IN becomes 'high' state, the voltage applied to the 'node NP' is raised to almost the high voltage VDDH level by the capacitor coupling to the PMOS transistor HP1 of the high voltage output unit 20. 'Off'.

In addition, the PMOS transistor HP1 is turned off and the NMOS transistor HN1 is turned on by the input signal IN, so that the high voltage output unit 20 outputs the output signal OUT. Will fall to the 'low' state.

That is, the above operation is similar to that of a general inverter, so that a short-circuit current path and a propagation delay that occur in a level shifter of a conventional latch structure do not occur.

Here, most of the supply current of the capacitor coupling level shifter is generated due to the capacitor coupling between the junction capacitor and the coupling capacitor CC generated inside the zener diode ZD, and thus an input signal IN is generated. When falling, the charge is taken from the power supply, and when the input signal IN rises, the charge is pushed toward the power supply.

Meanwhile, FIG. 3 is a graph showing a simulation of a rising and falling propagation delay time and power consumption accordingly. The high voltage VDDH is 10V, the input signal IN is 3.3V, and the load ( load) is assumed to be absent.

Here, the x-axis represents the width of the NMOS transistor as the ratio of the width of the PMOS transistor. In general, as the width ratio of the transistor increases, the rising propagation delay time is 'node OUT' and 'node'. It decreases due to the fast settling operation of OUTB ', but if the ratio exceeds "4", the rising propagation delay time is due to the increase of parasitic capacitance component that is induced in the drain of high voltage transistors (HN1, HN2). It can be seen that the increase again.

In the present invention, the propagation delay time generated in the level shifter is reduced by reducing the width ratio between the NMOS transistor and the PMOS transistor.

FIG. 4 is a waveform diagram showing waveforms of output signals with respect to voltage and current in the capacitor coupling level shifter of the present invention and the conventional latch type level shifter, wherein the width ratio of the NMOS transistor and the PMOS transistor is "4" in the latch level shifter. And "2.5" in the capacitor-coupled level shifter, where a in FIG. 4a shows that the rise propagation delay time of the capacitor-coupled level shifter is much smaller than that of the latched level shifter, and b in FIG. Is small, which consumes less power overall.

And, since the width of the NMOS transistor in the capacitor coupled level shifter is smaller than the width of the PMOS transistor, the falling propagation delay time is slightly longer than that of the latched level shifter.

Therefore, the capacitor coupling level shifter of the present invention operates similarly to a conventional inverter, and significantly reduces the short circuit current and propagation delay time, as shown in the table of FIG. 5, thereby reducing the power consumption of the capacitor coupled level shifter. Compared to the latched level shifter, the propagation delay time is reduced by 12.3% and 34.6%.

As described above, the present invention provides a flat panel display (FPD) driving circuit, in which a capacitor charged and discharged by a constant voltage is coupled when switching a low voltage input signal IN to a high voltage VDDH. By using the shifter, short-circuit current and rising propagation delay are prevented from occurring, thereby improving the data processing speed of the level shifter and reducing power consumption.

Claims (4)

delete A level shifter circuit for outputting a high voltage driving voltage in accordance with a low voltage input signal in a flat panel display driving circuit, Including a high voltage output control unit and a high voltage output unit, The high voltage output controller includes a Zener diode connected in a reverse direction with respect to a high voltage to which a high voltage is applied to a cathode, and a coupling capacitor having one side connected to an anode of the Zener diode and the other side connected to an input signal. and, The high voltage output unit includes two transistors which function as an output signal by outputting the high voltage as an inverter function with respect to the low voltage input signal, A first transistor of the two transistors connects a high voltage and an output terminal, a gate of the first transistor is connected to an anode of the zener diode, and a second transistor connects a ground terminal and the output terminal. The gate of the transistor is connected to the input signal, According to the high / low state of the low voltage input signal, a voltage value applied to the node to which the anode of the zener diode and the coupling capacitor are connected in the high voltage output control unit is variable, and the high voltage output unit according to the voltage value of the node. The first transistor is turned on / off, and at the same time, the second transistor of the high voltage output part is turned on / off according to the high / low state of the low voltage input signal, and the high voltage output part outputs a high voltage as a driving voltage. A capacitor coupled level shifter circuit in a flat panel display driving circuit. delete The PMOS transistor of claim 2, wherein a first transistor of the two transistors included in the high voltage output unit has a source connected to a high voltage, a gate connected to the anode of the zener diode, and a drain connected to the output terminal. ego; The second transistor is an NMOS transistor having a drain connected in common with the drain of the PMOS transistor, a gate connected to an input signal, and a source grounded.

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