CN112350710A

CN112350710A - Improved level shifter for integrated circuits

Info

Publication number: CN112350710A
Application number: CN201910733363.9A
Authority: CN
Inventors: 梅杰; C·朱; X·钱
Original assignee: Silicon Storage Technology Inc
Current assignee: Silicon Storage Technology Inc
Priority date: 2019-08-09
Filing date: 2019-08-09
Publication date: 2021-02-09

Abstract

The invention provides an improved level shifter for an integrated circuit. The present invention discloses an improved level shifter for use in an integrated circuit. The level shifter is capable of achieving switching times below 1ns while still using the core supply voltages VDDL and VDDH used in the prior art. The improved level shifter includes a coupling stage and a level shifting stage.

Description

Improved level shifter for integrated circuits

Technical Field

The present invention discloses an improved level shifter capable of operating at high speed.

Background

Level shifters are important components in integrated circuits. The level shifter converts the digital signal from the first voltage domain into the second voltage domain, which is an essential function when different parts of the integrated circuit operate in different voltage domains.

Fig. 1 shows a prior art level shifter 100. In the present example, "1" is represented by 1V and "0" is represented by 0V in the voltage domain 101, and "1" is represented by 2.5V and "0" is represented by 0V in the voltage domain 102. The level shifter 100 converts "1" in the voltage domain 101(1V) to "1" in the voltage domain 102(2.5V), and converts "0" in the voltage domain 101(0V) to "0" in the voltage domain 102. Other voltage domains are known that utilize other voltages to represent "1" and "0," and those of ordinary skill in the art will appreciate that the voltage values provided in FIG. 1 and herein are merely examples.

An implementation of the level shifter 100 will now be described with reference to fig. 2-4. First, FIG. 2 shows

inverters

201 and 202, where inverter 201 receives INPUT as a signal and produces A as an output (which is the complement of INPUT), and inverter 202 receives A as an INPUT and produces A-BAR as an output (which is the complement of A and is logically the same as INPUT). Here, a "1" value will have a voltage VDDL, which may be, for example, 1V. VDDL may be a low voltage core supply voltage.

Fig. 3 shows a prior art level shifter 300, which is an example of the level shifter 100. The level shifter 300 includes

NMOS transistors

301 and 302,

PMOS transistors

303 and 304, and an inverter 305. Signal a from fig. 2 is provided to the gate of NMOS transistor 301, and signal a-BAR from fig. 2 is provided to the gate of NMOS transistor 302.

When a is high, the NMOS transistor 301 will be turned on, and the transistor 302 will be turned off. The input of inverter 305 will be pulled to ground through NMOS transistor 301, which will also turn on to the gate of PMOS transistor 304. The OUTPUT of inverter 305, labeled OUTPUT, will be high, here will be the voltage VDDH, which may be, for example, 2.5V. VDDH may be a high voltage core supply voltage.

When a is low, the NMOS transistor 301 will be off, and the NMOS transistor 302 will be on. The PMOS transistor 303 will turn on because its gate will be pulled to ground through the NMOS transistor 302, which will cause the input of the inverter 305 to be pulled high through the PMOS transistor 303. OUTPUT will then be low.

The prior art level shifter 300 has significant drawbacks. In particular, the level shifter 300 cannot operate at a switching time of less than about 0.5 nanoseconds (ns). In the worst case, the switching time may be up to 1ns or more. This is due to the inherent variability in the current drive capability of each transistor. In addition, if the peak voltages of A and A-BAR are too low due to the low supply voltage VDDL in FIG. 2, the level shifter 300 may fail completely.

Fig. 4 depicts a prior art level shifter 400, which is another example of level shifter 100 and has a shorter switching time than level shifter 300. The level shifter 400 includes

NMOS transistors

401 and 402;

PMOS transistors

403, 404, 405, and 406; and an inverter 407. Signal a from fig. 2 is provided to the gate of NMOS transistor 401 and the gate of PMOS transistor 405, and signal a-BAR from fig. 2 is provided to the gate of NMOS transistor 402 and the gate of PMOS transistor 406.

When a is high, NMOS transistor 401 will turn on, transistor 402 will turn off, PMOS transistor 405 will turn off, and PMOS transistor 406 will turn on. The input of inverter 407 will be pulled to ground through NMOS transistor 401, which will also pull the gate of PMOS transistor 404 low, thereby turning on PMOS transistor 404, which in turn will cause the gate of PMOS transistor 403 to be pulled high to VDDH through

PMOS transistors

404 and 406. The OUTPUT of inverter 407, labeled OUTPUT, will be high, here will be the voltage VDDH, which may be, for example, 2.5V.

When a is low, NMOS transistor 401 will be off, NMOS transistor 402 will be on, PMOS transistor 405 will be on, and PMOS transistor 406 will be off. PMOS transistor 403 will turn on because its gate will be pulled to ground through NMOS transistor 402, which will cause the input of inverter 407 to be pulled up to VDDH through

PMOS transistors

403 and 405. OUTPUT will then be low.

Although the level shifter 400 has a faster switching time than the level shifter 300, the level shifter 400 is still limited. In particular, it cannot reduce the switching time below 1 ns. Furthermore, if the peak voltages of A and A-BAR are too low due to the low supply voltage VDDL in FIG. 2, the level shifter 400 may fail completely.

What is needed is an improved level shifting design that can reduce its switching time below 1ns while still using the same core supply voltages VDDL and VDDH used in the prior art.

Disclosure of Invention

The invention discloses an improved level shifter. The level shifter is capable of achieving switching times below 1ns while still using the core supply voltages VDDL and VDDH used in the prior art. The improved level shifter includes a coupling stage and a level switching stage.

Drawings

Fig. 1 shows a prior art level shifter.

Fig. 2 shows a prior art set of inverters.

Fig. 3 shows a prior art level shifter.

Fig. 4 shows another prior art level shifter.

Fig. 5 shows a level shifter.

Fig. 6 shows a coupling stage of the level shifter of fig. 5.

Fig. 7 shows a level shifting circuit of the level shifter of fig. 5.

Fig. 8 shows a level shifting method.

Detailed Description

Fig. 5 shows a level shifter 500 comprising a coupling stage 600 and a level shifting stage 700. When the level shifter 500 receives "0" as an input (where "0" is a first voltage), it outputs "0", i.e., a first voltage, and when it receives "1" of the first voltage domain (VDDL), which is a second voltage, as an input, it outputs "1" of the second voltage domain (VDDH), which is a third voltage different from the first voltage or the second voltage.

Fig. 6 shows a coupling stage 600 comprising a first circuit 621 and a second circuit 622, both powered by a low voltage power supply 610, the low voltage power supply 610 outputting a voltage VDDL. The first circuit 621 includes an NMOS transistor 602;

PMOS transistors

604, 606, and 608; and a capacitor 610. The second circuit 622 includes an NMOS transistor 601;

PMOS transistors

603, 605, and 607; and a capacitor 609. The signal a from fig. 2 is supplied to the gates of the NMOS transistor 601 and the PMOS transistor 603, and the signal a-BAR from fig. 2 is supplied to the gates of the NMOS transistor 602 and the PMOS transistor 604.

The operation of the first circuit 621 will now be described. When A is high, A-BAR is low, and NMOS transistor 602 is off, PMOS transistor 604 is on, and PMOS transistor 608 is off. The voltage AA will be floating because both NMOS transistor 602 and PMOS transistor 608 are off and will be about 0V in the initial state after start-up because any residual charge on capacitor 610 will dissipate without any power supply.

When A switches from high to low, A-BAR will switch from low to high, NMOS transistor 602 will turn on, PMOS transistor 604 will turn off, and PMOS transistor 608 will turn on because signal A is provided to the gate of PMOS transistor 608. The PMOS transistor 606 will also turn on because its gate will be pulled to ground through the NMOS transistor 602. Capacitor 610 will begin to charge and the node labeled AA will be near voltage VDDL because PMOS transistor 606 will turn on and be coupled to the supply providing VDDL through PMOS transistor 608. The source of NMOS transistor 602 has been described above as being grounded, however, this is not meant to be limiting in any way and any return voltage related to VDDH may be utilized instead of ground throughout the document without going beyond the scope. The first voltage, i.e., "0" in the second voltage domain, is a voltage close to the return voltage.

When A then switches from low to high, the A-BAR will switch from high to low. NMOS transistor 602 will turn off, PMOS transistor 604 will turn on, and PMOS transistor 608 will turn off because a is provided to the gate of PMOS transistor 608. The gate of PMOS transistor 606 will be at voltage AA (will start from VDDL) and will be off. Since a drives the top plate of capacitor 610 from low to high (which is VDDL), AA will be driven to 2 × VDDL through capacitor 610.

When a then switches from high to low, the PMOS transistor 608 will turn on, the NMOS transistor 602 will turn on, pulling the gate of the PMOS transistor 606 to ground and turning on the PMOS transistor 606, which pulls the node AA to the voltage VDDL.

The operation of the second circuit 622 will now be described. When A is low, A-BAR will be high, NMOS transistor 601 is turned off, PMOS transistor 603 is turned on, and PMOS transistor 607 is turned off because A-BAR is provided to its gate. The voltage AA-BAR will be floating because both NMOS transistor 601 and PMOS transistor 607 are off and will be about 0V in the initial state after start-up, because any residual charge on capacitor 610 will dissipate without any power supply.

When a switches from low to high, a-BAR will switch from high to low, NMOS transistor 601 will turn on, PMOS transistor 603 will turn off, and PMOS transistor 607 will turn on because a-BAR is provided to its gate. PMOS transistor 605 will also turn on because its gate will be pulled to ground through NMOS transistor 601. The bottom plate of capacitor 609 will be pulled to VDDL through

PMOS transistors

607 and 605 and the node labeled AA-BAR will get the voltage VDDL.

When A is then switched from high to low, A-BAR will switch from low to high, NMOS transistor 601 will turn off, PMOS transistor 603 will turn on, and PMOS transistor 607 will turn off since A-BAR is provided to its gate. The gate of PMOS transistor 605 will be at voltage AA-BAR (which will start from VDDL) through PMOS transistor 603 and will therefore be off. Since the a-BAR drives the top plate of capacitor 609 from low to high (i.e., VDDL), the AA-BAR will be driven to 2 × VDDL through capacitor 609.

When A is then switched from low to high, the A-BAR will switch from high to low, the PMOS transistor 607 will turn on, and the NMOS transistor 601 will turn on, pulling the gate of PMOS transistor 605 to ground and turning on PMOS transistor 605, which pulls node AA-BAR to the voltage VDDL through

PMOS transistors

605 and 607.

Thus, node AA will oscillate between VDDL and 2 VDDL, and node AA-BAR will oscillate between 2 VDDL and VDDL.

Fig. 7 shows a level-shifting stage 700 comprising

NMOS transistors

701, 702, 703, and 704,

PMOS transistors

705 and 706, and a high supply 710 that outputs a voltage VDDH. The signal a from fig. 2 is supplied to the gate of the NMOS transistor 701 and one terminal of the NMOS transistor 704. The signal a-BAR from fig. 2 is supplied to the gate of the NMOS transistor 702 and one terminal of the NMOS transistor 703. Node AA from fig. 5 is provided to the gate of NMOS transistor 703 and nodes AA-BAR from fig. 5 are provided to the gate of NMOS transistor 704. Likewise, node AA will oscillate between VDDL and 2 VDDL, and node AA-BAR will oscillate between 2 VDDL and VDDL.

When a switches from 1(VDDL) to 0, a-BAR will switch from 0 to 1(VDDL), AA will be VDDL, and AA-BAR will be 2 × VDDL. NMOS transistor 701 will turn off, NMOS transistor 702 will turn on, NMOS transistor 703 will turn off (since AA and a-BAR will both be VDDL), and NMOS transistor 704 will turn on. This will pull node OUTPUT to ground through

transistors

702 and 704.

When a switches from 0 to 1(VDDL), a-BAR will switch from 1 to 0, AA will be 2 × VDDL, and AA-BAR will be VDDL. NMOS transistor 701 will turn on, NMOS transistor 702 will turn off, NMOS transistor 703 will turn on, and NMOS transistor 704 will turn off (since both a and AA-BAR will be VDDL), and NMOS transistor 704 will turn off. The gate of PMOS transistor 706 will be pulled to ground through

NMOS transistors

701 and 703, which will turn on PMOS transistor 706 and cause OUPUT to be pulled to VDDH.

Notably, when a switches from 1 to 0,

NMOS transistors

702 and 704 are able to pull node OUTPUT to ground faster than

level shifters

300 and 400 because the overdrive voltage of NMOS transistor 704 is twice as high. Specifically, Vgs of pull-down NMOS transistor 704 is 2 × VDDL, while Vgs of NMOS transistor 302 and Vgs of NMOS transistor 402 in level shifter 400 are only VDDL. Thus, OUTPUT in level shifter 700 may be pulled to "0" faster than in level shifter 400.

Similarly, when a switches from 0 to 1,

NMOS transistors

701 and 703 can pull the gate of PMOS transistor 706 to ground faster than

level shifters

300 and 400 because the overdrive voltage of NMOS transistor 703 is twice as high. Therefore, OUTPUT is pulled to VDDH in a short time. Specifically, Vgs of pull-down NMOS transistor 703 is 2 × VDDL, while Vgs of NMOS transistor 301 in level shifter 300 and Vgs of NMOS transistor 401 in level shifter 400 are only VDDL. Therefore, the gate of PMOS transistor 706 will be pulled down to "0" quickly, and OUTPUT will be pulled to VDDH faster than in

level shifters

300 and 400.

That is, the level shifter 500 is able to switch faster than the

level shifters

300 and 400, which means that the switching time required for the level shifter 500 is less than the switching time required for the

level shifters

300 and 400.

Applicants have conducted experiments to compare the shifting speeds of the level shifter 500 with the prior

art level shifters

300 and 400. For the conditions of VDDL 0.94V to 1.26V, VDDH 1.4V to 2.75V, temperature-40 ℃ to 160 ℃, the level shifter 500 is 3.5 times faster when a switches from 0 to 1 and the level shifter 500 is 5.7 times faster when a switches from 1 to 0. Thus, the switching time of the level shifter 500 is at least 3.5 times faster than the

level shifters

300 and 400.

Fig. 8 illustrates a level shifting method 800, which may be implemented using the level shifter 500. The first step is to receive an input of a first voltage domain, where a "0" in the first voltage domain is a first voltage (e.g., 0V) and a "1" in the first voltage domain is a second voltage (e.g., 1V) (step 801). The second step is to generate a switching voltage equal to twice the second voltage (step 802). The third step is to generate an output of a second voltage domain using the switching voltage, where "0" in the second voltage domain is the first voltage and is generated when the input is "0", and "1" in the second voltage domain is a third voltage (e.g., 2.5V) and is generated when the input is "1" (step 803).

It should be noted that as used herein, the terms "above …" and "above …" both inclusively encompass "directly on …" (with no intermediate material, element, or space disposed therebetween) and "indirectly on …" (with intermediate material, element, or space disposed therebetween). Similarly, the term "adjacent" includes "directly adjacent" (no intermediate material, element, or space disposed therebetween) and "indirectly adjacent" (intermediate material, element, or space disposed therebetween), "mounted to" includes "directly mounted to" (no intermediate material, element, or space disposed therebetween) and "indirectly mounted to" (intermediate material, element, or space disposed therebetween), and "electrically coupled to" includes "directly electrically coupled to" (no intermediate material or element therebetween that electrically connects the elements together) and "indirectly electrically coupled to" (intermediate material or element therebetween that electrically connects the elements together). For example, forming an element "over a substrate" can include forming the element directly on the substrate with no intervening materials/elements therebetween, as well as forming the element indirectly on the substrate with one or more intervening materials/elements therebetween.

Claims

1. A level shifter for receiving an input of a first voltage domain and generating an output of a second voltage domain, wherein a "0" in the first voltage domain is a first voltage and a "1" in the first voltage domain is a second voltage and a "0" in the second voltage domain is the first voltage and a "1" in the second voltage is a third voltage different from the second voltage, the level shifter comprising:

a first power supply that provides the third voltage;

a first PMOS transistor comprising a first terminal coupled to the first power supply, a gate, and a second terminal;

a second PMOS transistor comprising a first terminal coupled to the first power supply, a gate coupled to the second terminal of the first PMOS circuit, and a second terminal coupled to the gate of the first PMOS transistor and an output node for providing the output;

a first NMOS transistor comprising a first terminal coupled to the second terminal of the first PMOS circuit, a gate configured to receive a first signal; and a second terminal configured to receive a complement of the input;

a second NMOS transistor comprising a first terminal coupled to the second terminal of the first PMOS circuit, a gate configured to receive the input, and a second terminal coupled to the first voltage;

a third NMOS circuit comprising a first terminal coupled to the output node, a gate configured to receive the complement of the input, and a second terminal coupled to the first voltage; and

a fourth NMOS circuit comprising a first terminal coupled to the output node, a gate coupled to receive a second signal, and a second terminal configured to receive the input;

wherein the first signal is floating or twice the second voltage when the input is at the second voltage and the first signal is the second voltage when the input is at the first voltage; and is

Wherein the second signal is floating or twice the second voltage when the input is at the first voltage and the second signal is the second voltage when the input is at the second voltage.

2. The level shifter of claim 1, further comprising a second power supply providing the second voltage.

3. The level shifter of claim 2, wherein the first signal is generated by a first circuit comprising:

a third PMOS transistor comprising a first terminal coupled to the second power supply, a gate, and a second terminal;

a fourth PMOS transistor comprising a first terminal coupled to the second terminal of the third PMOS transistor, a gate, and a second terminal;

a fifth PMOS transistor comprising a first terminal coupled to the second terminal of the fourth PMOS transistor, a gate configured to receive the complement of the input, and a second terminal coupled to the gate of the fourth PMOS transistor;

a fifth NMOS transistor comprising a first terminal coupled to the second terminal of the fifth PMOS transistor, a gate configured to receive the complement of the input, and a second terminal coupled to the first voltage; and

a first capacitor including a first terminal coupled to the gate of the third PMOS transistor and a second terminal coupled to the second terminal of the fourth PMOS transistor.

4. The level shifter of claim 3, wherein the second signal is generated by a second circuit comprising:

a sixth PMOS transistor comprising a first terminal coupled to the second power supply, a gate, and a second terminal;

a seventh PMOS transistor comprising a first terminal coupled to the second terminal of the sixth PMOS transistor, a gate, and a second terminal;

an eighth PMOS transistor that includes a first terminal coupled to the second terminal of the seventh PMOS transistor, a gate configured to receive the input, and a second terminal coupled to the gate of the seventh PMOS transistor;

a sixth NMOS transistor comprising a first terminal coupled to the second terminal of the eighth PMOS transistor, a gate configured to receive the input, and a second terminal coupled to the first voltage; and

a capacitor including a first terminal coupled to the gate of the sixth PMOS transistor and a second terminal coupled to the second terminal of the seventh PMOS transistor.

5. The level shifter of claim 2, wherein the first voltage is ground.

6. The level shifter according to claim 5, wherein the second voltage is 1V.

7. The level shifter according to claim 6, wherein the third voltage is 2.5V.

8. The level shifter of claim 3, wherein the first voltage is ground.

9. The level shifter according to claim 8, wherein the second voltage is 1V.

10. The level shifter of claim 9, wherein the third voltage is 2.5V.

11. The level shifter of claim 4, wherein the first voltage is ground.

12. The level shifter according to claim 11, wherein the second voltage is 1V.

13. The level shifter of claim 12, wherein the third voltage is 2.5V.

14. The level shifter of claim 1, wherein the first voltage is ground.

15. The level shifter of claim 14, wherein the second voltage is 1V.

16. The level shifter of claim 15, wherein the third voltage is 2.5V.

17. A method of shifting from a first voltage domain to a second voltage domain, the method comprising:

receiving an input of a first voltage domain, wherein a "0" in the first voltage domain is a first voltage and a "1" in the first voltage domain is a second voltage;

generating a switching voltage equal to twice the second voltage;

generating an output of a second voltage domain using the switching voltage, wherein a "0" in the second voltage domain is the first voltage and is generated when the input is a "0", and a "1" in the second voltage domain is a third voltage and is generated when the input is a "1".

18. The method of claim 17, wherein the first voltage is ground.

19. The method of claim 18, wherein the second voltage is 1V.

20. The method of claim 19, wherein the third voltage is 2.5V.