KR100670500B1 - Method for fabricating semiconductor device - Google Patents
Method for fabricating semiconductor device Download PDFInfo
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- KR100670500B1 KR100670500B1 KR1020000084535A KR20000084535A KR100670500B1 KR 100670500 B1 KR100670500 B1 KR 100670500B1 KR 1020000084535 A KR1020000084535 A KR 1020000084535A KR 20000084535 A KR20000084535 A KR 20000084535A KR 100670500 B1 KR100670500 B1 KR 100670500B1
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- 238000000034 method Methods 0.000 title claims abstract description 29
- 239000004065 semiconductor Substances 0.000 title claims abstract description 29
- 239000002184 metal Substances 0.000 claims abstract description 58
- 239000011229 interlayer Substances 0.000 claims abstract description 20
- 238000004519 manufacturing process Methods 0.000 claims abstract description 19
- 229920002120 photoresistant polymer Polymers 0.000 claims abstract description 17
- 238000005530 etching Methods 0.000 claims abstract description 12
- 238000005468 ion implantation Methods 0.000 claims abstract description 10
- 230000001681 protective effect Effects 0.000 claims abstract description 9
- 239000000758 substrate Substances 0.000 claims abstract description 8
- 239000010410 layer Substances 0.000 claims abstract description 6
- 150000002500 ions Chemical class 0.000 claims abstract description 5
- 238000000059 patterning Methods 0.000 claims abstract description 4
- 239000005380 borophosphosilicate glass Substances 0.000 claims description 5
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 claims description 4
- BOTDANWDWHJENH-UHFFFAOYSA-N Tetraethyl orthosilicate Chemical compound CCO[Si](OCC)(OCC)OCC BOTDANWDWHJENH-UHFFFAOYSA-N 0.000 claims description 3
- 239000011248 coating agent Substances 0.000 claims description 3
- 238000000576 coating method Methods 0.000 claims description 3
- 229910018125 Al-Si Inorganic materials 0.000 claims description 2
- 229910018520 Al—Si Inorganic materials 0.000 claims description 2
- 230000004888 barrier function Effects 0.000 description 9
- 238000001465 metallisation Methods 0.000 description 7
- 230000004913 activation Effects 0.000 description 3
- 238000000151 deposition Methods 0.000 description 3
- 125000006850 spacer group Chemical group 0.000 description 3
- 238000006243 chemical reaction Methods 0.000 description 2
- 238000002955 isolation Methods 0.000 description 2
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 150000001875 compounds Chemical class 0.000 description 1
- 230000008021 deposition Effects 0.000 description 1
- 230000006866 deterioration Effects 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 238000001312 dry etching Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 230000005012 migration Effects 0.000 description 1
- 238000013508 migration Methods 0.000 description 1
- 239000002245 particle Substances 0.000 description 1
- 238000002161 passivation Methods 0.000 description 1
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 1
- 229920005591 polysilicon Polymers 0.000 description 1
- 239000011241 protective layer Substances 0.000 description 1
- 230000006641 stabilisation Effects 0.000 description 1
- 238000011105 stabilization Methods 0.000 description 1
- 230000000087 stabilizing effect Effects 0.000 description 1
- 238000001039 wet etching Methods 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/027—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34
- H01L21/0271—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising organic layers
- H01L21/0273—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising organic layers characterised by the treatment of photoresist layers
- H01L21/0274—Photolithographic processes
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/26—Bombardment with radiation
- H01L21/263—Bombardment with radiation with high-energy radiation
- H01L21/265—Bombardment with radiation with high-energy radiation producing ion implantation
- H01L21/26586—Bombardment with radiation with high-energy radiation producing ion implantation characterised by the angle between the ion beam and the crystal planes or the main crystal surface
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
- H01L21/321—After treatment
- H01L21/3213—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer
- H01L21/32139—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer using masks
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Abstract
본 발명은 금속배선간 공간 마진을 보상하도록 한 반도체 소자의 제조 방법에 관한 것으로, 이를 위한 본 발명은 반도체 기판상에 층간절연막을 형성하는 단계, 상기 층간절연막을 선택적으로 식각하여 콘택홀을 형성하는 단계, 상기 콘택홀을 포함한 전면에 금속막을 형성하는 단계, 상기 금속막상에 감광막을 도포하고 노광 및 현상으로 패터닝하는 단계, 상기 패터닝된 감광막을 마스크로 이용하여 상기 금속막을 식각하여 다수의 금속배선을 형성하는단계, 상기 금속배선 사이의 층간절연막에 As이온을 이온주입하는 단계, 상기 패터닝된 감광막을 제거하는 단계, 및 상기 금속배선을 포함한 전면에 소자보호막을 형성하는 단계를 포함하여 이루어진다.The present invention relates to a method of manufacturing a semiconductor device to compensate for space margin between metal wirings. The present invention provides a method for forming a contact hole by selectively etching an interlayer insulating layer on a semiconductor substrate. Forming a metal film on the entire surface including the contact hole, applying a photoresist film on the metal film, and patterning the photoresist film by exposure and development, and etching the metal film using the patterned photoresist film as a mask to form a plurality of metal wires. Forming, ion implantation of As ions into the interlayer insulating film between the metal wiring, removing the patterned photosensitive film, and forming a device protective film on the entire surface including the metal wiring.
소자보호막, 금속배선, 로직소자, 마스크롬, 패드Device protection film, metal wiring, logic device, mask rom, pad
Description
도 1은 종래기술에 따른 반도체 소자의 제조 방법을 간략히 도시한 도면,1 is a view briefly showing a method of manufacturing a semiconductor device according to the prior art,
도 2는 종래기술에 따른 금속배선간 공간에서 발생되는 감광막의 어택을 도시한 도면,2 is a view showing an attack of a photosensitive film generated in a space between metal wires according to the prior art;
도 3은 종래기술에 따른 패드식각후 금속배선간 공간이 드러나는 현상을 도시한 도면,3 is a view illustrating a phenomenon in which a space between metal wires is exposed after etching a pad according to the prior art;
도 4a 내지 도 4d는 본 발명의 실시예에 따른 반도체 소자의 제조 방법을 도시한 도면.
4A to 4D illustrate a method of manufacturing a semiconductor device in accordance with an embodiment of the present invention.
*도면의 주요 부분에 대한 부호의 설명* Explanation of symbols for the main parts of the drawings
31 : 반도체 기판 32 : 필드산화막31
33 : 게이트산화막 34 : 게이트전극33: gate oxide film 34: gate electrode
35 : 측벽 스페이서 36 : LDD 구조의 소스/드레인35
37 : 층간절연막 38 : 배리어막37 interlayer insulating film 38 barrier film
39 : 금속배선막 40 : 감광막39
41 : 소자보호막 41: element protection film
본 발명은 반도체 소자의 제조 방법에 관한 것으로서, 특히 반도체 소자의 보호막 형성 방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a semiconductor device, and more particularly, to a method for forming a protective film for a semiconductor device.
통상적으로 반도체 소자의 제조에 있어서, 소자를 보호 및 외부로부터의 파티클 유입을 방지하기 위해 보호막(Passivation)을 형성한다. 이러한 보호막은 칩을 보호할 뿐만 아니라 외부의 환경에 대해서도 영향을 받지 않고, 그 고유의 특성을 발휘하므로써 반도체 소자의 공정에서 아주 중요한 공정 중 하나이다.Typically, in the manufacture of semiconductor devices, passivation is formed to protect the device and to prevent particle flow from the outside. Such a protective film is one of the very important processes in the process of semiconductor devices because it not only protects the chip but also is not affected by the external environment and exhibits its own characteristics.
도 1은 종래기술에 따른 반도체 소자의 소자 보호막 형성 방법을 도시한 도면이다.1 is a view showing a method of forming a device protective film of a semiconductor device according to the prior art.
도 1에 도시된 바와 같이, 반도체 기판(11)에 소자간 격리를 위한 필드산화막(12)을 형성한 후, 반도체 기판(11)상에 게이트 산화막(13), 게이트전극(14)을 순차적으로 형성한다. 게이트전극(14)의 양측벽에 접하는 측벽스페이서(15)를 형성하고, 게이트전극(14) 하부에는 LDD 구조의 소스/드레인(16)을 형성한다.As shown in FIG. 1, after forming the
상술한 바와 같은 트랜지스터(Transistor) 제조 공정이 완료된 후, 전면에 금속배선간 층간절연막(Inter Metal Dielectric; IMD)(17)으로서 TEOS/BPSG을 적층 형성한 후, BPSG를 플로우시켜 층간절연막(17)을 평탄화한다.After the transistor manufacturing process as described above is completed, a TEOS / BPSG is laminated as an inter metal dielectric (IMD) 17 on the entire surface, and then BPSG is flowed to flow the interlayer
층간절연막(17)상에 감광막을 도포하고 노광 및 현상으로 패터닝한 후, 패터닝된 감광막을 마스크로 이용하여 층간절연막(17)을 식각하므로써 금속배선용 콘택 홀을 형성한다.After the photosensitive film is coated on the
다음으로, 금속배선용 콘택홀을 포함한 층간절연막(17)상에 배리어막(18)으로서 Ti/TiN의 적층막을 증착한 후, 배리어막(18)상에 금속배선막(19)을 형성한다. 금속배선막(19)과 배리어막(18)을 선택적으로 패터닝하여 금속배선을 형성한다. 이 때, 금속배선을 형성하는 방법은 통상적인 감광막을 도포하고 노광 및 현상으로 패터닝한 후, 패터닝된 감광막을 마스크로 이용하여 금속배선막(19)과 배리어막(18)을 식각한다.Next, after depositing a stacked film of Ti / TiN as the barrier film 18 on the
금속배선 형성시 적용된 감광막을 제거한 후, 전면에 소자보호막(20)으로서 USG(Undoped Silica Glass)/PE-질화막의 적층막을 형성한다.After removing the photoresist film applied when the metal wiring is formed, a laminated film of USG (Undoped Silica Glass) / PE-nitride film is formed on the entire surface as the
후속 공정으로 소자보호막의 안정화를 위한 화합물 공정을 실시하고, 본딩패드를 형성하기 위한 패드 식각 공정을 실시한다.In a subsequent process, a compound process for stabilizing the device protective film is performed, and a pad etching process for forming a bonding pad is performed.
상술한 바와 같은 종래기술은 하나의 폴리실리콘과 하나의 금속배선으로 이루어지는 로직 소자(Logic device)의 제조 방법을 도시한 것으로, 통상적으로 로직 소자는 메모리 소자와 달리 각기 특성을 나타내는 단위소자를 연결하는 금속배선이 필요하므로 다수의 넓은 폭을 갖는 금속배선이 형성된다.The prior art as described above shows a method of manufacturing a logic device consisting of one polysilicon and one metal wiring. In general, a logic device, unlike a memory device, connects unit devices having respective characteristics. Since metal wiring is required, a plurality of wide metal wirings are formed.
그러나, 이러한 다수의 금속배선의 넓게 형성되므로 인해 금속배선간 공간의 마진(Space margin)이 상대적으로 부족하고, 소자보호막 증착시 금속배선간 공간의 단차피복성(Step coverage)이 취약하여(도 1의 21), 금속배선 식각을 위한 마스크 공정시 감광막이 금속배선간 공간에 잔류하게 되어 소자보호막의 안정화 공정시 주위 금속배선을 어택(Attack)하는 문제점이 있다(도 2 참조). However, due to the wide formation of such a plurality of metal wirings, the space margin between the metal wirings is relatively insufficient, and the step coverage of the spaces between the metal wirings is weak when the device protective layer is deposited (FIG. 1). 21), the photoresist film remains in the space between the metal wirings during the mask process for etching the metal wirings, thereby causing a problem of attacking the surrounding metal wirings during the stabilization process of the device protection film (see FIG. 2).
또한, 패드 식각시 패드부분만 패턴이 형성되어야 하는데 금속배선간 공간 마진이 취약한 부분에서도 같이 식각됨에 따라 소자의 보호 기능을 제대로 수행하지 못하고, 패드 식각후 패드 패턴 및 금속배선간 공간이 취약한 부분까지 드러나는 문제점이 있다(도 3 참조).
In addition, only the pad part should be patterned when the pad is etched. However, even when the space margin between the metal wirings is weak, the protection function of the device cannot be properly performed. There is a problem that is revealed (see Figure 3).
본 발명은 상기 종래기술의 문제점을 해결하기 위해 안출한 것으로서, 금속배선간 공간 마진의 취약함에 따른 보호막 특성 열화를 개선시키도록 한 반도체 소자의 소자보호막 형성 방법을 제공하는데 그 목적이 있다.
The present invention has been made to solve the problems of the prior art, and an object of the present invention is to provide a method for forming a device protective film of a semiconductor device to improve the protective film characteristics deterioration due to the weakness of the space margin between metal wiring.
상기의 목적을 달성하기 위한 본 발명의 반도체 소자의 제조 방법은 반도체 기판상에 층간절연막을 형성하는 단계, 상기 층간절연막을 선택적으로 식각하여 콘택홀을 형성하는 단계, 상기 콘택홀을 포함한 전면에 금속막을 형성하는 단계, 상기 금속막상에 감광막을 도포하고 노광 및 현상으로 패터닝하는 단계, 상기 패터닝된 감광막을 마스크로 이용하여 상기 금속막을 식각하여 다수의 금속배선을 형성하는단계, 상기 금속배선 사이의 층간절연막에 As이온을 이온주입하는 단계, 상기 패터닝된 감광막을 제거하는 단계, 및 상기 금속배선을 포함한 전면에 소자보호막을 형성하는 단계를 포함하여 이루어짐을 특징으로 한다.A method of manufacturing a semiconductor device of the present invention for achieving the above object comprises the steps of forming an interlayer insulating film on a semiconductor substrate, selectively etching the interlayer insulating film to form a contact hole, a metal on the front surface including the contact hole Forming a film, coating a photoresist film on the metal film and patterning the photoresist film by exposure and development, etching the metal film using the patterned photoresist film as a mask to form a plurality of metal wirings, and an interlayer between the metal wirings. And implanting As ions into the insulating film, removing the patterned photosensitive film, and forming a device protection film on the entire surface including the metal wiring.
이하, 본 발명이 속하는 기술분야에서 통상의 지식을 가진 자가 본 발명의 기술적 사상을 용이하게 실시할 수 있을 정도로 상세히 설명하기 위하여, 본 발명의 가장 바람직한 실시예를 첨부 도면을 참조하여 설명하기로 한다.Hereinafter, the preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings so that those skilled in the art may easily implement the technical idea of the present invention. .
도 4a 내지 도 4d는 본 발명의 실시예에 따른 반도체 소자의 제조 방법을 도시한 도면이다.4A to 4D are diagrams illustrating a method of manufacturing a semiconductor device in accordance with an embodiment of the present invention.
도 4a에 도시된 바와 같이, 반도체 기판(31)상에 소자간 격리를 위한 필드산화막(32)을 형성한 후, 반도체 기판(31)상에 게이트 산화막(33), 게이트전극(34)을 순차적으로 형성한다. 게이트전극(34)의 양측벽에 접하는 측벽스페이서(35)를 형성하고, 게이트전극(34) 하부에는 LDD 구조의 소스/드레인(36)을 형성한다.As shown in FIG. 4A, after forming the
상술한 바와 같은 트랜지스터 제조 공정이 완료된 후, 전면에 금속배선간 층간절연막(IMD)(37)으로서 TEOS/BPSG(1000Å/5000Å)을 적층 형성한 후, BPSG를 플로우시켜 층간절연막(37)을 평탄화한다.After the transistor fabrication process as described above is completed, TEOS / BPSG (1000 mW / 5000 mW) is laminated on the entire surface as the inter-metal interlayer insulating film (IMD) 37, and then BPSG is flowed to planarize the
다음으로, 평탄화된 층간절연막(37)상에 감광막(도시 생략)을 도포하고 노광 및 현상으로 패터닝한 후, 패터닝된 감광막을 마스크로 이용하여 층간절연막 (37)을 습식 식각 및 건식 식각하므로써 금속배선용 콘택홀을 형성하고, 패터닝된 감광막을 스트립한다.Next, a photosensitive film (not shown) is coated on the planarized
다음으로, 금속배선용 콘택홀을 포함한 층간절연막(37)상에 배리어막(38)으로서 Ti/TiN(300Å/1200Å)의 적층막을 증착한 후, 후속 금속배선막(39)과의 반응을 증가시키기 위해 배리어막(38)을 열처리한다.Next, after depositing a laminated film of Ti / TiN (300 mW / 1200 mW) as the barrier film 38 on the
다음으로, 배리어막(38)상에 금속배선(39)으로서 Al-Si(8000Å)을 형성한다음, 금속배선(39)의 난반사를 방지하기 위해 반사방지막으로서 TiN을 적층할 수 있 다.Next, Al-Si (8000 kPa) is formed as the
도 4b에 도시된 바와 같이, 금속배선(39)상에 감광막(40)을 도포하고 노광 및 현상으로 패터닝한 후, 패터닝된 감광막(40)을 마스크로 이용하여 금속배선 (39)과 배리어막(38)을 선택적으로 패터닝하여 금속배선을 형성한다. 이 때, 통상의 기술과 동일하게 로직소자에서는 넓은 금속배선이 다수 형성되어 금속배선간 공간마진이 부족한 부분(40b)과 공간마진이 충분한 부분(40a)이 존재하게 된다.As shown in FIG. 4B, after the
도 4c에 도시된 바와 같이, 금속배선간 공간의 활성화 에너지를 증가시키기 위하여 이온주입 공정을 실시하는데, 이 때 층간절연막(37)의 어택을 고려하여 표면에 얕은 도핑을 실시한다. 이러한 이온주입 공정은 원자량이 큰 소스, 예컨대 As를 3×1014의 도즈량과 30keV의 이온주입 에너지로 실시하며, 금속배선(39)에 영향을 주지 않기 위해 이온주입각도는 0°∼45°이다.As shown in FIG. 4C, an ion implantation process is performed to increase the activation energy of the space between the metal interconnections. At this time, a shallow doping is performed on the surface in consideration of the attack of the
이와 같은 이온주입 공정을 실시하면 금속배선(39)간 공간에 이온주입이 이루어져 후속 소자 보호막 증착시 갭필 능력을 향상시키는 요인으로 작용한다.When the ion implantation process is performed, ion implantation is performed in the space between the
도 4d에 도시된 바와 같이, 금속배선(39) 형성시 적용된 감광막(40)을 제거한 후, 전면에 소자보호막(41)으로서 USG/PE-질화막(3000Å/5000Å)의 적층막을 형성한다. 이 때, 금속배선(39)간 공간부분에도 소자보호막(41)이 형성되는데, 전술한 이온주입 공정에 의해 금속배선(39)간 공간부분의 활성화에너지가 증가함에 따라 소자보호막(41) 형성시 서로 반응을 활성화시켜 갭필 능력을 증가시킨다.As shown in FIG. 4D, after removing the
도면에 도시되지 않았지만, 후속 공정으로 소자보호막(41)상에 패드 식각을 위한 감광막을 도포하는데, 이 때 패드 식각의 하드 베이크(Hard bake) 공정에서 금속배선간 공간 중 취약한 부분에 감광막이 얇게 형성되는 현상을 방지하기 위해 감광막을 3.4㎛∼4.0㎛의 두께로 형성한다.Although not shown in the drawings, a photoresist film for pad etching is applied to the
본 발명의 기술 사상은 상기 바람직한 실시예에 따라 구체적으로 기술되었으나, 상기한 실시예는 그 설명을 위한 것이며 그 제한을 위한 것이 아님을 주의하여야 한다. 또한, 본 발명의 기술 분야의 통상의 전문가라면 본 발명의 기술 사상의 범위 내에서 다양한 실시예가 가능함을 이해할 수 있을 것이다.
Although the technical idea of the present invention has been described in detail according to the above preferred embodiment, it should be noted that the above-described embodiment is for the purpose of description and not of limitation. In addition, those skilled in the art will understand that various embodiments are possible within the scope of the technical idea of the present invention.
상술한 바와 같은 본 발명의 반도체 소자의 제조 방법은 다수의 금속배선간 공간 마진이 부족한 부분에 이온주입을 실시하여 활성화 에너지를 증가시키므로써 소자보호막을 용이하게 형성할 수 있는 효과가 있다.The method of manufacturing a semiconductor device of the present invention as described above has an effect that can easily form a device protective film by increasing the activation energy by performing ion implantation in a portion where the space margin between a plurality of metal wiring is insufficient.
또한, 금속배선간 공간 마진을 상대적으로 확보하므로써 금속배선의 EM(Electromigration) 또는 SM(Stress Migration) 특성을 증대시킬 수 있고, 아울러 금속배선의 디자인 마진(Design margin)을 확보할 수 있는 효과가 있다.In addition, it is possible to increase the EM (Electromigration) or SM (Stress Migration) characteristics of the metal wiring by securing the space margin between the metal wiring, and also to secure the design margin of the metal wiring. .
Claims (7)
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR930011134A (en) * | 1991-11-20 | 1993-06-23 | 김광호 | Method of forming interlayer insulating layer of semiconductor device |
| KR930011134B1 (en) * | 1990-12-31 | 1993-11-24 | 주식회사 금성사 | Recording and playback monitoring circuit of television camera |
| KR970052787A (en) * | 1995-12-11 | 1997-07-29 | 김주용 | Method of forming insulating film between metal wires |
| KR20000044570A (en) * | 1998-12-30 | 2000-07-15 | 김영환 | Method for flattening interlayer dielectric of semiconductor device |
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| KR930011134B1 (en) * | 1990-12-31 | 1993-11-24 | 주식회사 금성사 | Recording and playback monitoring circuit of television camera |
| KR930011134A (en) * | 1991-11-20 | 1993-06-23 | 김광호 | Method of forming interlayer insulating layer of semiconductor device |
| KR940003559B1 (en) * | 1991-11-20 | 1994-04-23 | 삼성전자 주식회사 | Forming method for inter-layer insulating film of semiconductor device |
| KR970052787A (en) * | 1995-12-11 | 1997-07-29 | 김주용 | Method of forming insulating film between metal wires |
| KR20000044570A (en) * | 1998-12-30 | 2000-07-15 | 김영환 | Method for flattening interlayer dielectric of semiconductor device |
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