KR100669728B1 - Pixel electrode-spilt flat panel device - Google Patents

Abstract

The present invention divides each pixel region into two sub-pixel regions, and arranges pixel electrode patterns in the divided sub-pixel regions, respectively, to different pixel regions among the divided electrode patterns arranged in adjacent pixel regions with gate lines therebetween. An organic light emitting display device capable of improving visibility and improving yield by configuring an array of pixel electrode patterns as one pixel is disclosed.

An organic light emitting display device of the present invention comprises: a substrate; A plurality of gate lines, data lines and power lines arranged on the substrate; A plurality of pixel regions defined by the plurality of gate lines, data lines, and power lines; A plurality of pixel electrodes each having a plurality of sub-pixel electrode patterns arranged in each pixel area, each of which is disposed in two neighboring pixel areas with one line among the gate line, the data line, and the power line interposed therebetween; Some of the sub pixel electrode patterns of the arranged plurality of sub pixel electrode patterns are configured as pixel electrodes of one pixel.

Description

Organic electroluminescent display device having divided pixel electrode {Pixel electrode-spilt flat panel device}

1A is a planar structure diagram of a conventional organic light emitting display device;

1B is a planar structure diagram of one pixel in a conventional organic light emitting display device;

1C is a cross-sectional structure diagram of one pixel in a conventional organic light emitting display device;

2A is a planar structure diagram of an organic light emitting display device according to an embodiment of the present invention;

2B is a plan view of one pixel in an organic light emitting display device according to an embodiment of the present invention;

2C is a cross-sectional structure diagram of one pixel in an organic light emitting display device according to an exemplary embodiment of the present invention;

Explanation of symbols on the main parts of the drawings

200: organic light emitting display device 211, 212, 213: gate line

220: data line 230: power line

260, 280: thin film transistor 270: capacitor

241, 242, 243, 241a, 241b, 242a, 242b, 243a: pixel area

251, 252, and 253 pixels 263 and 325 gate electrodes

265, 267, 341, 345: source / drain electrodes

264, 266, 268, 331, 335: contact holes 261, 310: semiconductor layer

320: gate insulating film 330: interlayer insulating film

350: protective film 370: pixel separation film

361a, 361b, 362a, 362b, 363a: sub pixel electrode pattern

371a, 371b, 372a, 372b, 373a: opening

355 via holes 381b, 382a, and 382b: organic layer

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a flat panel display, and more particularly, to organic light emitting diodes that can improve visibility and improve yield by dividing pixel electrodes and interposing adjacent electrode patterns with one pixel. It relates to a display device.

1A illustrates a planar structure of a conventional organic light emitting display device.

Referring to FIG. 1A, a conventional organic light emitting display device 15 includes a plurality of gate lines 10, a plurality of data lines 20, and a plurality of power lines 30. And a plurality of pixel regions 40 defined in the plurality of lines 10, 20, and 30, and the gate line 10, the data line 20, and the power line 30 in the pixel region 40. A plurality of pixels 50 connected to each other are arranged.

Each pixel 50 includes two thin film transistors of the switching thin film transistor 60 and the driving thin film transistor 80, one capacitor 70, and an anode electrode 160 as a pixel electrode, as shown in FIG. 1B. An organic light emitting element EL is provided. In the drawing, reference numeral 155 denotes a via hole for connecting the driving thin film transistor 80 and the pixel electrode 160.

FIG. 1B illustrates a plan view of one pixel arranged in one pixel area 40 in a conventional organic light emitting display device.

Referring to FIG. 1B, the switching thin film transistor 60 includes a semiconductor layer 61 having a source / drain region (not shown), a gate electrode 63 connected to the gate line 10, and the data. A source electrode 65 connected to the line 20 and a drain electrode 67 connected to the capacitor 70 are provided. The source / drain electrodes 65 and 67 are connected to the semiconductor layer 61 through contact holes 64 and 66.

The capacitor 70 overlaps the lower electrode 71 connected to the drain electrode 67 of the switching thin film transistor 60 through the contact hole 68 and the lower electrode 61 so as to overlap the power line 30. It is provided with an upper electrode 75 connected to.

The driving thin film transistor 80 includes a semiconductor layer 110 having a source / drain region (111 and 115 in FIG. 1C), a gate electrode 125 connected to the lower electrode 71 of the capacitor 70, A source electrode 141 connected to the power line 30 and a drain electrode 145 connected to the anode electrode 160 through the via hole 155 are provided. The source / drain electrodes 141 and 145 are connected to the source / drain regions 111 and 115 of the semiconductor layer 110 through contact holes 131 and 135.

FIG. 1C illustrates a cross-sectional view of one pixel in a conventional organic light emitting display device, and FIG. 1C illustrates a cross-sectional structure along the IC-IC line of FIG. 1B.

Referring to FIG. 1C, the driving thin film transistor 80 is formed on the buffer layer 105 of the substrate 100. The driving thin film transistor 80 includes a semiconductor layer 110 including source / drain regions 111, 115, and a channel region 113, a gate electrode 125 and an interlayer insulating layer formed on the gate insulating layer 120. Source / drain electrodes 141 and 145 are formed on the 130 and are connected to the source / drain regions 111 and 115 through contact holes 131 and 135.

An anode electrode 160 connected to the drain electrode 145 of the source / drain electrodes 141 and 145 through the via hole 155 is formed on the passivation layer 150. The pixel isolation layer 170 includes an opening 175 that exposes a portion of the anode electrode 160. The organic light emitting layer 180 is formed on the anode electrode 160 in the opening 175, and the cathode electrode 190 is formed on the entire surface of the substrate.

The defects generated in the organic light emitting display device are mostly dark pixels, and one of the main causes of the dark spot defects is a short circuit between the anode electrode and the cathode electrode due to the projection of the transparent conductive film which is the foreign material or the anode electrode. Another cause of dark spot defects is a pattern defect of the organic light emitting layer due to foreign substances in the mask when the organic light emitting layer is deposited using a fine metal mask.

Dark spot defects caused by foreign substances in the mask are detected as non-emission pixels or low luminance light emitting pixels on the screen of the organic light emitting display device. Conventionally, in the case of depositing an organic light emitting layer using a dot-type micrometal mask, an organic light emitting layer of one pixel is deposited by corresponding one dot to one pixel.

When a dot type micrometal mask is used, when an organic foreign material such as abnormal deposition is attached to one dot, the organic light emitting material is blocked by the foreign matter attached to the mask, so that the organic light emitting layer is applied to the pixel corresponding to the dot with the foreign material attached thereto. This may not be deposited properly, resulting in a pattern defect of the organic light emitting layer. In addition, the foreign matter attached to the mask is attached to the substrate for manufacturing the organic light emitting display device during the deposition process of the organic light emitting layer, the problem that the organic foreign matter attached to the substrate acts as a particle causing a short There was this.

The present invention is to solve the problems of the prior art as described above, by dividing one pixel electrode, the neighboring pixel electrode pattern of the divided pixel electrode pattern with a gate line interposed therebetween to test The purpose is to improve and improve the yield according to the pattern defect.

In order to achieve the above object, the present invention is a substrate; A plurality of gate lines, data lines and power lines arranged on the substrate; A plurality of pixel regions defined by the plurality of gate lines, data lines, and power lines; A plurality of pixel electrodes each having a plurality of sub-pixel electrode patterns arranged in each pixel area, each of which is disposed in two neighboring pixel areas with one line among the gate line, the data line, and the power line interposed therebetween; According to an aspect of the present invention, there is provided a flat panel display device having a divided pixel electrode, in which a plurality of sub pixel electrode patterns are arranged as pixel electrodes of one pixel.

The one line is a plurality of gate lines, and the pixel electrodes of one pixel are a plurality of sub pixels arranged in a pixel region different from a sub pixel electrode pattern adjacent to a gate among the plurality of sub pixel electrode patterns arranged in one pixel region. The electrode pattern includes a sub pixel electrode pattern adjacent to a gate.

The sub pixel electrode pattern arranged in one pixel region constituting the one pixel electrode and the sub pixel electrode pattern arranged in another pixel region are electrically connected to each other by a connection pattern intersecting the gate line.

In addition, the present invention is a substrate; A plurality of gate lines, data lines and power lines arranged on the substrate; At least one defined by the plurality of gate lines, data lines, and power lines, and arranged adjacent to one of two adjacent lines of a corresponding one of the plurality of gate lines, data lines, and power lines A plurality of pixel regions each having a first sub pixel region and at least one second sub pixel region arranged adjacent to another line; A plurality of at least one first sub pixel electrode pattern arranged in the at least one first sub pixel area and at least one second sub pixel electrode pattern arranged in the at least one second sub pixel area A pixel electrode, and two neighboring pixel regions of the plurality of pixel regions are respectively arranged on both sides of one line of the plurality of lines, and one side of the one line of the two neighboring pixel regions is arranged A flat display device comprising a divided pixel electrode in which a second sub pixel electrode pattern of a pixel area and a first sub pixel electrode pattern of a pixel area arranged on the other side of the one line constitute one pixel. It is done.

In addition, the present invention is a substrate; A plurality of gate lines, data lines and power lines arranged on the substrate; At least one first sub pixel region defined by the plurality of gate lines, data lines, and power lines, and arranged adjacent to one gate line of two neighboring gate lines among the plurality of gate lines, and another gate line; A plurality of pixel regions each having at least one second sub pixel region arranged adjacent to the plurality of pixel regions; A plurality of at least one first sub pixel electrode pattern arranged in the at least one first sub pixel area and at least one second sub pixel electrode pattern arranged in the at least one second sub pixel area A pixel electrode; A plurality of driving means for driving the plurality of pixel electrodes, respectively, wherein two neighboring pixel regions of the plurality of pixel regions are arranged on both sides of one gate line of the plurality of lines, respectively; The second sub pixel electrode pattern of the pixel region arranged on one side of the one gate line and the first sub pixel electrode pattern of the pixel region arranged on the other side of the one gate line constitute one pixel. A first sub pixel electrode pattern and a second sub pixel electrode pattern constituting one pixel provide a flat panel display having divided pixel electrodes simultaneously driven by one driving means among the plurality of driving steps. .

A corresponding one of the plurality of driving means includes a second sub pixel electrode pattern of a pixel region arranged on one side of a gate line constituting one pixel and a first sub pixel of a pixel region arranged on the other side of the gate line. It is connected to one of the electrode patterns.

Each pixel includes a lower electrode including the first sub pixel electrode pattern and a second sub pixel electrode pattern; An organic layer formed on the lower electrode; Further comprising an organic light emitting device comprising an upper electrode which is a cathode electrode formed on the substrate.

The driving means includes a switching thin film transistor for switching a data signal provided from the data line according to at least a signal provided to the gate line; A capacitor for storing the data signal; And a driving thin film transistor for driving the organic light emitting diode according to the data signal.

In addition, the flat panel display of the present invention includes a plurality of gate lines, data lines and power lines arranged on a substrate; A plurality of pixel regions defined by the plurality of gate lines, data lines, and power lines, each divided into first and second subpixel regions; First and second subpixel electrode patterns respectively arranged in the first and second subpixel regions, respectively, and having a gate line therebetween, in a second subpixel region of one pixel region of two adjacent pixel regions. A plurality of pixel electrodes in which the first sub pixel electrode pattern arranged in the first sub pixel area of the pixel area different from the arranged second sub pixel electrode pattern is composed of one pixel; And a thin film transistor connected to the first sub pixel electrode pattern, respectively, and a plurality of driving means for driving the plurality of pixel electrodes, respectively.

Each pixel comprises a thin film transistor having a gate and a source / drain electrode formed on a substrate corresponding to the first sub-pixel region; A first subpixel electrode pattern formed on a first insulating layer corresponding to the first subpixel region and connected to one electrode of the source / drain electrodes; A second sub pixel electrode pattern formed on the first insulating layer corresponding to the second sub pixel area; A second insulating film having a first opening exposing a portion of the first sub pixel electrode pattern and a second opening exposing a portion of the second sub pixel electrode pattern; A first organic film layer formed on the first sub pixel electrode pattern in the first opening and a second organic film layer formed on the second subpixel electrode pattern in the second opening; An upper electrode formed on the substrate is provided.

The first organic layer and the second organic layer formed on the first and second sub pixel electrode patterns arranged in one pixel area to form different pixels are separated from each other by a second insulating layer having a sidewall.

The gate lines are arranged on a substrate between a second sub pixel region of one pixel region and a first sub pixel region of another pixel region, and are arranged in different pixel regions including the one pixel. The second sub pixel electrode pattern is electrically connected to each other by a connection pattern crossing the gate line, and the connection pattern includes the same material as the first and second sub pixel electrode patterns.

Hereinafter, an embodiment of the present invention will be described with reference to the accompanying drawings.

2A illustrates a planar structure of an organic light emitting display device according to an exemplary embodiment of the present invention.

Referring to FIG. 2A, the organic light emitting display device 200 according to the present invention includes a plurality of gate lines 211, 212, 213, a plurality of data lines 220, a plurality of power lines 230, and a plurality of the plurality of gate lines 211. A plurality of pixel regions 241, 242, and 243 are defined by gate lines 211, 212, and 213, a plurality of data lines 220, and a plurality of power lines 230. The plurality of pixel areas 241, 242, and 243 are divided into two sub-pixel areas 241a and 241b, 242a and 242b, and 243a and.

 In the plurality of pixel regions 241, 242, and 243, pixel electrodes, which are anode electrodes, are divided into two sub-pixel electrode patterns 361a and 361b, 362a and 362b, and 363a and. The first subpixel electrode pattern 361a is arranged in the first subpixel region 241a of the region 241, and the second subpixel electrode pattern 361b is arranged in the second subpixel region 241b. The first subpixel electrode pattern 362a is arranged in the first subpixel region 242a of the pixel region 242, and the second subpixel electrode pattern 362b is arranged in the second subpixel region 242b. The first sub pixel electrode pattern 363a is arranged in the first sub pixel area 243a of the pixel area 243.

 Gate lines 211, 212, and 213 are arranged between two adjacent pixel areas among the plurality of pixel areas 241, 242, and 243, and gate lines 212 between two adjacent pixel areas 241 and 242. ) Is arranged, and the gate line 213 is arranged between two adjacent pixel regions 242 and 243.

That is, in two adjacent pixel areas with one gate line interposed, one pixel is arranged in the adjacent sub pixel area with the gate line interposed therebetween. Thus, in the embodiment of the present invention, one pixel is not arranged in one pixel region but one pixel is arranged over two neighboring pixel regions.

For example, in the case of the gate line 212, two pixel regions 241 and 242 are arranged with the gate line 212 interposed therebetween, and the subpixels of the two pixel regions 241 and 242 are arranged. One pixel 252 is arranged in two sub-pixel areas 241b and 242a arranged with the gate line 212 in the pixel areas 241a, 241b and 242b. In the case of the gate line 213, two subs arranged in the two pixel areas 242 and 243 with the gate line 213 interposed between the sub pixel areas 242a and 242b and 243a and. One pixel 253 is arranged in the pixel areas 242b and 243a.

A sub pixel electrode pattern arranged in two sub pixel areas adjacent to one gate line serves as a pixel electrode of one pixel. That is, the sub pixel electrode patterns 361b and 362a are arranged in the sub pixel regions 241b and 242a arranged adjacent to the gate line 212, and the two sub pixel electrode patterns 361b and ( 362a is connected by a connection pattern 362c to serve as a pixel electrode of one pixel 252. Sub-pixel electrode patterns 362b and 363a are arranged in sub-pixel regions 242b and 243a arranged adjacent to the gate line 213, respectively, and two pixel electrode patterns 362b and 363a are arranged. ) Is connected by the connection pattern 363c to serve as a pixel electrode of one pixel 253.

Accordingly, two sub pixel electrode patterns 361b and 362a arranged in two adjacent pixel regions 241b and 242a of different pixel regions 241 and 242 with the gate line 212 interposed therebetween. Are connected to each other by the connection pattern 362c, and are connected to the driving means through the via hole 355 to be driven. In addition, two sub pixel electrode patterns 362b and 363a arranged in two adjacent pixel regions 242b and 243a of different pixel regions 242 and 243 with the gate line 213 interposed therebetween. Are connected to each other by the connection pattern 363c and connected to the driving means through the via hole 355 to be driven.

FIG. 2B is a plan view of one pixel arranged in two adjacent pixel areas in the organic light emitting display according to the exemplary embodiment of the present invention, and one gate line 212 of the plurality of gate lines is shown. The planar structure of one pixel 252 arranged in two pixel regions 241 and 242 with a gap therebetween is shown.

Referring to FIG. 2B, two pixel regions 241 and 242 are arranged with the gate line 212 interposed therebetween, and each of the pixel regions 241 and 242 includes two sub pixel regions 241a and 241b. ), Divided into (242a, 242b), and among the two other pixel regions (241, 241b, 242a, 24b) of the other pixel regions (241, 242) arranged with the gate line (212) therebetween. One pixel 252 is arranged in two adjacent sub pixel areas 241b and 242a with the gate line 212 interposed therebetween.

The pixel includes an organic light emitting diode EL including two thin film transistors of the switching thin film transistor 260 and the driving thin film transistor 280, one capacitor 270, and an anode electrode 362 that is a pixel electrode. . In the embodiment of the present invention, the thin film transistor and the capacitor for driving the EL element are arranged in one sub pixel region 242a of the sub pixel regions 241b and 242a, but may be arranged in another sub pixel region 241b. have. Further, in the embodiment of the present invention, each pixel includes two thin film transistors and a capacitor for driving the EL element, but it can be applied to various types of pixel structures.

The pixel electrode 362 includes two sub pixel electrode patterns 361b and 362a. One of the sub pixel electrode patterns 361b of the sub pixel electrode patterns 361b and 362a includes the sub pixel regions 241b and 242a of the sub pixel regions 241b and 242a arranged adjacent to each other with the gate line 212 interposed therebetween. The other sub pixel electrode pattern 362a is arranged in another sub pixel region 242a.

The sub pixel electrode patterns 361b and 362a arranged in each of the sub pixel areas 241b and 242a are connected by a connection pattern 362c crossing the gate line 212. Only a portion of the sub pixel electrode patterns 361b and 362a are exposed through the openings 371b and 372a, respectively.

The switching thin film transistor 260 includes a semiconductor layer 261 having a source / drain region (not shown), a gate electrode 263 connected to a gate line 212, and the data line 210. And a drain electrode 267 connected to the source electrode 265 connected to the capacitor 270. The source / drain electrodes 265 and 267 are connected to the semiconductor layer 261 through contact holes 264 and 266.

The capacitor 270 overlaps the lower electrode 271 connected to the drain electrode 267 of the switching thin film transistor 260 through the contact hole 268 and the lower electrode 271 and the power line 230. And an upper electrode 275 connected to it.

The driving thin film transistor 280 includes a semiconductor layer 310 having a source / drain region (311 and 315 of FIG. 2C) and a channel region (313 of FIG. 2C), and a lower electrode 271 of the capacitor 270. And a drain electrode 345 connected to the gate electrode 325 connected to the power supply line 230, the source electrode 341 connected to the power line 230, and the pixel electrode 362 through the via hole 355. The source / drain electrodes 341 and 345 are connected to the source / drain regions 311 and 315 of the semiconductor layer 310 through contact holes 331 and 335.

FIG. 2C is a cross-sectional view of one pixel in the organic light emitting display according to the exemplary embodiment of the present invention, and the sub pixel areas 241b and 242a are arranged adjacent to each other with the gate line 212 interposed therebetween. 1 is a cross-sectional view of one pixel 252 arranged in FIG. FIG. 2C illustrates a cross-sectional structure along the IIC-IIC line of FIG. 2B, and illustrates a cross-sectional structure of the pixel electrode 362 and the driving thin film transistor 280 connected thereto.

Referring to FIG. 2C, a driving thin film transistor 280, a switching thin film transistor 260, and a capacitor 270 are formed in a portion of the buffer layer 305 of the substrate 300 corresponding to the subpixel region 242a. In the organic light emitting display device 200 according to the present invention, various arrangements and cross-sectional structures of the driving thin film transistor 280, the switching thin film transistor 260, and the capacitor 270 may be applied. Only the cross-sectional structure of the driving thin film transistor 280 connected to is illustrated.

A buffer layer 305 is formed on the substrate 300, and a semiconductor layer 310 is formed in a portion of the buffer layer 305 corresponding to the sub pixel region 242a by a conventional method. A gate insulating layer 320 is deposited on the semiconductor layer 310 and the buffer layer 305. A gate electrode material is deposited on the gate insulating layer 320 and then patterned to form a gate 325 and a gate line 212.

After the gate 325 is formed, source / drain regions 311 and 315 are formed by ion implanting a predetermined conductivity type, for example, p-type impurity, into the semiconductor layer 310. In this case, a portion between the source / drain regions 311 and 315 of the semiconductor layer 310 serves as the channel region 313 of the thin film transistor.

Subsequently, an interlayer insulating film 330 is deposited on the gate 325, the gate line 212, and the gate insulating film 320, and the interlayer insulating film 330 and the gate insulating film 320 are etched to form the source / drain regions ( 311 and 315, contact holes 331 and 335 are formed.

The source / drain electrode material is deposited on the interlayer insulating layer 330 including the contact holes 331 and 335 and then patterned to form the source / drain regions 311 through the contact holes 331 and 335. ) And source / drain electrodes 341 and 345 connected to 315. In this case, although not shown in the drawing, the data line 220 and the power line 230 shown in FIGS. 2A and 2B are formed.

After the deposition of the passivation layer 350 on the substrate, a via hole 355 exposing the drain electrode 345 of the source / drain electrodes 341 and 345 is formed. Subpixel electrode materials 361b and 362a are formed in the subpixel regions 241b and 242a by depositing and patterning a pixel electrode material on the passivation layer 350 including the via hole 355. In this case, the sub pixel electrode pattern 362a arranged in the sub pixel region 242a among the sub pixel electrode patterns 361b and 362a is connected to the drain electrode 345 through a via hole 355. The sub pixel electrode pattern 361b is connected to the sub pixel electrode pattern 362a by a connection pattern 362c.

The pixel isolation layer 370 is deposited on the substrate and then patterned to form openings 371b and 372a exposing portions of the sub-pixel electrode patterns 361b and 362a. Subsequently, the organic film layers 381b and (3b) are exposed to the sub pixel electrode patterns 361b and 362a exposed through the openings 371b and 372a using a dot-shaped fine metal mask (not shown in the drawing). 382a) are deposited respectively. Then, a cathode electrode is deposited on the entire surface of the substrate.

In this case, when the organic layer 382a and 382b are formed on the sub pixel electrode patterns 362a and 362b, the organic layer 338a and 382b are deposited by one dot mask. An organic film layer is also deposited on 370a so that the organic thin layers 382a and 382b are connected to each other. However, the light emitting layers of the organic film layers 382a and 382b commonly formed on the two subpixel electrode patterns have low horizontal conductivity, and thus are independent of each other only for the respective subpixel electrode patterns 362a and 362b. Driven by.

The sub pixel electrode patterns 362a and 362b arranged in each of the sub pixel areas 242a and 242b of one pixel area 242 are separated from each other by the partition pixel pixel 370a. The organic layer 381b and 382a are shown only for the light emitting layer, but include an organic layer selected from a hole injection layer, a hole transport layer, an organic light emitting layer, an electron transport layer, an electron injection layer, and a hole suppression layer.

Instead of the conventional method of depositing an organic light emitting layer by matching pixel electrodes of respective pixels to each dot of a fine metal mask, in the present invention, since the pixel electrodes of each pixel are formed into two sub-pixel electrode patterns, each sub-pixel electrode pattern The organic light emitting layer is deposited by corresponding to each dot of the fine metal mask. Therefore, when a foreign material or the like is attached to any one dot of the fine metal mask to cause a pattern defect in the organic light emitting layer of any pixel, conventionally, one pixel becomes a dark spot or a luminance decrease.

However, in the present invention, one pixel includes two sub pixel electrode patterns, and the organic light emitting layer is deposited by matching the dots of the fine metal mask with respect to each sub pixel electrode pattern. Even if a pattern defect of the light emitting layer occurs, the organic light emitting layer deposited on the other sub-pixel electrode pattern has a normal pattern shape, thereby preventing dark spots or luminance deterioration of the pixel. In addition, in the present invention, by adopting a method of arranging adjacent sub pixel areas into one pixel area with the gate line interposed therebetween, the area where light is emitted is the same, but the light emitting area is present with the gate line interposed therebetween. The area recognized by the eye may be increased to have an effect of improving the sense of vision.

In the exemplary embodiment of the present invention, the pixel region is divided so that the sub pixel regions are adjacent to each other with the gate line interposed therebetween, and the sub pixel electrode pattern arranged in the adjacent sub pixel region with the gate line therebetween is configured as one pixel. In order to prevent a decrease in luminance, the arrangement of the gate lines, the data lines, and the power lines is changed in FIGS. 2A and 2B, that is, the gate lines and the power lines are arranged side by side, and the data lines are aligned with the gate lines and the power lines. By arranging to intersect or arranging gate lines and data lines side by side and arranging power lines side by side with the gate lines and data lines, the pixel region is divided so that the subpixel regions are adjacent with the data lines or power lines interposed therebetween. In the adjacent sub-pixel areas with data lines or power lines The sub-pixel electrode pattern that is open may be formed in a pixel.

In addition, the present invention illustrates that the pixel electrode of each pixel is divided into two sub pixel electrode patterns, but the pixel electrode of each pixel is divided into a plurality of sub pixel electrode patterns, and a part of the plurality of sub pixel electrode patterns is gated. By arranging the lines in adjacent sub-pixel regions with the lines therebetween, a plurality of sub-pixel electrode patterns arranged in the adjacent sub-pixel regions with the gate lines interposed therebetween may be formed of one pixel.

For example, referring to FIG. 2A, a plurality of subpixel regions 241b are arranged side by side along the gate line 212, and a plurality of subpixel electrode patterns are arranged in the plurality of subpixel regions, respectively, along the gate line. Arrange them side by side. In addition, the subpixel regions 242a are arranged side by side along the gate line 212, and a plurality of subpixel electrode patterns are arranged in the plurality of subpixel regions, respectively, and are arranged side by side along the gate line. Accordingly, the plurality of sub pixel electrode patterns are formed as one pixel by arranging the gate lines side by side. In addition, one pixel may be configured by arranging the data lines side by side or in a matrix form without arranging the gate lines side by side.

In addition, the present invention exemplifies an organic light emitting display device in which a pixel electrode is divided to drive the divided pixel electrodes by the same driving means, but a flat panel such as an active matrix liquid crystal display device which drives the pixel electrode using a thin film transistor or the like. It is also applicable to a display device.

 According to the embodiment of the present invention as described above, by dividing each pixel electrode into a plurality of electrode patterns, and arranged in a sub-pixel region adjacent to each other with a gate line therebetween, so as to constitute a single pixel, It is possible to prevent dark spot defects and luminance decrease due to this, and thus there is an advantage of improving luminance and visibility.

Although the above has been described with reference to a preferred embodiment of the present invention, those skilled in the art will be able to variously modify and change the present invention without departing from the spirit and scope of the invention as set forth in the claims below. It will be appreciated.

Claims (15)

A substrate; A plurality of gate lines, data lines and power lines arranged on the substrate; A plurality of pixel regions defined by the plurality of gate lines, data lines, and power lines; A plurality of pixel electrodes each having a plurality of sub pixel electrode patterns arranged in each pixel region; Some sub pixel electrode patterns of a plurality of sub pixel electrode patterns arranged in two adjacent pixel areas with one line among the gate line, the data line and the power line interposed therebetween are configured as pixel electrodes of one pixel. A flat panel display having a divided pixel electrode. The flat panel display of claim 1, wherein the one line is a plurality of gate lines. The pixel electrode of claim 1, wherein the pixel electrode of one pixel is disposed on a gate of a plurality of sub pixel electrode patterns arranged in a pixel area different from a sub pixel electrode pattern adjacent to a gate of a plurality of sub pixel electrode patterns arranged in one pixel area. A flat panel display device having divided pixel electrodes, wherein the pixel electrodes include adjacent sub pixel electrode patterns. The method of claim 3, wherein the sub pixel electrode patterns arranged in one pixel area constituting the one pixel electrode and the sub pixel electrode patterns arranged in another pixel area are electrically connected to each other by a connection pattern crossing the gate line. A flat panel display having a divided pixel electrode, characterized in that connected. A substrate; A plurality of gate lines, data lines and power lines arranged on the substrate; At least one defined by the plurality of gate lines, data lines, and power lines, and arranged adjacent to one of two adjacent lines of a corresponding one of the plurality of gate lines, data lines, and power lines A plurality of pixel regions each having a first sub pixel region and at least one second sub pixel region arranged adjacent to another line; A plurality of at least one first sub pixel electrode pattern arranged in the at least one first sub pixel area and at least one second sub pixel electrode pattern arranged in the at least one second sub pixel area A pixel electrode, Two neighboring pixel regions of the plurality of pixel regions are arranged on both sides of one line of the plurality of lines, respectively, The second sub pixel electrode pattern of the pixel region arranged on one side of the one line among the two neighboring pixel regions and the first sub pixel electrode pattern of the pixel region arranged on the other side of the one line constitute one pixel. A flat panel display having a divided pixel electrode. The flat panel display of claim 5, wherein the one of the plurality of gate lines, the data lines, and the power lines is a plurality of gate lines. The gate line of claim 3, wherein the second sub pixel electrode pattern of the pixel region arranged on one side of the gate line and the first sub pixel electrode pattern of the pixel region arranged on the other side of the gate line constituting one pixel are formed in the gate line. A flat panel display device having a divided pixel electrode, wherein the pixel electrodes are electrically connected to each other by a connection pattern intersecting with each other. A substrate; A plurality of gate lines, data lines and power lines arranged on the substrate; At least one first sub pixel region defined by the plurality of gate lines, data lines, and power lines, and arranged adjacent to one gate line of two neighboring gate lines among the plurality of gate lines, and another gate line; A plurality of pixel regions each having at least one second sub pixel region arranged adjacent to the plurality of pixel regions; A plurality of at least one first sub pixel electrode pattern arranged in the at least one first sub pixel area and at least one second sub pixel electrode pattern arranged in the at least one second sub pixel area A pixel electrode; A plurality of driving means for driving each of the plurality of pixel electrodes, Two neighboring pixel regions of the plurality of pixel regions are respectively arranged on both sides of one gate line of the plurality of lines, One pixel includes a second sub pixel electrode pattern of a pixel region arranged on one side of the gate line among two neighboring pixel regions and a first sub pixel electrode pattern of a pixel region arranged on the other side of the one gate line. Constitute The first sub pixel electrode pattern and the second sub pixel electrode pattern constituting the one pixel are simultaneously driven by a corresponding one of the plurality of driving means. Display. 10. The method of claim 8, wherein the second sub pixel electrode pattern of the pixel region arranged on one side of the gate line constituting one pixel and the first sub pixel electrode pattern of the pixel region arranged on the other side of the gate line intersect with the gate line. A flat panel display device having a divided pixel electrode, which is electrically connected to each other by a connection pattern. 10. The pixel of claim 9, wherein one of the plurality of driving means corresponds to a second sub pixel electrode pattern of a pixel region arranged on one side of a gate line constituting one pixel and a pixel arranged on the other side of the gate line. A flat panel display device having a divided pixel electrode, which is connected to one of the first sub pixel electrode patterns of a region. The method of claim 8, wherein each pixel is A lower electrode including the first sub pixel electrode pattern and the second sub pixel electrode pattern; An organic layer formed on the lower electrode; A flat panel display having divided pixel electrodes, further comprising an organic light emitting device including an upper electrode which is a cathode electrode formed on a substrate. 12. The apparatus of claim 11, wherein the drive means is at least A switching thin film transistor for switching a data signal provided from the data line according to the signal provided to the gate line; A capacitor for storing the data signal; And a driving thin film transistor for driving the organic light emitting diode according to the data signal. A plurality of gate lines, data lines and power lines arranged on the substrate; A plurality of pixel regions defined by the plurality of gate lines, data lines, and power lines, each divided into first and second subpixel regions; First and second subpixel electrode patterns respectively arranged in the first and second subpixel regions, respectively, and having a gate line therebetween, in a second subpixel region of one pixel region of two adjacent pixel regions. A plurality of pixel electrodes in which the first sub pixel electrode pattern arranged in the first sub pixel area of the pixel area different from the arranged second sub pixel electrode pattern is composed of one pixel; A thin film transistor connected to the first sub pixel electrode pattern, and a plurality of driving means for driving the plurality of pixel electrodes, respectively; Each pixel A thin film transistor having a gate and a source / drain electrode formed on a substrate corresponding to the first sub-pixel region; A first subpixel electrode pattern formed on a first insulating layer corresponding to the first subpixel region and connected to one electrode of the source / drain electrodes; A second sub pixel electrode pattern formed on the first insulating layer corresponding to the second sub pixel area; A second insulating film having a first opening exposing a portion of the first sub pixel electrode pattern and a second opening exposing a portion of the second sub pixel electrode pattern; A first organic film layer formed on the first sub pixel electrode pattern in the first opening and a second organic film layer formed on the second subpixel electrode pattern in the second opening; A flat panel display device having a divided pixel electrode, wherein the upper electrode is formed on a substrate. The first organic film layer and the second organic film layer formed on the first and second sub pixel electrode patterns arranged in one pixel area to form different pixels are separated from each other by a second insulating film having sidewalls. A flat panel display having a divided pixel electrode, characterized in that the separation. The method of claim 13, wherein the gate line is arranged on a substrate between the second sub pixel region of one pixel region and the first sub pixel region of another pixel region, The first and second sub pixel electrode patterns arranged in different pixel areas including the one pixel are electrically connected to each other by a connection pattern crossing the gate line. And the connection pattern includes the same material as the first and second sub pixel electrode patterns.

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