KR100668733B1 - Method of forming via contact hole in semiconductor devices - Google Patents
Method of forming via contact hole in semiconductor devices Download PDFInfo
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- KR100668733B1 KR100668733B1 KR1020010045980A KR20010045980A KR100668733B1 KR 100668733 B1 KR100668733 B1 KR 100668733B1 KR 1020010045980 A KR1020010045980 A KR 1020010045980A KR 20010045980 A KR20010045980 A KR 20010045980A KR 100668733 B1 KR100668733 B1 KR 100668733B1
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- 238000000034 method Methods 0.000 title claims abstract description 25
- 239000004065 semiconductor Substances 0.000 title claims abstract description 21
- 239000010410 layer Substances 0.000 claims abstract description 27
- 238000005530 etching Methods 0.000 claims abstract description 23
- 229910052751 metal Inorganic materials 0.000 claims abstract description 17
- 239000002184 metal Substances 0.000 claims abstract description 17
- 239000000758 substrate Substances 0.000 claims abstract description 15
- 229920002120 photoresistant polymer Polymers 0.000 claims abstract description 11
- 239000011229 interlayer Substances 0.000 claims abstract description 7
- 150000004767 nitrides Chemical class 0.000 claims abstract description 5
- 238000000059 patterning Methods 0.000 claims abstract description 3
- 238000000151 deposition Methods 0.000 claims description 3
- 229910052782 aluminium Inorganic materials 0.000 abstract description 16
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical class [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 abstract description 16
- 229920000642 polymer Polymers 0.000 abstract description 15
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 abstract description 10
- 229910052814 silicon oxide Inorganic materials 0.000 abstract description 5
- 238000010030 laminating Methods 0.000 abstract 3
- 238000004140 cleaning Methods 0.000 description 6
- 239000002904 solvent Substances 0.000 description 5
- 238000001312 dry etching Methods 0.000 description 3
- 229910052721 tungsten Inorganic materials 0.000 description 3
- 230000004888 barrier function Effects 0.000 description 2
- 230000015572 biosynthetic process Effects 0.000 description 2
- 239000012528 membrane Substances 0.000 description 2
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 description 2
- 239000010937 tungsten Substances 0.000 description 2
- BOTDANWDWHJENH-UHFFFAOYSA-N Tetraethyl orthosilicate Chemical compound CCO[Si](OCC)(OCC)OCC BOTDANWDWHJENH-UHFFFAOYSA-N 0.000 description 1
- 230000002411 adverse Effects 0.000 description 1
- AZDRQVAHHNSJOQ-UHFFFAOYSA-N alumane Chemical class [AlH3] AZDRQVAHHNSJOQ-UHFFFAOYSA-N 0.000 description 1
- 230000003667 anti-reflective effect Effects 0.000 description 1
- 238000006243 chemical reaction Methods 0.000 description 1
- 230000008021 deposition Effects 0.000 description 1
- 238000005137 deposition process Methods 0.000 description 1
- 238000009792 diffusion process Methods 0.000 description 1
- 239000012535 impurity Substances 0.000 description 1
- 238000010849 ion bombardment Methods 0.000 description 1
- 150000002500 ions Chemical class 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 230000006641 stabilisation Effects 0.000 description 1
- 238000011105 stabilization Methods 0.000 description 1
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- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3105—After-treatment
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- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3105—After-treatment
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- H01L21/31144—Etching the insulating layers by chemical or physical means using masks
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- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76841—Barrier, adhesion or liner layers
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- H10B—ELECTRONIC MEMORY DEVICES
- H10B12/00—Dynamic random access memory [DRAM] devices
- H10B12/30—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells
- H10B12/48—Data lines or contacts therefor
- H10B12/482—Bit lines
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- H01L21/02104—Forming layers
- H01L21/02107—Forming insulating materials on a substrate
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- H01L21/02126—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon the material containing Si, O, and at least one of H, N, C, F, or other non-metal elements, e.g. SiOC, SiOC:H or SiONC
- H01L21/0214—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon the material containing Si, O, and at least one of H, N, C, F, or other non-metal elements, e.g. SiOC, SiOC:H or SiONC the material being a silicon oxynitride, e.g. SiON or SiON:H
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Abstract
본 발명은 알루미늄 금속 계열에 의한 폴리머를 방지하기 위한 반도체 소자의 비아 콘택 홀 형성 방법에 관한 것이다. 여기에 개시된 반도체 소자의 비아 콘택 홀 형성 방법은, ILD(Interlayer Dielectric) 막이 적층된 반도체 기판 상에 질화막과, 금속막과, 도전막 및 식각 저지막을 차례로 적층하는 단계와, 포토 레지스트 패턴을 마스크로 이용하여 기판이 노출되도록 패터닝하여 비트 라인을 형성하는 단계와, 비트 라인이 형성된 반도체 기판 전면에 IMD(Intermetal Dielectric) 막을 컨포멀하게 적층하고, 상기 IMD 막 위에 산화막을 적층하는 단계와, 상기 산화막 위에 포토 레지스트 패턴을 마스크로 이용하여 상기 IMD 막이 노출되도록 상기 산화막을 식각하는 단계 및 상기 산화막 패턴을 마스크로 이용하여 상기 도전막이 노출되도록 상기 IMD 막과 상기 식각 저지막을 식각하여 콘택 홀을 형성하는 단계를 포함한다. 따라서 반도체 소자의 콘택 홀 형성시, 산화막과 SiN 또는 SiON 등의 식각 저지막의 식각 선택비를 이용하여 ARC TiN 막에서 콘택 홀을 형성함으로써, 알루미늄 계열에 의한 금속성 폴리머의 발생을 방지할 수 있다.The present invention relates to a method for forming a via contact hole in a semiconductor device for preventing a polymer by an aluminum metal series. A method of forming a via contact hole in a semiconductor device disclosed herein comprises the steps of laminating a nitride film, a metal film, a conductive film, and an etch stop film on a semiconductor substrate on which an ILD (Interlayer Dielectric) film is laminated, and using a photoresist pattern as a mask. Forming a bit line by patterning the substrate to expose the substrate, conformally laminating an intermetal dielectric (IMD) film on the entire surface of the semiconductor substrate on which the bit line is formed, and laminating an oxide film on the IMD film, on the oxide film Etching the oxide film to expose the IMD film using a photoresist pattern as a mask, and forming a contact hole by etching the IMD film and the etch stop layer to expose the conductive film using the oxide pattern as a mask. Include. Therefore, when forming the contact hole of the semiconductor device, by forming the contact hole in the ARC TiN film using the etching selectivity of the oxide film and the etching stopper film such as SiN or SiON, it is possible to prevent the generation of the metallic polymer by the aluminum-based.
바아 콘택, 비아 콘택 홀, ARC TiN, 폴리머, 식각 선택비Bar Contact, Via Contact Hole, ARC TiN, Polymer, Etch Selectivity
Description
도 1은 본 발명의 실시예에 따른 비아 콘택 홀 형성을 설명하기 위한 반도체 소자의 단면도들이다.1 is a cross-sectional view of a semiconductor device for describing via contact hole formation according to an embodiment of the present invention.
* 도면의 주요 부분에 대한 부호 설명 *Explanation of symbols on the main parts of the drawings
2 : ILD 4 : 질화막2: ILD 4: nitride film
6 : 알루미늄 막 8 : ARC TiN 막6: aluminum film 8: ARC TiN film
10 : 식각 저지막 12 : IMD 막10: etch stop membrane 12: IMD membrane
14 : 산화막 16 : 포토 레지스트 패턴14
18, 18a : 콘택 홀18, 18a: contact hole
본 발명은 반도체 소자의 비아 콘택 홀(via contact hole) 형성 방법에 관한 것으로, 좀 더 구체적으로는 비아 콘택 홀 내부에 발생되는 폴리머를 방지하기 위한 반도체 소자의 비아 콘택 홀 형성 방법에 관한 것이다.The present invention relates to a method of forming a via contact hole of a semiconductor device, and more particularly, to a method of forming a via contact hole of a semiconductor device for preventing a polymer generated in a via contact hole.
일반적으로, 반도체 소자는 각각의 소자들을 형성한 후, 각각의 소자에 전압 을 인가하는 금속 배선이 형성된다. 이러한 금속 배선으로는 다른 재료들에 비해 증착 공정이 간단하고, 저저항의 특성을 갖는 알루미늄(Al) 계열 금속이 주로 사용되는데, 알루미늄 계열 금속 배선 콘택의 경우에는 금속층과 접촉되는 부분에서의 스파이크나 불순물의 확산을 방지하기 위하여 콘택면과 금속 배선의 사이에 Ti/TiN/Al 적층 구조의 금속 배선층을 형성하여 사용한다.In general, after the semiconductor elements are formed, respective metal lines are formed to apply voltages to the respective elements. As the metal wiring, an aluminum (Al) -based metal having a simple deposition process and low resistance is used, compared to other materials. In the case of an aluminum-based metal wiring contact, a spike or a portion in contact with the metal layer may be used. In order to prevent diffusion of impurities, a metal wiring layer having a Ti / TiN / Al laminated structure is formed between the contact surface and the metal wiring.
종래 기술에 따르면, 반도체 장치의 비아 콘택홀을 형성하기 위해 건식 식각 공정으로 콘택 식각시 W 또는 Al으로 이루어진 하부 금속 배선 상부에 반사 방지막으로 TiN 막이 형성되어 있는 경우에 효과적인 제거 방법으로 화학적인 반응 보다는 이온(Ion)에 의한 물리적인 반응으로 식각층을 제거하는데 물리적인 이온 충격에서도 효과적으로 제거가 되지 않기 때문에 필요 이상으로 오버 에칭(Over etching)을 실시하게 된다.According to the prior art, when the TiN film is formed as an anti-reflective film on the upper metal wiring made of W or Al during the dry etching process in order to form the via contact hole of the semiconductor device, it is more effective than chemical reaction. Physical etching by ions removes the etch layer, and since it is not effectively removed even in physical ion bombardment, over etching is performed more than necessary.
일반적으로 비아 콘택 홀 형성을 위한 에칭 공정시, 알루미늄 계열의 금속성의 폴리머가 시 발생하고, 이를 제거하기 위하여 솔벤트를 사용한 세정 공정을 실시한다.In general, during the etching process for forming the via contact hole, an aluminum-based metallic polymer is generated and a cleaning process using a solvent is performed to remove it.
따라서, 과도한 오버 에칭에 의해 다량의 폴리머가 발생하고 이러한 폴리머는 후속 공정의 세정 공정으로도 완벽하게 제거되지 않으며, 콘택 홀의 저면에 미세하게 잔류하여 콘택 저항을 상승시키는 요인으로 작용하게 된다.Therefore, a large amount of polymer is generated by excessive over etching, and such a polymer is not completely removed even by a cleaning process of a subsequent process, and it remains as a factor to increase the contact resistance by finely remaining on the bottom of the contact hole.
또한, 비아 콘택홀의 크기가 수축됨에 따라 콘택 저항은 계속 상승함과 더불어 콘택홀 저면에 폴리머 역시 더욱 많은 분포로 남게 되어 콘택 저항에 악영향을 미치게 되며, 후속 공정에서 파티클 등의 소오스(Source)가 되어 디바이스 특성 및 공정 안정화를 저해시켜 소자의 생산 수율을 떨어뜨리게 된다.In addition, as the size of the via contact hole shrinks, the contact resistance continues to increase, and polymers also remain on the bottom of the contact hole, which adversely affects the contact resistance. This hinders device characteristics and process stabilization, resulting in lower device yields.
일반적인 비아 저항 콘택을 형성하는 경우, 알루미늄에서 콘택을 형성하는데, 이는 후속 공정의 세정 공정에서 콘택의 오버 에칭시 알루미늄에서 발생되는 금속성 폴리머의 제거가 어려워 솔벤트를 이용하여 세정 공정이 수행된다. 그러므로 제조 비용이 증가하게 되고, 솔벤트에 의한 알루미늄이 손실되는 문제점이 발생된다. 또한 후속 공정에서 베리어 메탈과 텅스텐의 증착이 어렵다.In the case of forming a general via resistance contact, a contact is formed in aluminum, which is difficult to remove the metallic polymer generated in the aluminum during the over-etching of the contact in the cleaning process of a subsequent process, and the cleaning process is performed using a solvent. Therefore, the manufacturing cost is increased, there is a problem that the aluminum is lost by the solvent. It is also difficult to deposit barrier metal and tungsten in subsequent processes.
본 발명의 목적은 상술한 문제점을 해결하기 위한 것으로, 알루미늄 계열의 폴리머 형성을 방지하기 위한 비아 콘택 홀 형성 방법을 제공하는데 있다.An object of the present invention is to solve the above-described problems, to provide a via contact hole forming method for preventing the formation of aluminum-based polymer.
상술한 목적을 달성하기 위한 본 발명의 일 특징에 의하면, 반도체 소자의 비아 콘택 홀 형성 방법은, ILD(Interlayer Dielectric) 막이 적층된 반도체 기판 상에 질화막과, 금속막과, 도전막 및 식각 저지막을 차례로 적층하는 단계와, 포토 레지스트 패턴을 마스크로 이용하여 기판이 노출되도록 패터닝하여 비트 라인을 형성하는 단계와, 비트 라인이 형성된 반도체 기판 전면에 IMD(Intermetal Dielectric) 막을 컨포멀하게 적층하고, 상기 IMD 막 위에 산화막을 적층하는 단계와, 상기 산화막 위에 포토 레지스트 패턴을 마스크로 이용하여 상기 IMD 막이 노출되도록 상기 산화막을 식각하는 단계 및 상기 산화막 패턴을 마스크로 이용하여 상기 도전막이 노출되도록 상기 IMD 막과 상기 식각 저지막을 식각하여 콘택 홀을 형성하는 단계를 포함한다. According to an aspect of the present invention for achieving the above object, a method of forming a via contact hole in a semiconductor device includes a nitride film, a metal film, a conductive film, and an etch stop layer on a semiconductor substrate on which an interlayer dielectric (ILD) film is stacked. Sequentially stacking, patterning the substrate to expose the substrate using a photoresist pattern as a mask, forming a bit line, and conformally stacking an intermetal dielectric (IMD) film on the entire surface of the semiconductor substrate on which the bit line is formed. Stacking an oxide film on the film, etching the oxide film to expose the IMD film using a photoresist pattern as a mask on the oxide film, and using the oxide pattern as a mask to expose the conductive film so as to expose the conductive film. Etching the etch stop layer to form a contact hole.
바람직하게는 상기 산화막을 식각하는 단계는 상기 산화막과 상기 식각 저지막의 식각 선택비를 이용하여 식각하고, 상기 콘택 홀을 형성하는 단계는 상기 식각 저지막과 상기 IMD 막의 식각 선택비를 이용하여 식각하여 콘택 홀을 형성한다.Preferably, the etching of the oxide layer may be performed using an etching selectivity between the oxide layer and the etch stop layer, and the forming of the contact hole may be performed using an etching selectivity between the etch stop layer and the IMD layer. Form a contact hole.
따라서 본 발명에 의하면, 알루미늄 계열의 콘텍 홀 형성시, 금속막을 노출시키지 않음으로서 금속에 의한 폴리머를 방지한다.Therefore, according to the present invention, at the time of forming the aluminum-based contact hole, the metal-based polymer is prevented by not exposing the metal film.
이하 본 발명의 실시예를 첨부된 도면에 의거하여 상세히 설명한다.DETAILED DESCRIPTION Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings.
도 1은 본 발명에 따른 비아 콘텍 홀 형성 방법을 순차적으로 설명하기 위한 반도체 소자의 단면도이다.1 is a cross-sectional view of a semiconductor device for sequentially explaining a method of forming a via contact hole according to an exemplary embodiment of the present invention.
도 1a를 참조하면, ILD 막(2)이 적층된 반도체 기판 상에 질화막(4)과, 알루미늄 막(6)과, ARC TiN 막(8) 및 식각 저지막(10)을 차례로 적층한다. 도면에는 미도시되었지만 포토 레지스트 패턴을 마스크로 이용하여 기판이 노출되도록 패터닝하여 비트 라인을 형성한다. 비트 라인이 형성된 반도체 기판 전면에 IMD 막(12)을 컨포멀하게 적층하고, 산화막(14)을 적층한다. 이 때 IMD 막(12)은 200 Å ~ 1000 Å의 두께 범위를 가지고 식각 저지막으로 사용되며, 산화막(14)은 2000 Å의 두께 범위를 가지도록 형성된다. 이어서 산화막(14) 위에 비아 콘택 홀을 형성하기 위한 포토 레지스트 패턴(16)을 형성한다. 여기서 상기 ARC TiN 막(8)은 200 Å ~ 1000 Å의 두께 범위를 가지는 것이 바람직하다. 상기 식각 저지막(10)은 IMD 막(12)과 산화막(14)을 패터닝할 때, IMD 막(12)과 산화막(14)의 식각 선택비를 이용하여 식각 공정이 진행되며 SiON 또는 SiN(Si3N4)로 형성된다. 이 때 주 식각 가스로는 CXHYFZ 계열의 가스를 사용한다.
Referring to FIG. 1A, a
도 1b를 참조하면, 포토 레지스트 패턴(16)을 마스크로 이용하여 IMD 막(12)이 노출되도록 IMD 막(12)과 식각 저지막(10)의 식각 선택비를 이용하여 식각하여 비아 콘택 홀(18)을 형성하고, 포토 레지스트 패턴(16)을 제거한다.Referring to FIG. 1B, the
이어서 도 1c를 참조하면, ARC TiN 막(8)이 노출되도록 IMD 막(12)과 식각 저지막(10)을 건식 식각으로 제거하여 비아 콘택 홀(18a)을 형성한다.Referring to FIG. 1C, the
이는 알루미늄 막을 형성한 후 또는 알루미늄 막의 스택을 형성할 때, 식각 저지막으로 사용할 수 있는 SiN 또는 SiON 등의 제 1 층간 절연막을 증착한 후, SOG 산화막, 주형 산화막(TEOS) 또는 HDP 등의 제 2 층간 절연막을 증착한다. 그리고 층간 절연막의 비아 식각을 제 1 및 제 2 층간 절연막의 식각 선택비를 이용하여 진행한다. 이어서 식각 저지막으로 사용된 SiON 또는 SiN 막을 건식 식각으로 제거하여 알루미늄 막 위의 ARC TiN에서 비아 콘택을 형성하여 알루미늄 막이 노출되지 않도록 하여 금속성의 폴리머 발생을 방지한다.This is performed after forming an aluminum film or when forming a stack of aluminum films, and then depositing a first interlayer insulating film such as SiN or SiON, which can be used as an etch stop film, and then forming a second film such as an SOG oxide film, a template oxide film (TEOS), or an HDP. An interlayer insulating film is deposited. The via etching of the interlayer insulating film is performed using the etching selectivity of the first and second interlayer insulating films. Subsequently, the SiON or SiN film used as the etch stop layer is removed by dry etching to form a via contact in ARC TiN on the aluminum film to prevent the aluminum film from being exposed, thereby preventing the occurrence of metallic polymer.
상술한 바와 같이, 본 발명은 반도체 소자의 콘택 홀 형성시, 산화막과 SiN 또는 SiON 막의 식각 선택비를 이용하여 ARC TiN 막에서 콘택 홀을 형성함으로써, 알루미늄 계열에 의한 금속성 폴리머의 발생을 방지할 수 있다.As described above, the present invention can prevent the generation of the metallic polymer by the aluminum series by forming the contact hole in the ARC TiN film using the etching selectivity of the oxide film and the SiN or SiON film when forming the contact hole of the semiconductor device. have.
이로 인하여 후속 공정 중에 세정 공정시 금속 폴리머를 제거하기 위한 솔벤트 계를 사용할 필요가 없으므로 공정 소요 비용을 줄일 수 있다.This eliminates the need for using a solvent system to remove the metal polymer during the cleaning process during subsequent processes, thereby reducing the cost of the process.
또한 솔벤트 계에 의한 금속 폴리머 세정공정시 발생되는 산화막 손실을 방지하여 후속 베리어 금속막과 텅스텐 막의 증착시 보이드(void)의 발생을 방지할 수 있다.In addition, it is possible to prevent the oxide film loss generated during the metal polymer cleaning process by the solvent system to prevent the generation of voids during the deposition of the subsequent barrier metal film and tungsten film.
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