KR100668514B1 - Device for controlling reservoir capacitor - Google Patents

Abstract

An apparatus for controlling a capacitor is provided to easily adjust the capacitance of the capacitor by varying a plate voltage, which is applied on the capacitor, according to a selected mode. An apparatus for controlling a capacitor includes a multiplexer(100), control blocks(110~130), a logic combination unit(140), voltage supplies(150,160), a MOS(Metal Oxide Semiconductor) capacitor(N1) and a cell capacitor(CC1). The multiplexer selectively outputs control signals. The control blocks outputs a mode select signal according to the outputs from the multiplexer. The logic combination unit includes a NAND gate and an inverter. The first voltage supply(150) supplies an external voltage, a core voltage, and a peripheral voltage to the MOS capacitor. The second voltage supply(160) supplies a ground voltage, a bit line precharge voltage, and a cell plate voltage to the cell capacitor and the MOS capacitor. The MOS capacitor is connected between the first voltage supply and the call capacitor.

Description

Accumulation capacitor control device {Device for controlling reservoir capacitor}

1 is a block diagram of a conventional storage capacitor.

2 is a block diagram of a storage capacitor control device according to the present invention.

3 to 5 show other embodiments of the accumulation capacitor control device according to the present invention.

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an accumulator capacitor control device, and more particularly, a technique for increasing a net die by utilizing a cell capacitor as a mode accumulator capacitor according to a mode setting.

In general, various potentials are required to operate a memory device correctly, and a circuit for generating such potentials is various voltage generators. In such a voltage generator, in order to minimize the voltage drop caused by power consumption during operation of the device, a sufficient amount of power is generated in advance by using a storage capacitor, and the amount consumed by the operation of the device is stored in the storage capacitor again. Is using.

Therefore, in order to prevent the malfunction of the device due to power consumption, that is, the potential drop of the voltage generator, and to control the power supply of the semiconductor device more stably, a storage capacitor of sufficiently large capacity is required.

The above-mentioned accumulation capacitor mainly uses a gate capacitor using MOS. That is, the capacitance of the gate capacitor is determined by the thickness of the gate oxide by the insulator.

1 is a block diagram of such a conventional storage capacitor.

The conventional well capacitor 20 is applied with two or more various power supply voltages provided to a semiconductor memory device, that is, an external power supply voltage VEXT, a core voltage VCORE, and a ferry voltage VPERI applied through the power supply unit 10 through a gate terminal. do. In addition, the plate voltage of the well capacitor 20 using the MOS is always limited to the ground voltage.

The well capacitor 20 having such a configuration supplies a ground voltage to a source and a drain, and supplies a specific voltage to a gate to implement a storage capacitor. The capacitance of the storage capacitor thus implemented is the well capacitor 20. It is determined by the voltage Vin applied to the gate of and the ground voltage difference. That is, the capacitance of the accumulation capacitor is determined by the voltage Vin- ground voltage Vss.

Therefore, the capacitance must be changed according to the operation of the semiconductor device for stable operation of the semiconductor device. In the conventional storage capacitor and the decoupling capacitor, the storage capacitor once set cannot be changed to another storage capacitor. In addition, the plate voltage of the capacitor is always fixed so that the plate voltage cannot be arbitrarily changed.

Accordingly, there is a problem in that it is difficult to provide enough capacitance as necessary and fluidly, making it difficult to contrast noise, and supplying a stable voltage.

The present invention was created to solve the above problems, and in particular, it is possible to increase the net die by using a cell capacitor as a mode storage capacitor according to the mode setting. have.

In addition, an object of the present invention is to be able to change the level of the accumulation capacitor by selecting the plate voltage of the accumulation capacitor according to the mode setting.

Accumulation capacitor control apparatus of the present invention for achieving the above object, the cell capacitor for accumulating the power supply voltage applied through the power supply; And mode control means for selectively blocking the connection of the power supply unit and the cell capacitor depending on whether the operation mode is the normal operation mode or the test mode.

In addition, the present invention includes a first power supply for controlling the supply of a plurality of first voltage having different levels; Mode control means for outputting a mode selection signal having a different state according to a combination of a plurality of control signals for mode setting; A power controller configured to selectively supply a first voltage to the cell capacitor according to the mode selection signal; And a cell capacitor used as an accumulation capacitor for accumulating the first voltage applied through the power control unit.

Hereinafter, with reference to the accompanying drawings will be described in detail an embodiment of the present invention.

2 is a block diagram of a storage capacitor control device according to the present invention.

The present invention includes a multiplexer 100, control blocks 110 to 130, logic combination unit 140, power supply unit 150, 160, MOS capacitor N1 and cell capacitor CC1.

Here, the multiplexer 100 selectively outputs control signals CON1 to CON3. The control blocks 110 to 130 output a mode selection signal for controlling the mode selection according to the output of the multiplexer 100.

The logic combination unit 140 includes a NAND gate ND1 and an inverter IV1. At this time, the NAND gate ND1 performs a NAND operation on a mode selection signal that is an output of the control blocks 110 to 130. Inverter IV1 inverts the output of NAND gate ND1.

In addition, the power supply unit 150 supplies an external voltage VEXT, a core voltage VCORE, a ferry voltage VPERI, and the like to the MOS capacitor N1. The power supply unit 160 supplies the ground voltage VSS, the ground voltage VSSA which is the voltage source of the cell array, the bit line precharge voltage VBLP, and the cell plate voltage VCP to the bulk of the cell capacitor CC1 and the MOS capacitor N1.

The MOS capacitor N1 includes an NMOS capacitor connected between the power supply unit 150 and the cell capacitor CC1 to which an output of the inverter IV1 is applied through a gate terminal and an output of the power supply unit 160 is applied to a bulk.

3 is another embodiment of an accumulation capacitor control device according to the present invention.

The present invention includes a multiplexer 200, control blocks 210 to 230, logic combination unit 240, power supply units 250 and 260, MOS capacitor P1, and cell capacitor CC1.

Here, the multiplexer 200 selectively outputs the control signals CON1 to CON3. The control blocks 210 to 230 output a mode selection signal for controlling the mode selection according to the output of the multiplexer 200.

The logic combination unit 240 includes a NAND gate ND2 and an inverter IV2. At this time, the NAND gate ND2 performs a NAND operation on a mode selection signal that is an output of the control blocks 210 to 230. Inverter IV2 inverts the output of NAND gate ND2.

In addition, the power supply unit 250 supplies the external voltage VEXT, the core voltage VCORE, the ferry voltage VPERI, and the like to the MOS capacitor P1. The power supply unit 260 supplies the ground voltage VSS, the ground voltage VSSA which is the voltage source of the cell array, the bit line precharge voltage VBLP, the cell plate voltage VCP, and the like to the bulk of the cell capacitor CC2 and the MOS capacitor P1.

The MOS capacitor P1 includes a PMOS capacitor connected between the power supply 250 and the cell capacitor CC2 to which an output of the inverter IV2 is applied through a gate terminal, and an output of the power supply 250 is applied to a bulk.

The cell capacitors CC1 and CC2 of the present invention having such a configuration are provided in the ferry region of the semiconductor device, and accumulate capacitors such as core voltage VCORE, cell array voltage VDDA, power supply voltage VDD, and voltage VDDLL of a delay locked loop. Used as

At this time, the cell capacitors CC1 and CC2 are selected by the multiplexer 100 so that the cell capacitors CC1 and CC2 can be stably used among the control signals CON1 to CON3 when the externally applied voltage is 1.8 V or less. do.

On the other hand, in the worst case like the burn-in test mode, the control signal CON2 indicating the test operation mode among the control signals CON1 to CON3 is selected by the multiplexer 100 to open each voltage source with the cell capacitors CC1 and CC2. This prevents the destruction of cell capacitors CC1 and CC2.

In addition, the plate voltage source of the cell capacitors CC1 and CC2 may be changed using the mode selection signal. That is, the capacitance can be controlled by arbitrarily determining the plate capacitance from the power supply voltage VDD to the back bias voltage VBB level according to the mode.

4 is another embodiment of an accumulation capacitor control device according to the present invention.

The present invention includes a multiplexer 300, control blocks 310 to 330, logic combination unit 340, power supply unit 350, 370, power control unit 360 and MOS capacitor MC.

Here, since the configuration of the multiplexer 300, the control blocks 310 to 330, the logic combination unit 340, and the power supply units 350 and 370 are the same as those of FIGS. 2 and 3, a detailed description thereof will be omitted. However, the embodiment of FIG. 4 may change the gate voltage level of the MOS capacitor MC by the power control unit 360 controlled according to the mode setting, and may change the plate voltage of the MOS capacitor according to the power supply unit 370. .

5 is another embodiment of an accumulator capacitor control device according to the present invention.

The configuration of the multiplexer 300, the control blocks 310 to 330, the logic combination unit 340, and the power supply units 350 and 370 according to the embodiment of FIG. 5 is the same as that of FIG. 4, except that the cell capacitor CC3 is the storage capacitor. Using is different from FIG. 4.

Referring to the operation of the present invention having such a configuration as follows.

The capacitance of cell capacitors CC1-CC3 is more than three times per unit area larger than NMOS capacitors or NMOS Well capacitors whose capacitance capacity is determined by the gate oxide thickness. Accordingly, the present invention enables the net die to be increased by using the cell capacitors CC1 to CC3 as storage capacitors according to the mode setting.

Of course, compared to the conventional storage capacitor whose capacitance is determined by the gate oxide thickness, the cell capacitor tends to be destroyed when the plate voltage and the applied voltage difference are large.

For example, in the normal mode, cell capacitors CC1 to CC3 are used as accumulation capacitors of the core voltage VCORE, and the plate voltage is assumed to be ground. At this time, when the external applied voltage is 1.8V, the voltage difference applied to the cell capacitors CC1 to CC3 is typically set using the core voltage VCORE = 1.4V to 1.6V, and the capacitance of the cell capacitors CC1 to CC3 is the core voltage VCORE-ground voltage VSS. The difference is set at 1.6V-0V.

However, in a test mode such as burn-in mode, the core voltage VCORE is set to 2.1V. In this case, the cell capacitor may be destroyed by a Worst state in which the capacitance difference between the cell capacitors CC1 to CC3 is 2.1V@125 degree.

However, in the present invention, since the control capacitors CON1 to CON3 indicating the control mode are combined and there is no need to use the accumulation capacitor in the burn-in test mode, the mode of opening the cell capacitors CC1 to CC3 and the core voltage VCORE is applied. Therefore, the cell capacitances CC1 to CC3 can be stably used as the storage capacitors by using the control signals CON1 to CON3 input differently according to the mode setting.

That is, the cell capacitors CC1 to CC3 may be used as voltage VDDA, which is a voltage source of the cell array, voltage VDDLL, which is a voltage source of a delay locked loop, or an accumulation capacitor of an externally applied voltage. In burn-in test mode, however, each voltage source can be opened.

As a result, the capacitance of the cell capacitors CC1 to CC3 is about 30 fF, and the MOS capacitor capacitance is about 6 to 9 fF, so that an area securing gain of about 4,5 times can be achieved. In addition, the present invention allows the plate voltage of the MOS capacitor MC to be arbitrarily controlled, as in the embodiment of FIG. 4, so that the accumulation of capacitance or the decoupling capacitance can be arbitrarily controlled.

As described above, the present invention provides the following effects.

First, a cell capacitor is provided in the ferry region, and a net die can be increased by using the cell capacitor as a mode storage capacitor according to a mode setting.

Second, the capacitance of the storage capacitor can be changed by selecting the plate voltage of the storage capacitor according to the mode setting.

Third, it provides the effect of supplying a stable voltage by changing the plate voltage of the MOS capacitor according to the mode.

In addition, a preferred embodiment of the present invention is for the purpose of illustration, those skilled in the art will be able to various modifications, changes, substitutions and additions through the spirit and scope of the appended claims, such modifications and changes are the following claims It should be seen as belonging to a range.

Claims (16)

A cell capacitor accumulating a power supply voltage applied through the power supply unit; And And mode control means for selectively disconnecting the power supply from the live cell capacitor depending on whether the battery is in a normal operation mode or a test mode. 2. The accumulator capacitor control device according to claim 1, wherein the mode control means further comprises plate voltage control means for changing a plate capacitance of the cell capacitor. The accumulator capacitor control device according to claim 1, wherein the cell capacitor is formed in a ferry region of a semiconductor device. A first power supply for controlling supply of a plurality of first voltages having different levels; Mode control means for outputting a mode selection signal having a different state according to a combination of a plurality of control signals for mode setting; A power controller configured to selectively supply the first voltage to the cell capacitor according to the mode selection signal; And And a cell capacitor used as an accumulation capacitor for accumulating the first voltage applied through the power control unit. 5. The cell capacitor of claim 4, wherein the cell capacitor is applied with the first voltage through the power control unit when the control signal is in a normal operation mode, and according to control of the power control unit when the control signal is in a burn-in test mode. Accumulation capacitor control device characterized in that the application of one voltage is cut off. The accumulator capacitor control device according to claim 4, wherein the first power supply unit selects and supplies any one of an external power voltage, a core voltage, a ferry voltage, a cell array applied voltage, and a delayed synchronization loop applied voltage. The accumulator capacitor control device of claim 4, further comprising a second power supply unit configured to select one of a plurality of second voltages having different levels and supply the selected voltage to the cell capacitor according to the mode selection signal. . 8. The storage capacitor control device of claim 7, wherein the second power supply unit selects and supplies any one of a ground voltage, a cell array applied voltage, a bit line precharge voltage, and a cell plate voltage. The method of claim 4, wherein the mode control means A multiplexer for selecting and outputting any one of the plurality of control signals; A plurality of control blocks for controlling the output of the multiplexer to output a plurality of mode selection signals; And And a logic combination unit for logically combining and outputting the plurality of mode selection signals. 10. The apparatus of claim 9, wherein the logic combination unit comprises: a NAND gate NAND-operating the plurality of mode selection signals; And And an inverter for inverting the output of the NAND gate. The accumulating capacitor control device of claim 4, wherein the power control unit comprises a MOS capacitor connected between the first power supply unit and the cell capacitor to receive the mode selection signal through a gate terminal. 12. The accumulation capacitor control device of claim 11, wherein the MOS capacitor is an NMOS capacitor. The method of claim 12, further comprising a third power supply for selecting any one of the voltage from the power supply voltage level to the back bias voltage level range in accordance with the mode selection signal to supply to the plate of the NMOS capacitor. Accumulation capacitor control unit. 12. The accumulation capacitor control device of claim 11, wherein the MOS capacitor is a PMOS capacitor. 15. The accumulator capacitor control device according to claim 14, wherein said PMOS capacitor is applied with said first voltage to a plate. The accumulator capacitor control device according to claim 4, wherein the cell capacitor is formed in a ferry region of a semiconductor device.

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