KR100660247B1 - Plasma display panel set - Google Patents

Abstract

The present invention relates to a plasma display panel set. In the present invention, one dummy address electrode is disposed on an adjacent surface of the start address electrode and the end address electrode located on the outermost surface of the rear base plate, and the dummy address electrodes are arranged. The electrodes are electrically connected to the control circuit block described above.

In this case, since the dummy address electrodes of the present invention can form a series of electrical connections with the control circuit block, unlike the prior art, when the present invention is achieved, the control circuit block is selected as the start and end address electrodes. When the erase pulses are input, the same erase erase pulses can be input to these dummy address electrodes, and as a result, the wall charge erase state between the start / end display cells and the dummy display cells is changed to the same trend. Can be induced.

As described above, when the wall charge erasing states between the start and end display cells and the dummy display cells are equalized, an effect of preventing erasing errors of the start and end display cells due to adverse effects of the dummy display cells in the production line is obtained in advance. As a result, it is possible to easily secure the effect that the image quality of the PDP finally shipped is greatly improved.

Description

Plasma display panel set {Plasma display panel set}

1 is an exemplary view showing a plasma display panel set to which the present invention is applied.

2 is an exemplary diagram conceptually showing an electrical connection relationship of a plasma display panel set to which the present invention is applied.

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a plasma display panel set (hereinafter referred to as a " PDP set "), and more particularly to a series of electrical connections between dummy address electrodes and a control circuit block. When the select erase pulse is input to the start / end address electrodes, the select erase pulse of the same value can also be input to the dummy address electrodes, thereby starting and ending by the influence of the dummy display cells. The present invention relates to a PDP set capable of preventing erasing errors of display cells in advance.

Recently, various problems regarding the function of the CRT (Cathod Ray Tube) have been raised, and various kinds of display apparatuses that can overcome the disadvantages of the CRT have been developed.

Among such various display devices, in particular, interest in PDP is increasing because PDP has an excellent advantage of displaying a large screen more clearly than conventional CRT.

PDP according to the prior art is, for example, US Patent No. 6078139 "Front panel for plasma display", US Patent No. 6075319 "Plasma display panel device and a method of manufacturing the same (Plasma display panel device) and method for fabricating the same ", US Patent No. 6069446" Plasma display panel with ring-shaped loop electrodes, US Patent No. 6066917 "Plasma display panel display panel, US Pat. No. 6034656, "Plasma display panel and method of controlling brightness of the same."

In addition, various driving methods of the PDP in this conventional technique are described, for example, in US Patent Publication No. 6054970 "Method for driving an AC-driven PDP, US Patent Publication No. 5952986" Driving method and display device (Driving method of an AC-type PDP and the display device).

Typically, such a conventional PDP is composed of a combination of front and rear base plates that are integrally sealed and coupled to each other while facing each other. In this case, a plurality of X and Y sustain electrodes are stripped on one surface of the front base plate. ) Are arranged to form a separate tip, and similarly, a plurality of address electrodes are arranged to form a separate tip of a stripe shape on one surface of the rear base plate.

The X and Y sustain electrodes and the address electrodes receive a predetermined voltage pulse from the control circuit block, thereby rapidly discharging the gas sealed between the front base plate and the rear base plate.

In this case, one dummy address electrode is further disposed on the outermost surface of the rear base plate, that is, adjacent surfaces of the start address electrode and the end address electrode corresponding to the first display line and the last display line. These dummy address electrodes serve to assist the manufacturing process of the above-described address electrodes by providing the effect of maximizing the process margin at the outermost surface of the rear base plate. These dummy address electrodes are formed to be electrically separated from an external control circuit block.

On the other hand, various researches for smoothly driving the conventional PDP have been actively conducted, so-called PDP driving, which is called an address-display separation method (hereinafter referred to as an "ADS" method). The method has been in the spotlight recently.

In the case of this ADS method, since the display period and the address period are strictly separated, when this ADS method is actually applied to the driving of the PDP, the production line can obtain the advantage of driving the multi-gradation of 256 or more gray levels at high speed. have.

Generally, in the conventional ADS system, a time for displaying and maintaining one image on the entire screen, that is, a frame is divided into several sub-fields, and each sub-field is reset. (Reset period), Address discharge period (Sustain discharge period), and sustain discharge period (Sustain discharge period) is divided into the driving.

According to this conventional ADS method, when the above-mentioned address discharge period is performed, for example, the control circuit block applies a series of selective erasing pulses to specific address electrodes, whereby, other than the selected display cells By allowing the wall charges of unnecessary cells to be stably erased, a basic condition is provided in which a series of image information can be quickly displayed to the outside of the PDP.

However, according to the conventional selective erasing method, when a series of address discharge periods proceed, an unexpected erasure error occurs in the start and end display cells corresponding to the toxic, start and end address electrodes. Is caused.

Recently, as the research on the erasing error of the start and end display cells has progressed rapidly, it has been confirmed that the electrical arrangement structure of the above-mentioned dummy address electrodes greatly affects the erase error of the start and end display cells. If this is mentioned in detail as follows.

As mentioned above, the start and end address electrodes that control charge formation of the start and end display cells are disposed adjacent to the control circuit block and the dummy address electrodes electrically separated from each other, in this case, the start and end display cells. In addition, a dummy display cell corresponding to the dummy address electrodes is disposed in an adjacent portion thereof.                         

In this state, when the above-described address discharge period arrives and a series of selective erasing pulses are input from the control circuit block to the start and end address electrodes, the start and end address electrodes are formed on the walls of the start and end display cells. The charge is reliably erased.

However, as described above, since the dummy address electrodes have a structure electrically separated from the control circuit block, even if a series of selective erase spreads are input to the start and end address electrodes during the address discharge period, the corresponding dummy erase electrodes may be provided. The address electrodes are not affected by the selective erasing pulse, so that the dummy display cells under the influence of the dummy address electrodes also maintain the initial wall charge state regardless of the input of the selective erasing pulse. The charge state of adjacent start and end display cells is adversely affected.

For example, the dummy display cells adversely affect the start / end display cells under the influence of the selective erasing pulse, thereby unnecessarily transferring the wall charges formed therein into the start / end display cells, thereby eliminating the wall charge erasing state. This will adversely affect the formation of unnecessary wall charges inside the start / end display cells.

In this case, an abnormality is caused in the light emitting process of the display cells, and as a result, the finally released PDP has no choice but to maintain image quality below a certain level.

Of course, in order to prevent such a problem in advance, it is a first priority to remove the dummy address electrodes altogether, but in this case, it is difficult to secure a process margin. The situation is not prepared.

Accordingly, an object of the present invention is to allow a series of electrical connections to be formed between the dummy address electrodes and the control circuit block, whereby when the select erase pulse is input to the start and end address electrodes, the dummy address electrode By allowing the selective erase pulses of the same value to be inputted to each other, the wall charge erase state between the start / end display cells and the dummy display cells can be changed to the same trend.

Another object of the present invention is to equalize the wall charge erasing state between the start and end display cells and the dummy display cells, thereby preventing erasing errors of the start and end display cells due to adverse effects of the dummy display cells.

Another object of the present invention is to prevent the erasing error of the start and end display cells in advance, thereby maintaining the image quality of the PDP finally shipped to a certain level or more.

Still other objects of the present invention will become more apparent from the following detailed description and the accompanying drawings.

In order to achieve the above object, the present invention discloses a PDP set consisting of a combination of front and rear base plates, X and Y sustain electrodes, address electrodes, display cells and control circuit blocks.

In this case, the above-mentioned front and rear base plates face each other in a state in which a certain amount of discharge gas is received and form an integrally sealed structure. The X and Y sustain electrodes and the address electrodes are formed on one surface of the front and rear base plates. The display cells are spaced apart and arranged in parallel and arranged in parallel, and the above-described display cells are located at intersections between the X and Y sustain electrodes and the address electrodes, and the interface space between the front and rear base plates. Is formed at regular intervals, and the control circuit block selectively controls the light emission of display cells by applying a series of control pulses to the X and Y sustain electrodes and the address electrodes from time to time.

At this time, in the present invention, one dummy address electrode is disposed on the adjacent surfaces of the start address electrode and the end address electrode located on the outermost surface of the rear base plate, and the dummy address electrodes are disposed. It is electrically connected to the above-described control circuit block.

In this case, since the dummy address electrodes of the present invention can form a series of electrical connections with the control circuit block, unlike the prior art, when the present invention is achieved, the control circuit block is selected as the start and end address electrodes. When the erase pulses are input, the same erase erase pulses can be input to these dummy address electrodes, and as a result, the wall charge erase state between the start / end display cells and the dummy display cells is changed to the same trend. Can be induced.

As described above, when the wall charge erasing states between the start and end display cells and the dummy display cells are equalized, an effect of preventing erasing errors of the start and end display cells due to adverse effects of the dummy display cells in the production line is obtained in advance. As a result, it is possible to easily secure the effect that the image quality of the PDP finally shipped is greatly improved.                     

Hereinafter, a PDP set according to the present invention will be described in more detail with reference to the accompanying drawings.

As shown in FIG. 1, the PDP 50 for implementing the present invention, for example, an indirect discharge type PDP, consists of a combination of a front substrate unit 10 and a rear substrate unit 30 facing each other.

In this case, a series of seal lines (not shown) are formed outside the front substrate unit 10 and the rear substrate unit 30 to seal the front substrate unit 10 and the rear substrate unit 30 smoothly. Assist in maintaining state.

A discharge gas, for example, a penning mixed gas, is accommodated between the front substrate unit 10 and the rear substrate unit 30 sealed by the seal line. The phenning gas has a configuration in which argon (Ar), xenon (Xe), and the like are mixed with neon gas, and have a characteristic of easily discharging even at a low voltage.

At this time, as shown in the figure, the front substrate unit 10 is, for example, a pair of the front base plate 11 of the glass material, and the one side of the rear substrate unit 30 side of the front base plate 11, For example, the X-Y sustain electrodes 12 and 14 and the front dielectric layer 13 formed of an indium tin oxide (ITO) material are formed.

In this case, the X and Y sustain electrodes 12 and 14 are spaced apart from each other by a front end of the front base plate 11 facing the rear substrate unit 30 to form a continuous structure in parallel. The front dielectric layer 13 has a structure in which a front surface of the front base plate 11 is coated with a predetermined thickness so that the front X and Y sustain electrodes 12 and 14 are covered.                     

At this time, the X sustain electrodes 12 receive a write pulse, a sustain pulse, and the like from the control circuit block 100, and then use the write pulse, the sustain pulse, and the like to separate the individual display cells 36 to be described later. It plays a role of generating wall charge therein and also maintains a discharge state of the discharge gas contained in the individual display cells 36.

In addition, the Y sustain electrodes 14 receive scan pulses, sustain pulses, and the like from the control circuit block 100, and then use the scan pulses, the sustain pulses, and the like, and output image data to individual display cells 36. In addition to scanning and similarly to the aforementioned X sustaining electrodes 12, the display device serves to continuously maintain the discharge state of the discharge gas contained in the individual display cells 36.

At this time, a protective film layer (not shown), for example, an MgO layer is further disposed on the outermost surface of the front dielectric layer 13, and the protective film layer serves to improve the discharge characteristics of the front dielectric layer 13 described above.

Meanwhile, the rear board unit 30 corresponding to the front board unit 10 mentioned above is similar to the front board unit 10 of the front, for example, the rear base plate 31 made of glass, and the rear base plate. And a combination of the address electrodes 32 and the rear dielectric layer 33 formed on the upper side of the front base plate 11.

In this case, the address electrodes 32 are disposed on one surface of the rear base plate 31 facing the front base plate 11 in a state perpendicular to the arrangement direction of the X and Y sustain electrodes 12 and 14 described above. Spaced apart in a stripe shape, a parallel continuous array is formed, and the rear dielectric layer 33 forms a structure in which a thickness is applied to one surface of the rear base plate 31 so that the address electrodes 32 are covered.

In this case, the address electrodes 32 serve to selectively designate the individual display cells 36 to be subjected to the actual display discharge by receiving, for example, a selection erase pulse from the control circuit block 100.

Here, a plurality of partition walls 34 are erected on one surface of the rear dielectric layer 33 and arranged in a line.

These barrier ribs 34 are formed of the front substrate unit 10 and the rear substrate unit 30, if the aforementioned front substrate unit 10 and rear substrate unit 30 are integrally sealed by seal lines. By partitioning the interface space therebetween to a certain size, the plurality of display cells 36 corresponding to the above-described X and Y sustain electrodes 12 and 14 between the front substrate unit 10 and the rear substrate unit 30. ) Are defined individually. In this case, the above-described discharge gas is accommodated in the individual display cells 36.

In this case, R, G, and B phosphors 35 are further coated inside the individual display cells 36 covering the inner surfaces of the partition walls 34, and the R, G, and B phosphors 35 are described above. When the discharge gas contained in each of the display cells 36 is discharged by driving one of the X and Y sustain electrodes 12 and 14 and the address electrodes 32, the ultraviolet rays of a predetermined size are emitted. By colliding with the ultraviolet rays, R, G, and B colors serve to induce light to be emitted toward the front substrate unit 10, for example.

Here, the R, G, and B phosphors 35 are continuously arranged in the color order of, for example, "RGB, RGB, ...." along the transverse direction of each of the individual display cells 36. When the B phosphor 35 emits ultraviolet rays by the above-described discharge process of the discharge gas, the B phosphor 35 collides with the ultraviolet rays so that the R, G, and B colors of light are discharged to the front substrate unit side ( 10) to emit light. The color arrangement of the R, G and B phosphors 35 may be variously modified according to the situation of the production line.

In this case, when the front dielectric layer 13 is discharged in each of the display cells 36 to generate a plurality of discharge ions, each of the X and Y sustain electrodes 12 and 14 is discharged. Similarly, the rear dielectric layer 33 discharges each of the display cells 36 to generate a plurality of discharge ions, and thus, each of the address electrodes 32 is discharged. Play a role in protecting them.

Meanwhile, as shown in FIG. 2, the aforementioned control circuit block 100 includes an address driver 101, an X common driver 103, a Y scan driver 102, a Y common driver 104, and a control unit ( 109).

In this case, the previous address driver 101 serves to input a selective erase pulse to the address electrodes 32 while being electrically connected to the address electrodes 32, and the X common driver 103 is X. In a state of being electrically connected to the sustain electrodes 12, the write pulse and the sustain pulse are input to the X sustain electrodes 12.

In addition, the Y scan driver 102 serves to input a scan pulse to the Y sustain electrodes 14 while being electrically connected to the Y sustain electrodes 14, and the Y common driver. In operation 104, the sustain pulses are input to the Y sustain electrodes 14 while the Y scan electrodes 102 are electrically connected to the Y sustain electrodes 14.

On the other hand, the preceding control unit 109 is electrically connected to the address driver 101, the X and Y common drivers 103 and 104, and the Y scan driver 102, from an external electric device such as a computer (not shown). The address driver 101, the X and Y common drivers 103 and 104, and the Y scan driver 102 are simultaneously controlled by a series of input clock signals, display data signals, and horizontal and vertical signals.

In this case, the control unit 109 is dedicated to the display data control unit 105 which exclusively controls the address driver 101, the Y scan driver 102, the X common driver 103, and the Y common driver 104. It consists of a combination of the panel drive control unit 106 to control, in this case, the panel drive control unit 106 is a scan driver control unit 107 and X common driver 103, Y dedicated to control the Y scan driver 102 It consists of a combination of the common driver control unit 108 which exclusively controls the common driver 104.

On the other hand, as mentioned above, the PDP 50 of the present invention has a plurality of display cells at the intersections of the X and Y sustain electrodes 12 and 14 and the address electrodes 32 respectively formed in directions perpendicular to each other. With the reference numeral 36, a series of electrical connections are formed with the above-described control circuit block 100, thereby implementing a PDP set having a completed structure.

In this case, the start address electrode 32a and the end address electrode 32c defining the first display line and the last display line of the PDP are disposed in the outermost region of the rear base plate 31 mentioned above. One dummy address electrodes 32b and 32d are further disposed on the outer surfaces of the address electrodes 32a and 32c, respectively. The dummy address electrodes 32b and 32d provide the effect of maximizing the process margin at the outermost surface of the rear base plate 31, so that the above-described manufacturing process of the address electrodes 32 can be made more smoothly. It serves to assist.

In this case, the dummy address electrodes 32b and 32d are electrically connected to the above-described control circuit block 100, for example, the address driver 102. For example, in the present invention, the dummy address electrodes 32b and 32d are electrically connected in common with the start and end address electrodes 32a and 32c through the contacts P1 and P2. To form a series of electrical connection structure with the above-described control circuit block 100.

The electrical connection structure of the dummy address electrodes 32b and 32d constitutes the gist of the present invention. In this case, the production line may obtain an advantage that the erasing error of the start / end display cells as described above is easily solved. Can be. Looking at this in detail as follows.

As shown in the figure, the start and end address electrodes 32a and 32c, which influence charge formation of the start and end display cells 36a and 36c, have dummy address electrodes 32b and 32d at their periphery. In this case, the start and end display cells 36a and 36c also have a structure in which the dummy address electrodes 36b and 36d are adjacent to each other.                     

In this state, when a series of selective erasing pulses output from the control circuit block 100, for example, the address driver 102, are input to the start and end address electrodes 32a and 32c, the start and end address electrodes are applied. The fields 32a and 32c reliably erase the wall charges of the start and end display cells 36a and 36c.

At this time, since the dummy address electrodes 32b and 32d of the present invention form an electrical connection relationship with the control circuit block 100 unlike the prior art, a series of start and end address electrodes 32a and 32c are used. When the select erase spread is input, the dummy address electrodes 32b and 32d of the present invention are affected by the select erase pulse, similarly to the start and end address electrodes 32a and 32c. The display cells 36b and 36d are brought into a wall charge erasing state similarly to the adjacently placed start and end display cells 36a and 36c, whereby the charges of the adjacent start and end display cells 36a and 36c are disposed. It will not adversely affect the condition.

In other words, since the dummy address electrodes 32b and 32d of the present invention can form a series of electrical connections with the control circuit block 100, unlike the prior art, when the present invention is achieved, the control circuit block ( When the selection erase pulses are input to the start and end address electrodes 32a and 32c, the selection erase pulses having the same value can be input to the dummy address electrodes 32b and 32d. It is possible to induce the wall charge erase state between the end display cells 36a and 36c and the dummy display cells 36b and 36d to be changed to the same trend.

As described above, when the wall charge erasing states between the start and end display cells 36a and 36c and the dummy display cells 36b and 36d are equalized, the production line is adversely affected by the dummy display cells 36b and 36d. The effect of erasing errors of the start / end display cells 36a and 36c due to this can be obtained in advance. As a result, an effect of greatly improving the image quality of the finally shipped PDP can be easily obtained.

Thereafter, the control circuit block 100 repeatedly applies the aforementioned scan pulses, sustain pulses, selective erase pulses, and the like to the X and Y sustain electrodes 12 and 14 and the address electrodes 32. The light emitting state of the display device 36 is selectively adjusted, and thus, the image information display operation of the PDP can be performed smoothly.

As described above, in the present invention, a series of electrical connections are formed between the dummy address electrodes and the control circuit block, so that when the selective erase pulse is input to the start / end address electrodes, the dummy By allowing the selection erase pulses having the same value to be input to the address electrodes, the erasing error of the start / end display cells due to the influence of the dummy display cells can be prevented in advance.

This invention shows the overall useful effect in the various types of PDP produced in the production line.

And while certain embodiments of the invention have been described and illustrated, it will be apparent that the invention may be embodied in various modifications by those skilled in the art.

Such modified embodiments should not be understood individually from the technical spirit or point of view of the present invention and such modified embodiments should fall within the scope of the appended claims of the present invention.

As described in detail above, in the PDP set according to the present invention, one dummy address electrode is disposed on the adjacent surface of the start address electrode and the end address electrode located on the outermost surface of the rear base plate, and the dummy address electrodes are arranged. The electrodes are electrically connected to the control circuit block described above.

In this case, since the dummy address electrodes of the present invention can form a series of electrical connections with the control circuit block, unlike the prior art, when the present invention is achieved, the control circuit block is selected as the start and end address electrodes. When the erase pulses are input, the same erase erase pulses can be input to these dummy address electrodes, and as a result, the wall charge erase state between the start / end display cells and the dummy display cells is changed to the same trend. Can be induced.

As described above, when the wall charge erasing states between the start and end display cells and the dummy display cells are equalized, an effect of preventing erasing errors of the start and end display cells due to adverse effects of the dummy display cells in the production line is obtained in advance. As a result, it is possible to easily secure the effect that the image quality of the PDP finally shipped is greatly improved.

Claims (2)

A front base plate and a rear base plate which are integrally sealed while facing each other in a state of accommodating a predetermined amount of discharge gas; A plurality of X-Y sustaining electrodes spaced at regular intervals on one surface of the front base plate at regular intervals and arranged in parallel; A plurality of address electrodes arranged perpendicular to the X and Y sustain electrodes and spaced apart at predetermined intervals from one end of the rear base plate at a predetermined end in parallel to each other; A plurality of display cells positioned at intersections between the X and Y sustain electrodes and the address electrodes and defining the space for discharging the discharge gas, and partitioning the interface space between the front and rear base plates at regular intervals. and; And a control circuit block for applying a series of control pulses to the X and Y sustain electrodes and the address electrodes from time to time to selectively discharge the discharge gas and sequentially control whether the display cells emit light. Among the address electrodes, one dummy address electrode is arranged in pairs on the adjacent surfaces of the start address electrode and the end address electrode located on the outermost surface of the rear base plate, and the dummy address electrodes are arranged in the control circuit block. And a plasma display panel set electrically connected to the plasma display panel. The plasma display panel set of claim 1, wherein the dummy address electrodes are electrically connected to the start address electrode and the end address electrode.

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