KR100656456B1 - Apparatus and method for on die termination of semiconductor memory - Google Patents

Abstract

An on-die termination apparatus of a semiconductor memory and a method thereof are provided to normally perform data input and data output by preventing a code value adjustment error. An ODT(On Die Termination) input driving unit(100) outputs a first line voltage by dividing an input voltage by a resistance ratio according to a first code comprising at least two bits. A first ODT control unit(200) counts the first code or resets the first code at a first set value according to whether the first line voltage coincides with a reference voltage. An ODT output driving unit(300) outputs a second line voltage by dividing an input voltage by a resistance ratio according to the first code and a second code comprising at least two bits. A second ODT control unit(400) counts the second code or resets the second code at a second set value according to whether the second line voltage coincides with the reference voltage.

Description

Apparatus and Method for On Die Termination of Semiconductor Memory

1 is a block diagram showing a configuration of an on-die termination device of a semiconductor memory according to the prior art;

2 is a block diagram showing the configuration of an on-die termination device of a semiconductor memory according to the present invention;

3 is a circuit diagram illustrating a configuration of an ODT input driver of FIG. 2;

4 is a circuit diagram illustrating a configuration of a first control unit of FIG. 2;

5 is a circuit diagram showing the configuration of the ODT output driver of FIG. 2;

6 is a circuit diagram illustrating a configuration of a second control unit of FIG. 2;

7 is a timing diagram illustrating a signal waveform related to first code adjustment according to the present invention;

8 is a timing diagram illustrating a second code adjustment related signal waveform according to the present invention.

<Description of Symbols for Main Parts of Drawings>

100: ODT input driver 200: first ODT control unit

210: first comparator 220: first register

230: first control unit 300: ODT output driver

400: second ODT controller 410: second comparator

420: second register 430: second control unit

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to semiconductor memories, and more particularly to apparatus and methods for on die termination of semiconductor memories.

In general, when a signal transmitted through a bus line having a predetermined impedance encounters a bus line having a different impedance, part of the signal is lost. Therefore, reducing the signal loss by matching the impedances of the two bus lines is referred to as on die termination.

As shown in FIG. 1, the on-die termination device according to the related art is modeled in the same manner as the data input driver and has a power supply voltage VDDQ with a resistance ratio according to Pcode <0: N> (hereinafter referred to as a first code). The ODT input driver 10 which outputs the first line voltage P_out by dividing the voltage, compares the first line voltage P_out with the reference voltage Vref according to the first enable signal P_en, and compares the first voltage. A first comparator 20 for outputting a result signal Pcmp_out, a first register 30 for counting the first code according to the first comparison result signal Pcmp_out, and modeled in the same manner as a data output driver The ODT output driver 40 and the second enable signal N_en which output the second line voltage N_out by dividing the power supply voltage VDDQ with a resistance ratio according to <0: N> (hereinafter referred to as a second code). The second comparison result by comparing the second line voltage (N_out) and the reference voltage (Vref) according to And a second register 60 for counting the second code according to the second comparison part 50, and the second comparison result signal (Ncmp_out) for outputting a signal (Ncmp_out).

In an initial operation, an initial first code preset in the first register 30 is input to the ODT input driver 10.

The ODT input driver 10 outputs a resistor connected according to the first code and a first line voltage P_out corresponding to the line impedance detection resistor ZQ.

Subsequently, the first comparator 20 compares the first line voltage P_out and the reference voltage Vref according to the first enable signal P_en, and outputs the first comparison result signal Pcmp_out accordingly. do.

The first register 30 counts and stores the first code according to the first comparison result signal Pcmp_out.

At this time, the ODT input driver 10 feeds back the first line voltage P_out according to the counted first code input to the first comparator 20, and accordingly, the first comparator 20 performs the above-described comparison operation and operation. Accordingly, the first comparison result signal Pcmp_out is outputted.

When the first comparison unit 20 outputs the first comparison result signal Pcmp_out corresponding to the matching of the first line voltage P_out and the reference voltage Vref, the count operation of the first register 30 is performed. The input impedance adjustment operation is completed by stopping and storing the corresponding first code.

In an initial operation, an initial second code preset in the second register 60 is input to the ODT output driver 40.

The ODT output driver 40 outputs a second line voltage N_out according to a resistance ratio of a resistor connected according to the first code and the second code.

Subsequently, the second comparator 50 compares the second line voltage N_out and the reference voltage Vref according to the second enable signal N_en, and outputs the second comparison result signal Ncmp_out accordingly. do.

The second register 60 counts and stores the second code according to the second comparison result signal Ncmp_out.

At this time, the ODT output driver 40 feeds back the second line voltage P_out according to the counted second code to the second comparator 50. Accordingly, the second comparator 50 performs the above-described comparison operation and The output operation of the second comparison result signal Ncmp_out is repeated.

When the second comparison unit 50 outputs the second comparison result signal Ncmp_out corresponding to the matching of the second line voltage N_out and the reference voltage Vref, the count operation of the second register 60 is performed. The output impedance adjusting operation is completed by stopping and storing the corresponding second code.

 According to the related art, when the first line voltage P_out and the second line voltage N_out are larger than the reference voltage Vref during the adjustment of the first code and the second code, the resistance value must be increased. The second code value is decreased.

At this time, when the line voltage is continuously higher than the reference voltage because the impedance outside the memory, i.e., the input / output terminal is very high, the first code is continuously increased, and the first code becomes the maximum value, and thus the resistance value becomes almost infinite. . Likewise, the second code continues to decrease so that at the end the second code is at its minimum and thus the resistance value is near infinity.

Therefore, the on-die termination device of the semiconductor memory according to the related art described above generates a code adjustment error in which the first code becomes the maximum value and the second code becomes the minimum value due to external impedance, and thus the resistance value approaches infinity. There is a problem that accurate data input and output is not made.

SUMMARY OF THE INVENTION The present invention has been made in view of the above-mentioned conventional problems, and an object thereof is to provide an apparatus and method for on-die termination of a semiconductor memory, which can prevent a code adjustment error.

An on-die termination device of a semiconductor memory according to the present invention comprises: on-die termination (ODT) input driving means for outputting a first line voltage by dividing an input voltage at a resistance ratio according to a first code including at least two bits; First ODT control means for counting or resetting the first code to a first set value according to whether the first line voltage and the reference voltage match each other; ODT output driving means for outputting a second line voltage by dividing an input voltage with a resistance ratio according to the first code and a second code having at least two bits; And second ODT control means for counting or resetting the second code to a second set value according to whether the second line voltage and the reference voltage match each other.

In the on-die termination method of a semiconductor memory according to the present invention, the on-die termination method of a semiconductor memory having an input driving means for determining the resistance ratio according to the first code, and an output driving means for determining the resistance ratio according to the second code, A first comparing step of comparing the first line voltage output from the input driving means with the reference voltage; Counting or resetting the first code to a first set value according to a comparison result of the first comparing step; A second comparing step of comparing a second line voltage output from the output driving means with a reference voltage; And counting or resetting the second code to a second set value according to the comparison result of the second comparison step.

Hereinafter, exemplary embodiments of the present invention will be described with reference to the accompanying drawings.

2 is a block diagram showing the configuration of the on-die termination device of the semiconductor memory according to the present invention, FIG. 3 is a circuit diagram showing the configuration of the ODT input driver of FIG. 2, FIG. 4 is a circuit diagram showing the configuration of the first control unit of FIG. 5 is a circuit diagram illustrating the configuration of the ODT output driver of FIG. 2, FIG. 6 is a circuit diagram illustrating the configuration of the second control unit of FIG. 2, and FIG. 7 is a timing diagram illustrating a signal waveform related to first code adjustment according to the present invention. 8 is a timing diagram illustrating a second code adjustment related signal waveform according to the present invention.

According to an embodiment of the on-die termination device of a semiconductor memory according to the present invention, as shown in FIG. 2, an ODT for dividing an input voltage with a resistance ratio according to a first code including at least two bits to output a first line voltage (On Die Termination) An input driver 100, a first ODT controller 200 for counting or resetting the first code to a first set value according to whether the first line voltage and the reference voltage match each other, and the first code. And an ODT output driver 300 for dividing an input voltage at a resistance ratio according to a second code including at least two bits to output a second line voltage, and according to whether the second line voltage matches a reference voltage. And a second ODT controller 400 for counting or resetting the code to a second set value.

The first ODT controller 200 compares the first line voltage P_out and the reference voltage Vref according to a first enable signal P_en to output a first comparison result signal Pcmp_out. A first register 220 for counting or resetting the first code to a first set value according to the first comparison result signal Pcmp_out and the reset signal reset, and the first enable signal; And a first controller 230 generating a reset signal according to P_en and the first code.

The second ODT control unit 400 compares the second line voltage N_out and the reference voltage Vref according to a second enable signal N_en to output a second comparison result signal Ncmp_out. A second register 420 for counting or resetting the second code to a second set value according to the second comparison result signal Ncmp_out and a reset signal, and the second enable signal; And a second control unit 430 for generating a reset signal according to N_en and the second code.

As shown in FIG. 3, the ODT input driver 100 is connected to a power supply terminal VDDQ and is turned on according to the first code, and the plurality of transistors P0 to Pn. It includes a plurality of resistors (NR0 ~ NRn) connected between each and the ground terminal (VSSQ).

The first controller 230 determines that the first code is the maximum value (for example, N = 4 in Pcode <0: N>) when the first enable signal P_en is disabled, that is, Pcode < When 0: N> is 5 bits, the reset signal is configured to be enabled when 11111 is reached, and as shown in FIG. 4, the first inverter receiving the first enable signal P_en (see FIG. 4). IV1) and a first XNOR gate XNOR1 receiving an output of the first inverter IV1 and the first code.

As shown in FIG. 5, the ODT output driver 400 is connected to a power supply terminal VDDQ and is turned on according to the first code, and the plurality of transistors P0 to Pn. A plurality of resistors NR0 to NRn connected between the ground terminal VSSQ, a plurality of resistors PR0 to PRn connected to the plurality of resistors NR0 to NRn, and the plurality of resistors PR0 to PRn, respectively. And a plurality of transistors N0 to Nn connected between the first and second ground terminals VSSQ and turned on according to the second code.

The second controller 430 determines that the second code is the minimum value (for example, N = 4 in Pcode <0: N>) when the second enable signal N_en is disabled, that is, Pcode <0. When: N> is 5 bits, 00000) is configured to enable the reset signal (reset), and as shown in FIG. 6, a second receiving the second enable signal (N_en) Inverter IV2, an inverter IV3 to IVn corresponding to the number of bits of the second code receiving each bit of the second code, and a second XNOR gate XNOR2 receiving the output of the inverters IV2 to IVn. It includes.

The first set value and the second set value are set through simulation or semiconductor memory operation test so that data input and output can be performed even when the impedance of the semiconductor input / output side is high.

An operation of the on-die termination apparatus of the semiconductor memory according to the present invention configured as described above will be described with reference to FIGS. 2 to 8.

First, referring to a first code adjustment related operation, an initial first code preset in the first register 220 is input to the ODT input driver 100 during an initial operation.

The ODT input driver 100 outputs a first line voltage P_out corresponding to a resistor connected according to the first code and a resistor ZQ for detecting line impedance.

Subsequently, the first comparator 210 compares the first line voltage P_out and the reference voltage Vref according to the first enable signal P_en, and outputs the first comparison result signal Pcmp_out accordingly. do. In this case, when the first line voltage P_out does not coincide with the reference voltage Vref, the first comparator 210 performs a first counting operation such that the first register 220 counts up. The comparison result signal Pcmp_out is output high.

The first register 220 up counts and stores the first code according to the first comparison result signal Pcmp_out as shown in FIG. 7.

At this time, the ODT input driver 100 feeds back the first line voltage P_out according to the up-counted first code to the first comparator 210, whereby the first comparator 210 performs the above-described comparison operation. And accordingly the first comparison result signal Pcmp_out output operation.

The first comparison unit 210 compares the first line voltage P_out with the reference voltage Vref during the enable period of the first enable signal P_en, that is, while the pulse is generated. When the result signal Pcmp_out is output low, the counting operation of the first register 220 is stopped, and a corresponding code value is stored, thereby completing the adjustment operation.

However, as shown in FIG. 7, even when the first code is up counted during the enable period of the first enable signal P_en, the first line voltage P_out and the reference voltage Vref do not coincide with each other. If the signal Pcmp_out remains high, the first code reaches the maximum value 11111 and the first enable signal P_en is disabled.

Accordingly, the first control unit 230 of FIG. 4 receives the first code reaching the maximum value 11111 and the first enable signal P_en disabled at a low level, thereby setting the reset signal high. Let it be.

Accordingly, the first register 220 resets and stores the first code to the first set value according to the reset signal.

Therefore, as the impedance of the semiconductor input / output side is very high, a code adjustment error in which the first code is stored at the maximum value is prevented.

Next, referring to a second code adjustment related operation, an initial first code preset in the second register 420 is input to the ODT output driver 300 during an initial operation.

The ODT output driver 300 outputs a second line voltage N_out corresponding to a resistor connected according to the second code.

Subsequently, the second comparator 410 compares the second line voltage N_out with the reference voltage Vref according to the second enable signal N_en, and outputs the second comparison result signal Ncmp_out accordingly. do. In this case, if the second line voltage N_out does not coincide with the reference voltage Vref, the second comparator 410 causes the second register 420 to count down as shown in FIG. 8. The comparison result signal Ncmp_out is output low.

The second register 420 down-counts and stores the second code according to the second comparison result signal Ncmp_out as shown in FIG. 8.

At this time, the ODT output driver 300 feeds back the second line voltage N_out according to the down-counted second code to the second comparator 410, and accordingly, the second comparator 410 performs the above-described comparison operation. And the second comparison result signal Ncmp_out is outputted accordingly.

A second comparison in which the second comparator 410 matches the second line voltage N_out and the reference voltage Vref during an enable period of the second enable signal N_en, that is, while a pulse is generated. When the result signal Ncmp_out is output high, the counting operation of the second register 420 is stopped, and the corresponding code value is stored, thereby completing the adjustment operation.

However, as shown in FIG. 8, even if the second code is continuously counted down during the enable period of the second enable signal N_en, the second line voltage N_out and the reference voltage Vref do not coincide with each other. When the result signal Ncmp_out remains low, the second code reaches the minimum value (00000), and the second enable signal N_en is disabled.

Accordingly, the second control unit 430 of FIG. 6 receives the second code reaching the minimum value (00000) and the second enable signal N_en disabled at a low level to enable the reset signal high. Let's do it.

Accordingly, the second register 420 resets and stores the second code to the second set value according to the reset signal.

Therefore, as the impedance of the semiconductor input / output side is very high, a code adjustment error in which the second code is stored at the minimum value is prevented.

In this case, the first set value related to the first code and the second set value related to the second code are set through simulation or semiconductor memory operation test so that data input and output can be performed even when the impedance of the semiconductor input / output side is high.

As those skilled in the art to which the present invention pertains may implement the present invention in other specific forms without changing the technical spirit or essential features, the embodiments described above should be understood as illustrative and not restrictive in all aspects. Should be. The scope of the present invention is shown by the following claims rather than the detailed description, and all changes or modifications derived from the meaning and scope of the claims and their equivalents should be construed as being included in the scope of the present invention. do.

The apparatus and method for on-die termination of a semiconductor memory according to the present invention can prevent a code value adjustment error so that data input and data output can be normally performed, thereby improving memory operation reliability.

Claims (22)

On Die Termination (ODT) input driving means for outputting a first line voltage by dividing an input voltage with a resistance ratio according to a first code comprising at least two bits; First ODT control means for counting or resetting the first code to a first set value according to whether the first line voltage and the reference voltage match each other; ODT output driving means for outputting a second line voltage by dividing an input voltage with a resistance ratio according to the first code and a second code having at least two bits; And And second ODT control means for counting or resetting the second code to a second set value according to whether the second line voltage and the reference voltage match each other. The method of claim 1, The ODT input driving means includes a plurality of switching elements connected to a power terminal and turned on according to the first code, and a plurality of resistors connected between each of the plurality of switching elements and a ground terminal VSSQ. On-die termination device of semiconductor memory On-die termination device of semiconductor memory. The method of claim 1, The first ODT control means A comparator for comparing the first line voltage with a reference voltage according to a first enable signal and outputting a first comparison result signal; A register for counting or resetting the first code to a first set value according to the first comparison result signal and a reset signal; And a controller configured to generate a reset signal according to the first enable signal and the first code. The method of claim 3, wherein And the comparator is configured to output a first comparison result signal to cause the first register to count up if the first line voltage does not match the reference voltage. The method of claim 3, wherein And the control unit is configured to enable the reset signal when the first code reaches a maximum value in a state where the first enable signal is disabled. The method of claim 3, wherein The controller receives the first enable signal, and an inverter; And an XNOR gate configured to receive the output of the inverter and the first code. The method according to claim 5 or 6, And the first enable signal is a pulse signal. The method of claim 1, The ODT output driving means A first transistor group composed of a plurality of transistors connected to a power supply terminal and turned on according to the second code, a first resistor group consisting of a plurality of resistors connected between each transistor of the first transistor group and a ground terminal, the first resistor group A second resistor group consisting of a plurality of resistors connected to each of the resistors of the resistor group, and a second transistor group consisting of a plurality of transistors connected between each of the resistors of the second resistor group and a ground terminal and turned on according to the second code On die termination device of a semiconductor memory comprising a. The method of claim 1, The second ODT control means A comparator for comparing the second line voltage with a reference voltage according to a second enable signal and outputting a second comparison result signal; A register for counting or resetting the second code to a second set value according to the second comparison result signal and the reset signal; And a controller configured to generate a reset signal according to the second enable signal and the second code. The method of claim 9, And the comparator is configured to output a second comparison result signal so that the register counts down when the second line voltage does not match the reference voltage. The method of claim 9, And the control unit is configured to enable the reset signal when the second code reaches a minimum value when the second enable signal is disabled. The method of claim 9, The control unit is a first inverter for receiving the second enable signal, A second inverter equal to the number of bits of the second code receiving each bit of the second code, and And an XNOR gate for receiving outputs of the first and second inverters. The method according to claim 11 or 12, And the second enable signal is a pulse signal. The method of claim 1, And the first and second set values are set through simulation or semiconductor memory operation test. An on-die termination method of a semiconductor memory having an input driving means having a resistance ratio determined according to a first code and an output driving means having a resistance ratio determined according to a second code, A first comparing step of comparing a first line voltage output from the input driving means with a reference voltage; Counting or resetting the first code to a first set value according to a comparison result of the first comparing step; A second comparing step of comparing a second line voltage output from the output driving means with a reference voltage; And Counting or resetting the second code to a second set value according to a comparison result of the second comparing step. The method of claim 15, Counting the first code according to the comparison result of the first comparison step And counting the code if the first line voltage and the reference voltage do not coincide with each other during the enable period of the first enable signal. The method of claim 15, Resetting the first code to the first set value according to the comparison result of the first comparison step And resetting the first code to a first set value when the first code reaches a maximum value when the first enable signal is disabled. The method according to claim 16 or 17, And the first enable signal is a pulse signal. The method of claim 15, Counting the second code according to the comparison result of the second comparison step And counting the code if the second line voltage and the reference voltage do not coincide during the enable period of the second enable signal. The method of claim 15, Resetting the second code to the second set value according to the comparison result of the second comparison step And resetting the second code to a second set value when the second code reaches a minimum value when the second enable signal is disabled. The method of claim 19 or 20, And the second enable signal is a pulse signal. The method of claim 15, And the first and second set values are set by simulation or semiconductor memory operation test.

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