KR20190075788A - Storage device including calibration device - Google Patents

Abstract

Provided is a calibration device, which includes a first comparator, a second comparator, and a control signal generator. The first comparator outputs a first comparison result comparing a level of a first voltage of a first node with a level of a reference voltage. The second comparator outputs a second comparison result comparing the level of the first voltage with a level of a second voltage of a second node. The control signal generator outputs a first control signal for adjusting a first resistance value of a first resistance circuit based on the first comparison result and outputs a second control signal for adjusting a second resistance value of a second resistance circuit based on the second comparison result. The first node is positioned between the first resistance circuit and reference resistance. The second node is positioned between a third resistance circuit adjusted to have a resistance value equal to the first resistance value and the second resistance circuit.

Description

[0001] STORAGE DEVICE INCLUDING CALIBRATION DEVICE [0002]

To an electronic device, and more particularly to a storage device.

As the interface operation of the semiconductor memory device becomes faster, the swing width of signals transmitted between the memory device and the memory controller is gradually reduced. The smaller the swing width of the signal, the larger the influence of the external noise can be. Accordingly, high-speed transfer of signals between the memory device and the memory controller may be difficult, and data output from the semiconductor memory device may be damaged.

Therefore, in the semiconductor memory device, there may be a pull-up resistor and a pull-down resistor for accurately adjusting the level of the signal used for the interface operation.

However, the values of the pull-up and pull-down resistors can vary depending on the PVT (Process, Voltage, Temperature) conditions. The semiconductor memory device may perform a calibration operation to maintain the values of the pull-up and pull-down resistors at a constant value.

A storage device including an apparatus for calibrating a pull-down resistor and a pull-up resistor may be provided.

The calibration apparatus according to an embodiment of the present invention may include a first comparator, a second comparator, and a control signal generator. The first comparator may output a first comparison result comparing the level of the first voltage of the first node with the level of the reference voltage. The second comparator may output a second comparison result of comparing the level of the first voltage and the level of the second voltage of the second node. The control signal generator outputs a first control signal for adjusting the first resistance value of the first resistance circuit based on the first comparison result and controls the second resistance value of the second resistance circuit based on the second comparison result The second control signal can be output. The first node may be located between the first resistor circuit and the reference resistor. The second node may be located between the third resistor circuit and the second resistor circuit that is adjusted to have the same resistance value as the first resistor value.

The calibration apparatus according to an exemplary embodiment of the present invention may include a first operational amplifier and a second operational amplifier. The first operational amplifier may output a first control signal for adjusting the first resistance value of the first resistance circuit by comparing the level of the first voltage of the first node with the level of the reference voltage. The second operational amplifier may output a second control signal for adjusting the second resistance value of the second resistance circuit by comparing the level of the first voltage and the level of the second voltage of the second node. The first node may be located between the first resistor circuit and the reference resistor. The second node may be located between the third resistor circuit and the second resistor circuit that is adjusted to have the same resistance value as the first resistor value.

A storage device according to an embodiment of the present invention may include a memory device and a controller. The controller adjusts the first resistance value of the first resistance circuit based on the first comparison result obtained by comparing the level of the first voltage with the level of the first reference voltage and compares the level of the first voltage with the level of the second voltage And perform a calibration operation for adjusting the second resistance value of the second resistance circuit based on the second comparison result. The level of the first voltage is determined based on the first resistance value and the first reference resistance value, and the level of the second voltage can be determined based on the first resistance value and the second resistance value.

According to an embodiment of the present invention, a pull-down calibration operation and a pull-up calibration operation can be performed in parallel or simultaneously. Thus, the total time taken to perform the calibration operation including the pull-down calibration operation and the pull-up calibration operation can be reduced.

In addition, since the resistance values of the pull-down circuit and the pull-up circuit are simultaneously adjusted, the influence of the pull-down circuit and the pull-up circuit resistance value on the PVT variation can be reduced. Thus, the performance of the storage apparatus can be improved.

1 is a block diagram illustrating a storage device according to one embodiment.
2 is a conceptual diagram illustrating a transmitter and a receiver that perform an interface operation based on a voltage signal in accordance with one embodiment.
3 is a block diagram illustrating a calibration apparatus in accordance with one embodiment.
4 is a block diagram illustrating a calibration apparatus in accordance with one embodiment.
5 is a flow chart showing how the calibration apparatus of FIG. 4 performs a calibration operation.
Fig. 6 is a circuit diagram showing an exemplary configuration of the calibration apparatus of Fig. 4; Fig.
Fig. 7 is a circuit diagram showing an exemplary configuration of the calibration apparatus of Fig. 4; Fig.
8 is a circuit diagram illustrating a calibration apparatus according to one embodiment.
9 is a graph showing current-voltage characteristics of a transistor according to an embodiment.
10 is a block diagram illustrating a calibration apparatus in accordance with one embodiment.
11 is a flow chart showing how the calibration apparatus of FIG. 10 performs a calibration operation.
12 is a circuit diagram showing an exemplary configuration of the calibration apparatus of FIG.
Fig. 13 is a circuit diagram showing an exemplary configuration of the calibration apparatus of Fig. 10; Fig.
14 is a circuit diagram showing a calibration apparatus according to one embodiment.
15 is a block diagram showing a configuration of an electronic system according to an embodiment.

In the following, embodiments of the present invention will be described in detail and in detail so that those skilled in the art can easily carry out the present invention.

1 is a block diagram illustrating a storage device according to one embodiment.

The storage apparatus 1000 stores data and manages the stored data to provide information necessary for a user. According to one embodiment, the storage device 1000 may be a personal computer (PC) or a mobile electronic device such as a notebook computer, a cell phone, a PDA (Personal Digital Assistant), or a camera, but is not limited thereto.

Storage device 1000 may include a controller 1200 and a memory device 1400.

The controller 1200 may control the overall operations of the storage device 1000. As an example, the controller 1200 may schedule operations of the memory device 1400, or may encode and decode signals / data processed in the storage device 1000. The controller 1200 may control the memory device 1400 to allow the memory device 1400 to store or output data. As an example, the controller 1200 may perform an interface operation with the memory device 1400 in response to a command received from a host (not shown).

The controller 1200 may be coupled to the memory device 1400 via a plurality of channels. The controller 1200 may include a hardware or software device (not shown) for performing operations in response to various requests from a host (not shown). The controller 1200 according to an exemplary embodiment may include a volatile memory such as a dynamic random access memory (DRAM), a static random access memory (SRAM), or a synchronous DRAM (SDRAM).

Controller 1200 may include one or more hardware components (e.g., analog circuitry, logic circuitry, etc.) configured to perform the functions described above and described below. Additionally or alternatively, controller 1200 may include one or more processor cores. The functions of the controller 1200 described above and described below may be implemented in software code in the form of software and / or firmware, and the processor core (s) in the controller 1200 may execute a set of instructions in the program code. The processor core (s) of the controller 1200 may process various kinds of arithmetic and / or logic operations to execute a set of instructions.

The memory device 1400 may include at least one non-volatile memory. By way of example, the memory device 1400 may include a plurality of flash memories. By way of example, memory device 1400 may include other types of non-volatile memory such as PRAM, FRAM, and MRAM. The memory device 1400 may store one bit of data or two or more bits of data per memory cell. The non-volatile memory constituting the memory device 1400 may also include a memory cell array of a three-dimensional structure.

The interface operation between the controller 1200 and the memory device 1400 may be performed based on a digital signal or an analog signal. The controller 1200 may include a driver for interfacing with the memory device 1400. The memory device 1400 may include a driver for interfacing with the controller 1200.

By way of example, the controller 1200 may send a digital signal to the memory device 1400 and the memory device 1400 may return a response to the received digital signal to the controller 1200.

By way of example, controller 1200 may transmit an analog signal to memory device 1400 and memory device 1400 may return a response to controller 1200 to the received analog signal. According to one embodiment, the analog signal may be a voltage signal.

When the interface operation between the controller 1200 and the memory device 1400 is performed based on the voltage signal, the level of the voltage signal needs to be maintained at a specific value. If the level of the voltage signal is not correct or easily changed, the speed of the interface operation may decrease, or the data output from the storage apparatus 1000 or input to the storage apparatus 1000 may be damaged.

Each of the controller 1200 and the memory device 1400 may include a resistance portion 1220 and a resistance portion 1420, respectively. The resistor portion 1220 and the resistor portion 1420 can be used to adjust the level of the voltage signal transmitted and received between the controller 1200 and the memory device 1400. [ By way of example, the level of the voltage signal for interface operation may be defined by the standard specification of the storage device 1000, but is not limited thereto.

The resistor portion 1220 of the controller 1200 may include a pull-up circuit 1222 and a pull-down circuit 1224. The resistive portion 1420 of the memory device 1400 may include a pull-up circuit 1422 and a pull-down circuit 1424. The pull-up circuit 1222, the pull-down circuit 1224, the pull-up circuit 1422, and the pull-down circuit 1424, respectively, may include circuitry. As an example, each of the pull-up circuit 1222, the pull-down circuit 1224, the pull-up circuit 1422, and the pull-down circuit 1424 may each comprise a single resistor. Alternatively, the pull-up circuit 1222, the pull-down circuit 1224, the pull-up circuit 1422, and the pull-down circuit 1424, respectively, may include transistors coupled in parallel. Alternatively, each of the pull-up circuit 1222, the pull-down circuit 1224, the pull-up circuit 1422 and the pull-down circuit 1424 may comprise a single resistor with the transistors connected in parallel . However, the circuitry included in each of the pull-up circuit 1222, the pull-down circuit 1224, the pull-up circuit 1422, and the pull-down circuit 1424 can include any device or component, It is not limited.

The resistance value of each of the pull-up circuit 1222, the pull-down circuit 1224, the pull-up circuit 1422 and the pull-down circuit 1424 is controlled by the pull-up circuit 1222, Down circuit 1424, the pull-up circuit 1422, the pull-down circuit 1424, or the impedance value of the entire AC circuit.

According to one embodiment, when controller 1200 transmits a voltage signal to memory device 1400, the level of the voltage signal is controlled by the resistance value of pull-up circuit 1222 and pull-down circuit 1424 . According to one embodiment, when transmitting a voltage signal from the memory device 1400 to the controller 1200, the level of the voltage signal is controlled by the resistance value of the pull-up circuit 1422 and pull-down circuit 1224 .

The resistance values of the pull-up circuit 1222, the pull-down circuit 1224, the pull-up circuit 1422 and the pull-down circuit 1424 can be changed according to the PVT (Process, Voltage, and Temperature) have. In this case, the level of the voltage signal used for the interface operation between the controller 1200 and the memory device 1400 can not be accurately adjusted.

To adjust the level of the voltage signal, the controller 1200 and the memory device 1400 may include a calibration device 1240 and a calibration device 1440, respectively. The controller 1200 may include a calibration device 1240 for performing a calibration operation that adjusts the resistance values of the pull-up circuit 1222 and the pull-down circuit 1224. The memory device 1400 may include a calibration device 1440 for performing a calibration operation that adjusts the resistance values of the pull-up circuit 1422 and the pull-down circuit 1424. The calibration device 1240 and the calibration device 1440 may perform a calibration operation using a reference resistor 1600 connected to the storage device 1000. [ According to one embodiment, the storage device 1000 may include a terminal for connection with the reference resistor 1600. The terminal may be in the form of a pin, a pad, but is not limited thereto.

2 is a conceptual diagram illustrating a transmitter and a receiver that perform an interface operation based on a voltage signal in accordance with one embodiment.

Referring to Figure 1, when controller 1200 transmits a voltage signal to memory device 1400, transmitter 2200 and receiver 2400 may represent controller 1200 and memory device 1400, respectively. The transmitter 2200 and the receiver 2400 may represent the memory device 1400 and the controller 1200 respectively when the memory device 1400 transmits the voltage signal to the controller 1200. [

The transmitter 2200 may output the voltage signal V _OH to the receiver 2400. V _OH according to one embodiment may be supplied from the supply voltage. The power supply voltage may be a power supply voltage (VDD / VSS) or a power supply voltage (VDDQ / VSSQ) supplied from an external device of the storage apparatus 1000. The transmitter 2200 and the receiver 2400 can perform the calibration operation using the power supply voltage VDD / VSS or the power supply voltage VDDQ / VSSQ. The power supply voltage VDD / VSS may be a power supply voltage for operating the components 1200 and 1400 of the storage apparatus 1000. The power supply voltage VDDQ / VSSQ may be a power supply voltage for the components 1200 and 1400 of the storage apparatus 1000 to output data. The levels of the power supply voltages VDD and VDDQ may be higher than the levels of the power supply voltages VSS and VSSQ, respectively. However, the power supply voltage supplied to the present invention may not be limited thereto. In the following description, VDD and VSS may be replaced by VDDQ and VSSQ, respectively.

When the transmitter 2200 outputs a voltage signal V _OH to the receiver 2400, the level of V _OH may be determined according to the resistance value of the pull-up circuit 2220 and the resistance value of the pull-down circuit 2420 have. As an example, V _OH can be determined according to Equation (1).

(R _{pull- up} : resistance value of the pull-up circuit 2220, R _{pull- down} : resistance value of pull-down circuit 2420)

Each of the pull-up circuit 2220 and the pull-down circuit 2420 according to an embodiment may include at least one transistor. As an example, each of the pull-up circuit 2220 and the pull-down circuit 2420 may include transistors connected in parallel. Alternatively, the pull-up circuit 2220 and the pull-down circuit 2420, respectively, may include additional resistors in addition to the transistors, but are not limited thereto.

Through the calibration operation according to the embodiment of the present invention, the level of the voltage signal V _OH can be accurately adjusted. Calibration operations according to an embodiment of the present invention will be described with reference to Figs. 3 to 14. Fig.

3 is a block diagram illustrating a calibration apparatus in accordance with one embodiment.

Calibration device 3000 may represent one of calibration device 1240 and calibration device 1440 of FIG. Calibration apparatus 3000 may include a reference voltage generator 3200, a first comparator 3600, a second comparator 3700, and a control signal generator 3800. Calibration apparatus 3000 may perform a calibration operation to adjust the resistance values of first pull-down circuit 3300, second pull-down circuit 3400, and pull-up circuit 3500.

The second pull-down circuit 3400 may include the same circuitry as the circuitry included in the first pull-down circuit 3300 and may have the same logic value as the control signal received by the first pull-down circuit 3300 Lt; / RTI > Thus, the second pull-down circuit 3400 can be adjusted to have the same resistance value as that of the first pull-down circuit 3300. The first pull-down circuit 3300 and the second pull-down circuit 3400 may be included in the pull-down circuit 1224 of FIG. Alternatively, the first pull-down circuit 3300 and the second pull-down circuit 3400 may be included in the pull-down circuit 1424 of FIG. The second pull-down circuit 3400 may be used for the calibration operation of the pull-up circuit 3500. This will be described later.

The pull-up circuit 3500 may be included in the pull-up circuit 1222 or pull-up circuit 1422 of FIG.

The reference resistor 3100 may be used to adjust the resistance values of the first pull-down circuit 3300, the second pull-down circuit 3400, and the pull-up circuit 3500. The reference resistor 3100 may correspond to the reference resistor 1600 of FIG.

The reference voltage generator 3200 can output the reference voltage V _REF used for the calibration operation. For example, the level of the reference voltage V _REF output from the reference voltage generator 3200 may be half the level of the power source voltage V _DD .

First, the first comparator 3600 compares the level of the reference voltage V _REF output from the reference voltage generator 3200 with the level of the PD_CAL_VOL output from the node 3150. The pull- And outputs the first comparison result to the control signal generator 3800. [ The first comparator 3600 according to one embodiment may be implemented with an operational amplifier, but is not limited thereto.

PD_CAL_VOL may be the voltage at node 3150 located between reference resistor 3100 and first pull-down circuit 3300. PD_CAL_VOL may be supplied from the power supply voltage VDD and the level of PD_CAL_VOL may be determined based on the value of the reference resistor 3100 and the resistance value of the first pull-down circuit 3300. As an example, PD_CAL_VOL can be determined according to [Equation 2].

(R _{pull- down_1} : resistance value of first pull-down circuit 3300, R _REF : value of reference resistance 3100)

Therefore, by changing the resistance value of the first pull-down circuit 3300, PD_CAL_VOL can also be changed.

The first comparison result may include information on whether the level of PD_CAL_VOL is equal to the level of the reference voltage V _REF . In addition, the first comparison result may include a reference level, and if the different levels of voltage (V _REF), information as to whether higher or lower than the level of the level of PD_CAL_VOL reference voltage (V _REF) of PD_CAL_VOL. According to one embodiment, the first comparison result may comprise a bit value. For example, if the level of the PD_CAL_VOL is equal to the level of the reference voltage V _REF , the bit value '1' is output to the control signal generator 3800. Otherwise, the bit value '0' is output to the control signal generator 3800 can do.

The control signal generator 3800 outputs a control signal PD_CODE for adjusting the resistance value of the first pull-down circuit 3300 to the first pull-down circuit 3300 based on the received first comparison result can do. The control signal generator 3800 in accordance with one embodiment may be an ASIC, an embedded processor, a microprocessor, hardware control logic, a hardware finite state machine (FSM), or a combination thereof. The operation in which the resistance value of the first pull-down circuit 3300 is adjusted based on the control signal PD_CODE will be described in detail with reference to FIG.

The level of PD_CAL_VOL can be changed as the resistance value of the first pull-down circuit 3300 is adjusted, and the PD_CAL_VOL having the changed level and the reference voltage _VREF can be input again to the first comparator 3600 . The first comparator 3600 may compare the changed level of PD_CAL_VOL with the level of the reference voltage V _REF and output the first comparison result to the control signal generator 3800.

The above operation can be repeated until the level of the PD_CAL_VOL becomes equal to the level of the reference voltage V _REF . For example, if the first comparison result received by control signal generator 3800 indicates that the level of PD_CAL_VOL is equal to the level of reference voltage V _REF , then control signal generator 3800 includes first pull-down circuit 3300 It is possible to stop outputting the control signal PD_CODE. According to one embodiment, the control signal generator 3800 determines that the calibration for the first pull-down circuit 3300 has been completed and sends a control signal to the first comparator 3600 ).

According to one embodiment, if the level of the reference voltage V _REF is set at half the level of the power supply voltage V _DD , then the first pull-down circuit 3300, Down circuit 3300 may be equal to the value of the reference resistor 3100. [

The control signal generator 3800 may also output the control signal PD_CODE to the second pull-down circuit 3400. [ The second pull-down circuit 3400 receiving the control signal PD_CODE may be calibrated to have the same resistance value as that of the first pull-down circuit 3300. The second pull-down circuit 3400 that has been calibrated may be used for a pull-up calibration operation to adjust the resistance value of the pull-up circuit 3500.

The second comparator 3700 first compares the level of the reference voltage V _REF output from the reference voltage generator 3200 with the level of the PU_CAL_VOL output from the node 3550, The second comparison result can be outputted. The second comparator 3700 according to one embodiment may be implemented with an operational amplifier, but is not limited thereto.

PU_CAL_VOL is the voltage at node 3550 located between pull-up circuit 3500 and second pull-down circuit 3400. PU_CAL_VOL may be supplied from the power supply voltage VDD and the level of PU_CAL_VOL may be determined based on the resistance value of the pull-up circuit 3500 and the resistance value of the second pull-down circuit 3400. As an example, the level of PU_CAL_VOL may be determined according to [Equation 3].

(R _{pull- down_2} : the resistance value of the second pull-down circuit 3400 that has been calibrated, R _pull-up : The resistance value of the pull-up circuit 3500)

Therefore, by changing the resistance value of the pull-up circuit 3500, PU_CAL_VOL can also be changed.

The control signal generator 3800 may output the control signal PU_CODE to the pull-up circuit 3500 based on the second comparison result received from the second comparator 3700. The resistance value of the pull-up circuit 3500 can be adjusted by the control signal PU_CODE received from the control signal generator 3800. As the resistance value of the pull-up circuit 3500 is adjusted, the level of the PU_CAL_VOL can be changed, and the PU_CAL_VOL having the changed level and the reference voltage V _REF can be inputted again to the second comparator 3700. The second comparator 3700 may compare the changed level of the PU_CAL_VOL with the level of the reference voltage V _REF and output the second comparison result to the control signal generator 3800.

The above operation can be repeated until the level of PU_CAL_VOL and the reference voltage V _REF become equal in level. For example, if the second comparison result received by the control signal generator 3800 indicates that the level of the PU_CAL_VOL is equal to the level of the reference voltage V _REF , the control signal generator 3800 controls the pull-up circuit 3500, It is possible to stop outputting the control signal PU_CODE. According to one embodiment, the control signal generator 3800 determines that the calibration for the pull-up circuit 3500 is complete and sends a control signal to the second comparator 3700 indicating that it is no longer necessary to perform the comparison Can be output.

According to one embodiment, if the level of the reference voltage V _REF is set at half the level of the power supply voltage V _DD , the pull-up circuit 3500 at the time the calibration for the pull- 3500 may be equal to the resistance value of the second pull-down circuit 3400.

According to an embodiment of the present invention described with reference to Figure 3, the calibration apparatus 3000 includes a first pull-down circuit 3300 and a second pull-down circuit 3400. After the calibration operation for the first pull-down circuit 3300 and the second pull- The pull-down circuit 3400 may be used to initiate the calibration operation for the pull-up circuit 3500. [ Thus, the total time for completing the pull-down calibration operation and the pull-up calibration operation may be the sum of the time taken for the pull-down calibration operation and the time taken for the pull-up calibration operation. In addition, since the resistance value of the pull-up circuit 3500 is adjusted based on the resistance value of the second pull-down circuit 3400, if the resistance value of the second pull-down circuit 3400 is not accurately adjusted , The resistance value of the pull-up circuit 3500 may not be precisely adjusted.

3, when the reference resistor 3100 is located between the node 3150 and the node to which the power supply voltage VDD is supplied, the first pull-down circuit 3300, the second pull- Up circuit 3500 are connected between the node 3150 and the node to which the power supply voltage VSS is supplied, the node 3550 and the node to which the power supply voltage VSS is supplied, the node 3550, And may be located between the nodes to which the power supply voltage VDD is supplied. The calibration operation performed when the reference resistor 3100 is located between the node 3150 and the node to which the power supply voltage VDD is supplied will be described in detail with reference to FIGS. The node supplying the power supply voltage VSS to the first pull-down circuit 3300 may be the same as or different from the node supplying the power supply voltage VSS to the second pull-down circuit 3400. [ The node that supplies the power supply voltage VDD to the reference resistor 3100 may be the same as or different from the node that supplies the power supply voltage VDD to the pull-up circuit 3500.

4 is a block diagram illustrating a calibration apparatus in accordance with one embodiment.

The components shown in FIG. 4 may provide the components and corresponding operations shown in FIG. Therefore, redundant descriptions will be omitted.

The calibration device 4000 of FIG. 4 is different from the calibration device 3000 of FIG. 3 in that the second comparator 3700 receives PD_CAL_VOL and PU_CAL_VOL instead of receiving the reference voltage V _REF and PU_CAL_VOL. Accordingly, the calibration apparatus 4000 may perform the pull-down calibration operation and the pull-up calibration operation in parallel or concurrently. Thus, the total time taken to perform the calibration operation can be reduced.

More specifically, as described above with reference to FIG. 3, PD_CAL_VOL is determined according to Equation (2), and PU_CAL_VOL is determined according to Equation (3). Since the resistance values of the first pull-down circuit 3300 and the second pull-down circuit 3400 are the same, the value of R _{pull-down_1} in Equation (2) The value of R _{pull- down_2} in Equation (3) is the same. Therefore, whether or not PD_CAL_VOL and PU_CAL_VOL input to the second comparator 3700 are the same can be determined by comparing the resistance value of the pull-up circuit 3500 (R _{pull -up in} [Equation 3]) with that of the reference resistor 3100 Value (R _{REF in} [Equation 2]) is the same. That is, since the pull-up calibration operation is not performed depending on the resistance value of the second pull-down circuit 3400, the pull-up calibration operation need not be performed after the pull-down calibration operation is completed.

The second comparator 3700 outputs a comparison result of comparing the level of the PD_CAL_VOL with the level of the PU_CAL_VOL to the control signal generator 3800. The control signal generator 3800 generates the comparison result based on the comparison result received from the second comparator 3700 Up circuit 3500 to output the control signal PU_CODE. Control signal generator 3800 indicates that the level of PU_CAL_VOL is equal to the level of reference voltage V _REF when the comparison result received by control signal generator 3800 indicates that control signal PU_CODE Can be stopped. According to one embodiment, the control signal generator 3800 determines that the calibration for the pull-up circuit 3500 is complete and sends a control signal to the second comparator 3700 indicating that it is no longer necessary to perform the comparison Can be output. The resistance value of the pull-up circuit 3500 at the time when calibration for the pull-up circuit 3500 is completed may be the same as the value of the reference resistor 3100.

The calibration device 4000 according to one embodiment may perform a calibration operation including a full-up calibration operation and a full-up calibration operation based on a constant time period. As an example, the calibration device 4000 may perform a calibration operation in response to a calibration enable signal periodically received from the storage device 1000 of FIG. As an example, the calibration apparatus 4000 may perform the calibration operation at time T1 and again perform the calibration operation at time T2. According to one embodiment, the calibration device 4000 may begin a new calibration operation based on the state of the pull-down circuit 3300 or the pull-up circuit 3500 at the time the previous calibration operation is completed, It does not.

5 is a flow chart showing how the calibration apparatus of FIG. 4 performs a calibration operation.

In S5100 operation, the first comparator 3600 may receive PD_CAL_VOL and a reference voltage (V _REF ).

In S5200 operation, the first comparator 3600 may compare the level of the PD_CAL_VOL with the level of the reference voltage (V _REF ).

When the level of the PD_CAL_VOL is different from the level of the reference voltage V _REF , in S5300 operation, the control signal generator 3800 can adjust the resistance value of the first pull-down circuit 3300. As the resistance value of the first pull-down circuit 3300 is adjusted, the level of PD_CAL_VOL is changed and the changed level of PD_CAL_VOL can again be compared with the level of the reference voltage (V _REF ) in S5100 operation.

If the resistance value of the first pull-down circuit 3300 is equal to the value of the reference resistor 3100, the level of PD_CAL_VOL may be equal to the level of the reference voltage V _REF . If the level of PD_CAL_VOL is equal to the level of the reference voltage V _REF , the pull-down calibration operation can be terminated.

In operation S5400, the second comparator 3700 may receive PD_CAL_VOL and PU_CAL_VOL. PU_CAL_VOL may be supplied from the power supply voltage VDD and the level of PU_CAL_VOL may be determined based on the resistance value of the pull-up circuit 3500 and the resistance value of the second pull-down circuit 3400.

In the S5500 operation, the second comparator 3700 may compare the level of PD_CAL_VOL with the level of PU_CAL_VOL.

If the level of PD_CAL_VOL is different from the level of PU_CAL_VOL, in S5600 operation, control signal generator 3800 may adjust the resistance value of pull-up circuit 3500. As the resistance value of the pull-up circuit 3500 is adjusted, the level of PU_CAL_VOL is changed, and the changed level of PU_CAL_VOL can again be compared with the level of PD_CAL_VOL in S5400 operation.

If the resistance value of the pull-up circuit 3500 is equal to the resistance value of the second pull-down circuit 3400, the level of the PD_CAL_VOL and the level of the PU_CAL_VOL may be the same. If the level of PD_CAL_VOL and the level of PU_CAL_VOL are the same, the pull-up calibration operation can be terminated. That is, when the resistance value of the pull-up circuit 3500 and the pull-down circuit 3300, 3400 is equal to the value of the reference resistor 3100, the calibration operation including the pull-down calibration and the pull-up calibration ends .

The pull-up calibration operation performed by repeating the operations of S5100, S5200, and S5300 and the pull-up calibration operation performed by repeating the operations of S5400, S5500, and S5600 are performed independently of each other. Therefore, according to the embodiment of the present invention, the time taken for the calibration operation can be shortened as compared with the case where the pull-up calibration operation is performed after the pull-down calibration operation is completed.

Fig. 6 is a circuit diagram showing an exemplary configuration of the calibration apparatus of Fig. 4; Fig.

The components shown in FIG. 6 may provide the components and corresponding operations shown in FIG. Therefore, redundant explanations will be omitted below.

The calibration device 6000 uses the reference resistance 3100 connected through the pads to measure the resistance values of the first pull-down circuit 3300a, the second pull-down circuit 3400a, and the pull-up circuit 3500a A calibration operation can be performed.

Each of the first pull-down circuit 3300a and the second pull-down circuit 3400a may include N (N is a positive integer) transistors connected in parallel and a single resistor. In addition, the pull-up circuit 3500a may include M (M is a positive integer) transistors connected in parallel and a single resistor.

When the reference resistor 3100 is located between the node 3150 and the node to which the power supply voltage VDD is supplied, the first pull-down circuit 3300a and the N pull-down circuits 3400a included in the second pull- Each of the transistors may be an NMOS transistor. In this case, the source terminal of the NMOS transistor may be connected to the node to which the power supply voltage VSS is supplied. In addition, each of the M transistors included in the pull-up circuit 3500a may be a PMOS transistor. In this case, the drain terminal of the PMOS transistor may be connected to the node to which the power supply voltage VDD is supplied.

The first comparator 3600 may compare the level of the reference voltage V _{REF with} the level of the PD_CAL_VOL and output the first comparison result to the control signal generator 3800.

Based on the received first comparison result, the control signal generator 3800 provides control signal generator 3800 with the transistors included in the first pull-down circuit 3300a and the second pull-down circuit 3400a, respectively A control signal PD_CODE [(N-1): 0] that can be turned on or off can be output. The resistance value of the first pull-down circuit 3300a can be adjusted according to the number of turned-on transistors among the transistors connected in parallel. By way of example, the greater the number of turned-on transistors, the lower the resistance value of the first pull-down circuit 3300.

According to one embodiment, the control signal PD_CODE [(N-1): 0] may be a bit string composed of N bit values. N may represent the number of transistors included in the first pull-down circuit 3300a. For example, if the first pull-down circuit 3300a includes three transistors connected in parallel, the control signal generator 3800 generates a control signal PD_CODE [2: 0] containing bit string " 101 & Can be output. When the first pull-down circuit 3300a includes NMOS transistors, the first transistor and the third transistor of the first pull-down circuit 3300a receiving the control signal PD_CODE [2: 0] And the second transistor can be turned off.

The second comparator 3700 may compare the level of PD_CAL_VOL with the level of PU_CAL_VOL and output the second comparison result to the control signal generator 3800. The control signal generator 3800 generates a control signal PU_CODE [(M-1) ", which can turn on or off each of the transistors included in the pull-up circuit 3500a, based on the received second comparison result ): 0] to the pull-up circuit 3500a. The control signal PU_CODE [(M-1): 0] may be a bit string composed of M bit values. For example, when the pull-up circuit 3500a includes three transistors connected in parallel, the control signal generator 3800 outputs a control signal PU_CODE [2: 0] containing bit string " 101 & . When the pull-up circuit 3500a includes PMOS transistors, the first transistor and the third transistor of the pull-up circuit 3500 which have received the control signal PU_CODE [2: 0] are turned off and the second The transistor can be turned on.

The control signal generator 3800 may output the control signal PD_CAL_DONE to the first comparator 3600 when the pull-down calibration operation is completed. The first comparator 3600 receiving the control signal PD_CAL_DONE from the control signal generator 3800 may stop comparing the reference voltage V _REF with PD_CAL_VOL.

The control signal generator 3800 may output the control signal PU_CAL_DONE to the second comparator 3700 when the pull-up calibration operation is completed. The second comparator 3700 receiving the control signal PU_CAL_DONE from the control signal generator 3800 may stop the comparison of PD_CAL_VOL and PU_CAL_VOL.

Fig. 7 is a circuit diagram showing an exemplary configuration of the calibration apparatus of Fig. 4; Fig.

The components shown in Fig. 7 can provide the components and corresponding operations shown in Fig.

The first pull-down circuit 3300b and the second pull-down circuit 3400b of FIG. 7 differ from the first pull-down circuit 3300a and the second pull-down circuit 3400a of FIG. The first pull-down circuit 3300b and the second pull-down circuit 3400b do not include a resistor. That is, the first pull-down circuit 3300b and the second pull-down circuit 3400b may include only N (N is a positive integer) transistors connected in parallel.

The pull-up circuit 3500b may also not include a resistor, unlike the pull-up circuit 3500a. That is, the pull-up circuit 3500b may include only M (M is a positive integer) transistors connected in parallel.

The calibration operation performed by the components shown in FIG. 7 is substantially the same as that described with reference to FIG. 6, so that the following description is omitted.

8 is a circuit diagram illustrating a calibration apparatus according to one embodiment.

The first pull-down circuit 8300, the second pull-down circuit 8400, and the pull-up circuit 8500 of FIG. 8 are similar to the first pull-down circuit 3300b, Circuit 3400b, and pull-up circuit 3500b may be substantially the same. In addition, the calibration apparatus 8000 of FIG. 8 may provide corresponding operations to the calibration apparatus 7000 of FIG.

Calibration apparatus 8000 may include a first operational amplifier 8600, a second operational amplifier 8700, and a reference voltage generator (not shown). Calibration apparatus 8000 may not include control signal generator 3800 of FIG.

The first operational amplifier 8600 may output the control signal PD_CONT to the first pull-down circuit 8300 and the second pull-down circuit 8400, respectively. The control signal PD_CONT may be an analog voltage signal for adjusting the resistance values of the first pull-down circuit 8300 and the second pull-down circuit 8400, respectively. The first operational amplifier 8600 can adjust the level of the control signal PD_CONT by comparing the level of the PD_CAL_VOL with the level of the reference voltage V _REF . For example, when the level of PD_CAL_VOL is larger than the level of the reference voltage V _REF , the level of the control signal PD_CONT becomes large, and when the level of PD_CAL_VOL is lower than the level of the reference voltage V _REF , Can be reduced.

The first pull-down circuit 8300 and the second pull-down circuit 8400 may include one or more NMOS transistors. In this case, the source terminal of the NMOS transistor may be connected to the node to which the power supply voltage VSS is supplied.

The first operational amplifier 8600 can adjust the resistance values of the first pull-down circuit 8300 and the second pull-down circuit 8400 by adjusting the level of the control signal PD_CONT. The level of the control signal PD_CONT, the level of the voltage supplied to the first pull-down circuit 8300, and the level of the voltage supplied to the first pull-down circuit 8300 by the current-voltage characteristic of the first pull- The resistance value of the first pull-down circuit 8300 can be determined according to the level of the current flowing in the first pull-down circuit 8300. The level of the control signal PD_CONT, the level of the voltage supplied to the second pull-down circuit 8400 and the level of the voltage supplied to the second pull-down circuit 8400 by the current-voltage characteristic of the second pull- The resistance value of the second pull-down circuit 8400 can be determined according to the level of the current flowing in the second pull-down circuit 8400. This will be described in more detail in FIG.

The second operational amplifier 8700 may output the control signal PU_CONT to the pull-up circuit 8500. [ The control signal PU_CONT may be an analog voltage signal for adjusting the resistance value of the pull-up circuit 8500. The second operational amplifier 8700 can adjust the level of the control signal PU_CONT by comparing the level of the PD_CAL_VOL and the level of the PU_CAL_VOL. As an example, when the level of the PU_CAL_VOL is greater than the level of the PD_CAL_VOL, the level of the control signal PU_CONT is decreased, and when the level of the PU_CAL_VOL is lower than the level of the PD_CAL_VOL, the level of the control signal PU_CONT may be increased.

The pull-up circuit 8500 may include one or more PMOS transistors. In this case, the source terminal of the PMOS transistor may be connected to the node to which the power supply voltage VDD is supplied.

The second operational amplifier 8700 can adjust the resistance value of the pull-up circuit 8500 included in the pull-up circuit 8500 by adjusting the level of the control signal PU_CONT. The level of the control signal PU_CONT, the level of the voltage supplied to the pull-up circuit 8500, and the level of the current flowing in the pull-up circuit 8500 are controlled by the current-voltage characteristic of the pull- The resistance value of the pull-up circuit 8500 can be adjusted. This will be described in more detail in FIG.

The pull-down calibration operation and the pull-up calibration operation performed in the calibration apparatus 8000 correspond to the pull-down calibration operation and the pull-up calibration operation described above with reference to FIG. 4, and therefore redundant description will be omitted below.

9 is a graph showing current-voltage characteristics of a transistor according to an embodiment. To facilitate understanding of the present invention, FIG. 8 is also referenced.

The graph 9000 may represent the current-voltage characteristics of the NMOS transistors included in the first pull-down circuit 8300 and the second pull-down circuit 8400. The horizontal axis of the graph 9000 represents the level of the voltage V _DS supplied between the drain and the source of the NMOS transistor and the vertical axis represents the level of the operating current I _D flowing between the drain and source of the NMOS transistor . However, the levels of the voltages (V _DS , V _GS ) and current (I _D ) indicated in the graph (9000) correspond to exemplary values, and the present invention is not limited thereto.

Referring to the graph 9000, the NMOS transistor has a current-to-voltage ( _VDS ) level at which the level of the operating current I _D varies depending on the level of the voltage V _DS supplied to the NMOS transistor and the level of the voltage V _GS supplied to the gate . ≪ / RTI > The first operational amplifier 8600 adjusts the level of the control signal PD_CONT so that the voltage V applied to the gate of the transistor included in the first pull-down circuit 8300 and the second pull- _GS ) can be adjusted. By way of example, the level of the voltage (V _GS ) supplied to the gate of the NMOS transistor may be the level of the control signal PD_CONT.

The resistance value of the NMOS transistor can be determined by the reciprocal of the slope of the current-voltage curve of the graph (9000). That is, in a period in which the level of the operating current I _D flowing through the NMOS transistor changes, the resistance value of the NMOS transistor is set to the level of the voltage V _DS applied to the NMOS transistor to the level of the operating current I _D flowing through the NMOS transistor Can be divided. Specifically, when the level of the drain voltage of the NMOS transistor is V _a , the level of the source voltage of the NMOS transistor is 0, and the level of the voltage (V _GS ) supplied to the gate of the NMOS transistor is 2.7, the resistance value of the NMOS transistor is V _a / I _a . In this case, if the level of the voltage (V _GS ) supplied to the gate of the NMOS transistor is changed to 2.1, the resistance value of the NMOS transistor can be adjusted to V _a / I _b .

The first pull-down circuit 8300 can include a plurality of NMOS transistors connected in parallel, and the resistance value of the first pull-down circuit 8300 can be changed according to the number of NMOS transistors. For example, when the number of NMOS transistors is N (a positive integer of 2 or more), the level of the drain voltage of the NMOS transistor is V _a , the level of the source voltage of the NMOS transistor is 0, _GS ) is 2.7, the resistance value of the NMOS transistor may be V _a / (N * I _a ).

Although only the current-voltage characteristic of the NMOS transistor is described with reference to FIG. 9, the level of the operating current flowing between the drain and the source of the PMOS transistor depends on the level of the voltage supplied between the drain and the source and the level of the voltage supplied to the gate And can have varying current-voltage characteristics. The second operational amplifier 8700 also adjusts the level of the control signal PU_CONT in a similar manner as the first operational amplifier 8600 adjusts the resistance value of the NMOS transistor by adjusting the level of the control signal PD_CONT. So that the resistance value of the PMOS transistor included in the pull-up circuit 8500 can be adjusted.

Referring again to FIG. 1, the storage device 1000 according to an embodiment may be configured such that any one of the pull-up circuit 1222 and the pull-down circuit 1224 is configured as a digital circuit and the other is configured as an analog circuit It is possible to implement. For example, when the pull-up circuit 1222 is implemented as a digital circuit and the pull-down circuit 1224 is implemented as an analog circuit, the storage device 1000 may generate a digital control signal (e.g., the control signal PU_CODE ) Circuit 1222 and adjust the resistance value of the pull-down circuit 1224 through an analog control signal (e.g., the control signal PD_CONT in FIG. 8) .

10 is a circuit diagram showing a calibration apparatus according to one embodiment.

10 to 14, the calibration operation performed when the reference resistor 4100 is located between the node 4150 and the node to which the power supply voltage VSS is supplied will be described, unlike in FIGS. When the reference resistor 4100 is located between the node 4150 and the node to which the power supply voltage VSS is supplied, the first pull-up circuit 4300, the second pull-up circuit 4400, The power supply voltage VSS is supplied between the node 4550 and the node to which the power supply voltage VDD is supplied and between the node 4550 and the node to which the power supply voltage VDD is supplied, May be located between the nodes. The node that supplies the power supply voltage VDD to the first pull-up circuit 4300 may be the same as or different from the node that supplies the power supply voltage VDD to the second pull-up circuit 4400. [ The node that supplies the power supply voltage VSS to the reference resistor 4100 may be the same as or different from the node that supplies the power supply voltage VSS to the pull-down circuit 4500.

The components 4200, 4600, 4700 and 4800 of the calibration apparatus 4000a shown in Fig. 10 correspond to the components 3200, 3600, 3700 and 3800 of the calibration apparatus 4000 shown in Fig. Lt; / RTI >

Calibration device 4000a may represent one of calibration device 1240 and calibration device 1440 of FIG. Calibration apparatus 4000a may include a reference voltage generator 4200, a first comparator 4600, a second comparator 4700, and a control signal generator 4800. [ The calibration device 4000a may perform a calibration operation to adjust the resistance values of the first pull-up circuit 4300, the second pull-up circuit 4400, and the pull-down circuit 4500.

The second pull-up circuit 4400 may include the same circuitry as the circuitry included in the first pull-up circuit 4300 and may have the same logic value as the control signal received by the first pull- Lt; / RTI > Therefore, the second pull-up circuit 4400 can be adjusted to have the same resistance value as that of the first pull-up circuit 4300. The first pull-up circuit 4300 and the second pull-up circuit 4400 may be included in the pull-up circuit 1222 of FIG. Alternatively, the first pull-up circuit 4300 and the second pull-up circuit 4400 may be included in the pull-up circuit 1422 of FIG. The second pull-up circuit 4400 may be used for the calibration operation of the pull-down circuit 4500.

The pull-down circuit 4500 may be included in the pull-down circuit 1224 or the pull-down circuit 1424 of FIG.

The first comparator 4600 may compare the level of the PU_CAL_VOL with the level of the reference voltage V _REF to output the first comparison result. The control signal generator 4800 outputs a control signal PU_CODE for adjusting the resistance value of the first pull-up circuit 4300 to the first pull-up circuit 4300 based on the received first comparison result . The control signal generator 4800 may output a control signal PU_CODE to the second pull-up circuit 4400 to adjust the resistance value of the second pull-up circuit 4400.

PU_CAL_VOL is the voltage at node 4150 located between reference resistor 4100 and first pull-up circuit 4300. PU_CAL_VOL may be supplied from the power supply voltage VSS and the level of PU_CAL_VOL may be determined based on the value of the reference resistor 4100 and the resistance value of the first pull-up circuit 4300. As an example, the level of PU_CAL_VOL may be determined according to [Equation 4].

(R _{pull -up_1} : resistance value of first pull-up circuit 4300, R _REF : value of reference resistance 4100)

Therefore, by changing the resistance value of the first pull-up circuit 4300, the level of PU_CAL_VOL can also be changed.

Hereinafter, the operation of the first comparator 4600 and the control signal generator 4800 described with reference to FIG. 10 corresponds to the operation of the first comparator 3600 and the control signal generator 3800 described with reference to FIG. 4 , Redundant explanations are omitted.

The second comparator 4700 may compare the level of the PU_CAL_VOL and the level of the PD_CAL_VOL to output the second comparison result. The control signal generator 4800 may output the control signal PD_CODE to the pull-down circuit 4500 to adjust the resistance value of the pull-down circuit 4500 based on the received second comparison result.

PD_CAL_VOL is the voltage at node 4550 located between pull-down circuit 4500 and second pull-up circuit 4400. PD_CAL_VOL may be supplied from the power supply voltage VSS and the level of PD_CAL_VOL may be determined based on the resistance value of the pull-down circuit 4500 and the resistance value of the second pull-up circuit 4400. As an example, the level of PD_CAL_VOL may be determined according to [Equation 5].

(R _{pull- up_2} : the resistance value of the second pull-up circuit 4400 that has been calibrated, R _{pull- down} : the resistance value of the _pull -down circuit 4500)

Therefore, by changing the resistance value of the pull-down circuit 4500, PD_CAL_VOL can also be changed.

The operations of the second comparator 4700 and the control signal generator 4800 described with reference to FIG. 10 correspond to the operations of the second comparator 3700 and the control signal generator 3800 described with reference to FIG. 4 , Redundant explanations are omitted.

11 is a flow chart showing how the calibration apparatus of FIG. 10 performs a calibration operation.

In S6100 operation, the first comparator 4600 may receive PU_CAL_VOL and a reference voltage (V _REF ).

In the S6200 operation, the first comparator 4600 can compare the level of the PU_CAL_VOL with the level of the reference voltage (V _REF ).

If the level of the PU_CAL_VOL is different from the level of the reference voltage V _REF , in the S6300 operation, the control signal generator 4800 can adjust the resistance value of the first pull-up circuit 4300. As the resistance value of the first pull-up circuit 4300 is adjusted, the level of PU_CAL_VOL is changed and the changed level of PU_CAL_VOL can again be compared with the level of the reference voltage V _REF in S6100 operation.

If the resistance value of the first pull-up circuit 4300 is equal to the value of the reference resistor 4100, the level of PU_CAL_VOL may be equal to the level of the reference voltage V _REF . If the level of PU_CAL_VOL is equal to the level of the reference voltage V _REF , the pull-up calibration operation can be terminated.

In S6400 operation, the second comparator 4700 may receive PD_CAL_VOL and PU_CAL_VOL. PD_CAL_VOL may be supplied from the power supply voltage VSS and the level of PD_CAL_VOL may be determined based on the resistance value of the pull-down circuit 4500 and the resistance value of the second pull-up circuit 4400.

In S6500 operation, second comparator 4700 may compare the level of PD_CAL_VOL with the level of PU_CAL_VOL.

If the level of PD_CAL_VOL is different from the level of PU_CAL_VOL, in S6600 operation, control signal generator 4800 may adjust the resistance value of pull-down circuit 4500. As the resistance value of the pull-down circuit 4500 is adjusted, the level of PD_CAL_VOL is changed, and the changed level of PD_CAL_VOL can be again compared with the level of PU_CAL_VOL in the S6400 operation.

If the resistance value of the pull-down circuit 4500 is equal to the resistance value of the second pull-up circuit 4400, the level of the PD_CAL_VOL and the level of the PU_CAL_VOL may be the same. If the level of PD_CAL_VOL is equal to the level of PU_CAL_VOL, the pull-down calibration operation can be terminated. That is, when the resistance values of the pull-up circuits 4300 and 4400 and the pull-down circuit 4500 are equal to the value of the reference resistor 4100, the calibration operation including the pull-down calibration and the pull-up calibration ends .

The pull-up calibration operation performed by repeating the S6100, S6200, and S6300 operations and the pull-down calibration operation performed by repeating the S6400, S6500, and S6600 operations can be performed independently of each other. Thus, the total time taken for the calibration operation can be shortened.

12 is a circuit diagram showing an exemplary configuration of the calibration apparatus of FIG. To facilitate understanding of the present invention, FIG. 6 is also referenced.

The components shown in Fig. 12 can provide the components and corresponding operations shown in Fig. Therefore, redundant descriptions will be omitted below.

Each of the first pull-up circuit 4300a and the second pull-up circuit 4400a may include K (K is a positive integer) transistors connected in parallel and a single resistor. Also, the pull-down circuit 4500a may include P (P is a positive integer) transistors connected in parallel and a single resistor.

When the reference resistor 4100 is located between the node 4150 and the node to which the power supply voltage VSS is supplied, the first pull-up circuit 4300a and the second pull- Each of the K transistors included in the up circuit 4400a may be a PMOS transistor. In this case, the drain terminal of the PMOS transistor may be connected to the node to which the power supply voltage VDD is supplied. In addition, each of the P transistors included in the pull-down circuit 4500a may be an NMOS transistor. In this case, the source terminal of the NMOS transistor may be connected to the node to which the power supply voltage VSS is supplied.

Control signal generator 4800 may adjust the resistance values of first pull-up circuit 4300a, second pull-up circuit 4400a and pull-down circuit 4500a. The control signal generator 4800 outputs an output signal to turn on and off the transistors included in each of the first pull-up circuit 4300a, the second pull-up circuit 4400a and the pull-down circuit 4500a. The control signal may be similar to the control signal described with reference to Fig.

However, when the control signal generator 4800 outputs the control signal PU_CODE [2: 0] including the bit string "101" to the first pull-up circuit 4300a, the first pull-up circuit 4300a ) And the third transistor may be turned off and the second transistor may be turned on. Further, when the control signal generator 4800 outputs the control signal PD_CODE [2: 0] including the bit string " 101 " to the pull-down circuit 4500a, The transistor and the third transistor may be turned on and the second transistor may be turned off.

Fig. 13 is a circuit diagram showing an exemplary configuration of the calibration apparatus of Fig. 10; Fig.

The components shown in Fig. 13 can provide the components and corresponding operations shown in Fig.

The first pull-up circuit 4300b and the second pull-up circuit 4400b in Fig. 13 are different from the first pull-up circuit 4300a and the second pull-up circuit 4400a in Fig. The first pull-up circuit 4300b and the second pull-up circuit 4400b do not include a resistor. In other words, the first pull-up circuit 4300b and the second pull-up circuit 4400b may include only N (N is a positive integer) transistors connected in parallel.

The pull-down circuit 4500b may also not include a resistor, unlike the pull-down circuit 4500a. That is, the pull-down circuit 4500b may include only M (M is a positive integer) transistors connected in parallel.

The calibration operation performed by the components shown in FIG. 13 is substantially the same as that described with reference to FIG. 12, so that redundant description will be omitted below.

14 is a circuit diagram showing a calibration apparatus according to one embodiment.

The first pull-up circuit 5300, the second pull-up circuit 5400 and the pull-down circuit 5500 of FIG. 14 each include a first pull-up circuit 4300b, a second pull- May be substantially the same as circuit 4400b and pull-down circuit 4500b.

Calibration apparatus 8000a may include a first operational amplifier 8600, a second operational amplifier 8700, and a reference voltage generator (not shown). Calibration apparatus 8000a may not include control signal generator 4800. [

The calibration device 8000a may adjust the resistance values of the first pull-up circuit 5300, the second pull-up circuit 5400 and the pull-down circuit 5500. The calibration device 8000a is connected to the calibration device 8000 of Figure 8 to adjust the resistance values of the first pull-up circuit 5300, the second pull-up circuit 5400 and the pull- May provide similar behavior. Therefore, redundant descriptions will be omitted below.

However, the first operational amplifier 8600 compares the level of the PU_CAL_VOL with the level of the reference voltage V _REF to generate the first pull-up circuit 5300, the second pull-up circuit 5400 including the PMOS transistor, Can be adjusted. In this case, the source terminal of the PMOS transistor may be connected to the node to which the power supply voltage VDD is supplied. Also, the second operational amplifier 8700 may compare the level of PU_CAL_VOL with the level of PD_CAL_VOL to adjust the resistance value of the pull-down circuit 5500 including the NMOS transistor. In this case, the source terminal of the NMOS transistor may be connected to the node to which the power supply voltage VSS is supplied.

15 is a block diagram showing a configuration of an electronic system according to an embodiment.

The electronic system 10000 may include a main processor 11010, a working memory 12000, a storage device 13000, a communication block 14000, a user interface 15000, and a bus 16000. By way of example, electronic system 10000 can be a desktop computer, a laptop computer, a tablet computer, a smart phone, a wearable device, a video game console, a workstation, A server, and the like.

The main processor 11010 may control overall operations of the electronic system 10000. The main processor 11010 may process various kinds of arithmetic and / or logic operations. To this end, the main processor 11010 may include a special-purpose circuit (e.g., a Field Programmable Gate Array (FPGA), Application Specific Integrated Circuits (ASICs), etc.). By way of example, main processor 11010 may include one or more processor cores and may be implemented as a general purpose processor, a dedicated processor, or an application processor.

The working memory 12000 may store data used in the operation of the electronic system 10000. [ By way of example, working memory 12000 may temporarily store data to be processed or to be processed by main processor 11010. [ For example, the working memory 12000 may be a volatile memory such as DRAM (Dynamic RAM), SDRAM (Synchronous RAM), and / or a memory such as a PRAM (Phase-change RAM), an MRAM (Magneto-resistive RAM), a ReRAM Non-volatile memory such as Ferro-electric RAM (FRAM) and the like.

Storage device 13000 may include a memory device and a controller. The memory device of the storage device 13000 can store data regardless of the power supply. By way of example, storage device 13000 may include non-volatile memory such as flash memory, PRAM, MRAM, ReRAM, FRAM, and the like. For example, the storage device 13000 may include a storage medium such as a solid state drive (SSD), an embedded multi media card (eMMC), a universal flash storage (UFS), and the like. The controller may control the memory device to store or output data.

The interface operation between the memory device of the storage device 13000 and the controller can be performed based on the analog voltage signal. The storage device 13000 can accurately adjust the level of the analog voltage signal using the pull-up circuit 13020 and the pull-up circuit 13040. Although only one pull-down circuit 13020 and one pull-up circuit 13040 are shown for convenience of explanation, each of the controllers and memory devices in the storage device 13000 includes a pull-down resistor and a pull- . ≪ / RTI >

However, the values of the pull-down circuit 13020 and the pull-up circuit 13040 may change according to the PVT condition. When the values of the pull-down circuit 13020 and the pull-up circuit 13040 change The storage device 13000 may also change the level of the analog voltage signal transmitted between the pull-down resistor 13020 so that the storage device 13000 may malfunction or the data output from the storage device 13000 may be damaged .

The calibration device 13060 of the storage device 13000 can independently adjust the resistance value of the pull-down circuit 13020 and the resistance value of the pull-up circuit 13040. By way of example, calibration device 13060 can independently adjust the resistance of pull-down circuit 13020 and the resistance of pull-up circuit 13040 based on the method described above with reference to FIGS. have. Down unit 13020 and the resistance value of the pull-up circuit 13040 are respectively set to the outside of the storage apparatus 13000 and the pull-down circuit 13040, respectively, when the pull-down calibration operation and the pull- May be the same as the value of the reference resistor (not shown).

Communication block 14000 may communicate with an external device / system of electronic system 10000. By way of example, communication block 14000 may be a wireless communication device such as Long Term Evolution (LTE), Worldwide Interoperability for Microwave Access (WIMAX), Global System for Mobile communications (GSM), Code Division Multiple Access (CDMA) , And / or at least one of various wireless communication protocols such as Wi-Fi (Wireless Fidelity), Radio Frequency Identification (RFID), and / And may support at least one of various wired communication protocols.

The user interface 15000 may mediate communication between the user and the electronic system 10000. For example, the user interface 15000 may include an input interface such as a keyboard, a mouse, a keypad, a button, a touch panel, a touch screen, a touch pad, a touch ball, a camera, a microphone, a gyroscope sensor, For example, the user interface 15000 may include an output interface such as a liquid crystal display (LCD) device, a light emitting diode (LED) display device, an organic light emitting diode (OLED) display device, an AMOLED . ≪ / RTI >

Bus 16000 may provide a communication path between the components of electronic system 10000. The components of electronic system 10000 can exchange data with each other based on the bus format of bus 16000. [ For example, the bus format may be a USB, a Small Computer System Interface (SCSI), a Peripheral Component Interconnect Express (PCIe), a Mobile PCIe (M-PCIe), an Advanced Technology Attachment (ATA), a Parallel ATA (PATA) , Serial Attached SCSI (SAS), Integrated Drive Electronics (IDE), Enhanced IDE (EIDE), Nonvolatile Memory Express (NVMe), Universal Flash Storage (UFS), and the like.

The above description is specific embodiments for carrying out the present invention. The present invention will also include embodiments that are not only described in the above-described embodiments, but also can be simply modified or changed easily. In addition, the present invention will also include techniques that can be easily modified and implemented using the embodiments. Therefore, the scope of the present invention should not be limited to the above-described embodiments, but should be determined by the claims equivalent to the claims of the present invention as well as the following claims.

Claims (10)

A first comparator configured to output a first comparison result comparing the level of the first voltage of the first node with the level of the reference voltage;
A second comparator configured to output a second comparison result comparing the level of the first voltage with the level of a second voltage of the second node; And
Outputting a first control signal for adjusting a first resistance value of the first resistance circuit based on the first comparison result and outputting a second control signal for adjusting a second resistance value of the second resistance circuit based on the second comparison result And a control signal generator configured to output a second control signal,
The first node being located between the first resistor circuit and a reference resistor,
And the second node is located between the third resistor circuit and the second resistor circuit, the third resistor circuit being adjusted to have the same resistance value as the first resistor value. The method according to claim 1,
Wherein the control signal generator outputs the second control signal while outputting the first control signal. The method according to claim 1,
The control signal generator stops outputting the first control signal when the first comparison result indicates that the level of the first voltage is equal to the level of the reference voltage, And to stop outputting the second control signal if the level of the first voltage is equal to the level of the second voltage. The method according to claim 1,
The first resistor circuit includes first transistors connected in parallel,
The second resistor circuit includes second transistors connected in parallel,
Wherein each of the first transistors is turned on or off based on the first control signal,
And each of the second transistors is turned on or off based on the second control signal. 5. The method of claim 4,
The control signal generator outputs the first control signal including a bit string for turning on or off each of the first transistors based on the first comparison result, And outputs the second control signal including a bit string for turning on or off each of the second transistors based on the first control signal. The method according to claim 1,
The third resistor circuit includes the same circuit as the first resistor circuit,
Wherein the third resistance value of the third resistance circuit is adjusted based on the first control signal to be the first resistance value. A first operational amplifier configured to output a first control signal for adjusting a first resistance value of a first resistor circuit by comparing a level of a first voltage of the first node with a level of a reference voltage; And
And a second operational amplifier configured to output a second control signal for adjusting a second resistance value of the second resistance circuit by comparing the level of the first voltage with the level of the second voltage of the second node,
The first node being located between the first resistor circuit and a reference resistor,
And the second node is located between the third resistor circuit and the second resistor circuit, the third resistor circuit being adjusted to have the same resistance value as the first resistor value. 8. The method of claim 7,
Wherein the first resistor circuit is located between the first node and a node to which a first supply voltage is applied,
Wherein the reference resistor is located between the first node and a node to which a second supply voltage is applied,
The third resistor circuit being located between the second node and a node to which the first supply voltage is applied,
Wherein the second resistor circuit is located between the second node and a node to which the second supply voltage is applied. 9. The method of claim 8,
Wherein the level of the first supply voltage is lower than the level of the second supply voltage,
Wherein the first resistor circuit and the third resistor circuit each include one or more NMOS transistors connected in parallel,
Wherein the second resistor circuit comprises at least one PMOS transistor connected in parallel. A memory device; And
The first resistance value of the first resistance circuit is adjusted based on the first comparison result obtained by comparing the level of the first voltage with the level of the first reference voltage and the level of the first voltage is compared with the level of the second voltage And a controller configured to perform a calibration operation to adjust a second resistance value of the second resistance circuit based on the second comparison result,
Wherein the level of the first voltage is determined based on the first resistance value and the first reference resistance value,
Wherein the level of the second voltage is further configured to determine based on the first resistance value and the second resistance value.

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