KR100656427B1 - Apparatus for generating power up signal of semiconductor memory - Google Patents

Abstract

A power up signal generator of a semiconductor memory is provided to supply a stable power supply voltage by enabling a power up signal after an external voltage reaches an accurate target voltage by preventing an operation error of an inverter and a latch during initial supply of the external voltage. A detection unit(110) outputs a detection signal by detecting whether an external voltage is above a first set level. An output unit(120) changes the detection signal into a logic level signal and then outputs a power up signal. An output control unit(130) controls the output unit in order for the power up signal to maintain a disable state when the external voltage is below a second set level. The first set level is a voltage level two times of a threshold voltage of one of transistors used in the power up signal generator.

Description

Apparatus for Generating Power up Signal of Semiconductor Memory

1 is a circuit diagram showing a configuration of a power up signal generator of a semiconductor memory according to the prior art;

2 is a circuit diagram showing the configuration of a power-up signal generator of a semiconductor memory according to a first embodiment of the present invention;

3 is a circuit diagram showing the configuration of a power-up signal generator of a semiconductor memory according to a second embodiment of the present invention;

4 is a circuit diagram showing the configuration of a power-up signal generator of a semiconductor memory according to a third embodiment of the present invention;

5 is a circuit diagram showing the configuration of a power-up signal generator of a semiconductor memory according to a fourth embodiment of the present invention;

6 is a waveform diagram illustrating a power up signal generated according to the first to fourth embodiments of the present invention.

<Description of Symbols for Main Parts of Drawings>

110: voltage detector 111: voltage detector

112: protection circuit section 113: signal generating section

120: output unit 121: inverter

130: output control unit 131: switching unit

132: first switching controller 133: second switching controller

140: output stabilization unit 150: delay unit

160: second delay unit

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to semiconductor memories, and more particularly, to a power up signal generator for semiconductor memories.

The semiconductor memory should be provided with a circuit for generating a signal for notifying that the external power source has reached a level for normal operation of the semiconductor memory, that is, a power-up signal.

If the power-up signal is not generated normally, that is, if the power-up signal is enabled before the external power source reaches a predetermined level, the power-up signal because an abnormal level may be supplied to each circuit of the semiconductor memory and cause a malfunction. The generating circuit is essential and its reliability is also very important.

Hereinafter, a power up signal generator of a semiconductor memory according to the related art will be described with reference to FIG. 1.

As shown in FIG. 1, a power-up signal generator of a semiconductor memory according to the related art has a distribution resistor R1 and R2 connected in series between an external power supply VDD terminal and a ground terminal VSS, and the distribution resistor R1. A transistor N0 having a gate and a source connected to an intermediate node A of R2 and the external power source VDD connected to a drain, and a transistor P1 connected between the external power source VDD terminal and a ground terminal VSS. N1), an inverter 11 composed of transistors P2 and N2, and a transistor N3 operating as a latch for maintaining the output level of the inverter 11. At this time, the transistor N0 operates as a diode by connecting a gate and a source to the node A in common.

Referring to the operation of the power-up signal generator of the semiconductor memory according to the prior art configured as described above are as follows.

In this case, the conventional technology has a threshold voltage VT level by the P-type transistor and the N-type transistor when the external power supply VDD rises to a target level at which the power-up signal can be generated at 0V. Therefore, when the external power supply VDD becomes 2VT or more which is the sum of the threshold voltages of the P-type transistor and the N-type transistor, normal operation is possible. Therefore, in order to detect that the external power supply VDD becomes 2VT, the voltage level output from the output node A of the distribution resistors R1 and R2 should be 1/2 VDD, which is half of the external power supply VDD. The circuit must be configured so that the 1/2 VDD becomes greater than or equal to the VT of the predetermined transistor to satisfy the condition for turning on the transistor. Therefore, the distribution resistors R1 and R2 have the same resistance value.

First, the external power supply VDD level is divided by 1/2 VDD by the distribution resistors R1 and R2 and applied to the gate of the transistor N1 through the node A.

Subsequently, when the voltage of the node A, that is, 1/2 VDD becomes equal to or higher than the threshold voltage VT of the transistor N1, the transistor N1 is turned on so that the node DET voltage becomes a ground level, that is, a low level. do.

At this time, the fact that 1/2 VDD rises above the threshold voltage VT of the transistor N1 means that VDD becomes 2VT or more.

The node DET is converted to a high level through the inverter 11, and a power up signal PWRUP is output at a high level. That is, the power up signal PWRUP is enabled. At this time, the node (DET) output level is buffered through the inverter 11 to change to a complete logic level.

The output of the inverter 11 is latched through the transistor N3 to maintain the high level.

On the other hand, since the transistor N0 acts as a diode, when the voltage of the node A becomes VDD + VT or more, the charge of the node A is moved to the external power supply terminal VDD so that the internal of the transistor N0 is driven by a high voltage. Perform an operation to prevent damage to the circuit.

However, according to the related art, the gate level of the transistor that performs the latch operation is increased due to the pull-up of the inverter 11 before the external power supply VDD is supplied, that is, before the external power supply VDD reaches VT. In a state higher than the ground level, the power-up signal PWRUP is enabled before the external power supply VDD reaches the target level, thereby causing a malfunction of the memory.

In addition, since the manufacturing technology of the semiconductor memory is becoming more fine and the internal voltage level is gradually lowered, the signal generation error of the conventional power-up generation circuit described above and the malfunction of the memory are inevitably more frequent.

SUMMARY OF THE INVENTION The present invention has been made in view of the above-mentioned conventional problems, and an object thereof is to provide a power-up signal generator of a semiconductor memory capable of preventing a power-up signal generation error.

The apparatus for generating a power up signal of a semiconductor memory according to the present invention comprises: detecting means for detecting whether an external power source is above a first set level and outputting a detection signal according thereto, and changing the detection signal into a logic level signal to power up a signal. And output control means for controlling the output means to maintain the disabled state when the external power source is less than the second set level.

A power up signal generating apparatus of a semiconductor memory according to the present invention includes a detecting means for detecting whether an external power supply is greater than or equal to a first set level for internal normal operation, and outputting a detection signal according to the power supply by changing the detection signal into a logic level signal. Output means for outputting an up signal, and delay means for delaying a power supply for generating a power up signal of the output means for a predetermined time so that the power up signal remains disabled for the delay time. do.

Hereinafter, a first to fourth embodiments of a power up signal generating apparatus of a semiconductor memory according to the present invention will be described with reference to the accompanying drawings.

FIG. 2 is a circuit diagram showing a configuration of a power up signal generator of a semiconductor memory according to a first embodiment of the present invention. FIG. 3 is a diagram showing a configuration of a power up signal generator of a semiconductor memory according to a second embodiment of the present invention. 4 is a circuit diagram showing a configuration of a power up signal generator of a semiconductor memory according to a third embodiment of the present invention, and FIG. 5 is a configuration of a power up signal generator of a semiconductor memory according to a fourth embodiment of the present invention. 6 is a waveform diagram showing a power-up signal generated according to the first to fourth embodiments of the present invention.

First Embodiment

As shown in FIG. 2, the first embodiment of the power-up signal generator of the semiconductor memory according to the present invention detects whether the external power supply (VDD) level is equal to or greater than a first set level for internal normal operation, and accordingly detects a signal accordingly. A detection unit 110 for outputting a signal, an output unit 120 for outputting a power-up signal PWRUP by converting the detection signal into a logic level signal, and the external power supply VDD level as a second set level, that is, a transistor threshold. The output controller 130 controls the output unit 120 to maintain the disable state when the power-up signal PWRUP is less than the voltage VT.

In this case, it is assumed that the first setting level is 2VT which is twice the transistor threshold voltage (hereinafter, referred to as VT), and the second setting level is VT.

The detector 110 detects whether the voltage detector 111 detects the voltage of the external power supply VDD, the output of the voltage detector 111 is greater than or equal to the first set level, and outputs a detection signal according thereto. When the output of the generator 113 and the voltage detector 111 is greater than or equal to the third set level, the protection circuit unit 112 that blocks the output of the voltage detector 111 from being applied to the signal generator 113. Include. At this time, the third setting level is VDD + VT. In addition, the voltage detector 111 includes distribution resistors R1 and R2 connected in series between an external power supply VDD terminal and a ground terminal. The protection circuit 112 includes a transistor N10 having a drain connected to the external power supply VDD terminal and a source and a gate commonly connected to an output terminal of the voltage detector 111. The signal generator 113 has a source connected to the external power supply VDD terminal, a gate connected to the first transistor P11, and a source connected to the drain of the first transistor P11. Is grounded and includes a second transistor N11 connected to an output terminal of the voltage detector 111.

At this time, when the external power supply VDD rises to a target level capable of generating the power-up signal PWRUP at 0V, the P-type transistor and the N-type transistor each have a threshold voltage VT level. Therefore, there may be a difference due to device characteristics and circuit design characteristics. However, the optimal target level for the normal operation of the power-up circuit is 2VT which is the sum of the threshold voltages of the P-type transistor and the N-type transistor. It's time. Therefore, in order to detect that the external power supply VDD becomes 2VT, the voltage level output from the output node A of the distribution resistors R1 and R2 should be 1/2 VDD, and the 1/2 VDD is greater than or equal to VT. In this case, a circuit must be configured to satisfy a condition for turning on a predetermined transistor. Therefore, the distribution resistors R11 and R12 have the same resistance value.

The output unit 120 includes an inverter 121 and a transistor N13 for latching an output of the inverter 121.

The output controller 130 turns on the switching unit 131 for supplying or blocking the external power VDD to the output unit 120, and when the external power VDD is equal to or greater than the VT. The first switching controller 132 and the second switching controller 133 to keep the switching unit 131 in an off state until the switching unit 131 is turned on by the first switching control unit 132. It is composed. In this case, the switching unit 131 includes a transistor P14 having a drain connected to the external power supply VDD and a source connected to the output unit 120. The first switching controller 132 includes a transistor N14 having a drain connected to the switching unit 131, a source grounded, and a gate connected to the external power source VDD. The second switching controller 133 includes a transistor P13 having a drain connected to the external power supply VDD and a gate and a source connected to the switching unit 131.

The operation of the first embodiment of the present invention configured as described above is as follows.

First, the level of the external power supply VDD is divided by 1/2 VDD by the distribution resistors R11 and R12 of the voltage detector 111 so that the gate of the transistor N11 of the signal generator 113 is passed through the node A. Is applied to.

Subsequently, when the 1/2 VDD rises above VT of the transistor N11, the transistor N10 is turned on to output a low level detection signal through the node DET.

At this time, the fact that 1/2 VDD rises above VT of the transistor N11 means that VDD becomes 2VT or more.

The low level detection signal is output as a high level power up signal PWRUP through the inverter 121 of the output unit 120. That is, the power up signal PWRUP is enabled. At this time, the node DET output level is buffered through the inverter 121 to be changed to a power-up signal PWRUP of a complete logic level.

Subsequently, the output of the inverter 121 is latched through the transistor N13 to maintain the enable level, that is, the high level.

On the other hand, since the transistor N10 operates as a diode, when the voltage of the node A becomes VDD + VT or more, the voltage of the node A is blocked from being applied to the signal generator 113. That is, the charge of the node A flows to the external power supply terminal VDD to prevent damage to the internal circuit due to the high voltage.

Meanwhile, since the external power supply VDD applied to the gate of the transistor N14 of the first switching control unit 132 of the output control unit 130 does not reach VT at the initial supply of the external power supply VDD, the state is maintained in the off state. The transistor P14 of the switching unit 131 is turned off to block the external power supply VDD connected to the drain from being applied to the transistor P12 of the inverter 121. At the same time, the second switching controller 133 operates as a capacitor to maintain the gate of the transistor P14 of the switching unit 131 at a level higher than the ground level to more stably maintain the off state of the switching unit 131. .

Subsequently, when the level of the external power supply VDD rises to VT or more, the first switching control unit 132 of the output control unit 130 is turned on, and the switching unit 131 is turned on to supply the external power supply VDD to the inverter 121. ) Is supplied, thereby making the inverter 121 operable.

At this time, unlike the detection unit 110 operates on the basis that the external power supply (VDD) is 2VT or more, the output control unit 130 operates on the basis that the external power supply (VDD) is VT or more. same. Since a problem of the prior art occurs during a period in which the external power source VDD is less than VT, the external power source VDD is supplied to the output unit 120 through the output control unit 130 until the external power source VDD reaches VT. When the external power supply VDD reaches VT, the external power supply VDD is supplied to the output unit 120 to prepare for an operation. Then, the detection signal output from the detection unit 110 is set to a complete logic level. It is output by the power-up signal PWRUP.

Therefore, a problem of the related art in which the gate level of the latch transistor N13 becomes higher than the ground level due to the pull-up of the inverter at the initial supply of the external power supply VDD is abnormally enabled. Can be solved.

Second Embodiment

According to the second embodiment of the power-up signal generator of the semiconductor memory according to the present invention, as shown in FIG. 3, an output stabilization unit 140 is added between the output unit 120 and the output control unit 130. Except for the configuration thereof, the first embodiment of the present invention shown in FIG.

The output stabilization unit 140 includes a capacitor NC10 configured using a transistor.

At this time, the output stabilization unit 140 when the VT of the transistor P14 of the switching unit 131 is too low, or the level rise of the supplied external power supply VDD is made very slowly, the first switching control unit 132 described above This is to prepare for the case in which the control operation of the switching unit 131 by the second switching control unit 133 is not normally performed or the control ability decreases.

The operation of the second embodiment of the present invention configured as described above is as follows.

Although the first switching control unit 132 and the second switching control unit 133 do not normally control the switching unit 131 due to the above-described VT and external power supply VDD problems during the period in which the external power supply VDD is less than VT, The output stabilization unit 140 charges the external power VDD output to the inverter 121 through the switching unit 131 so as to correspond to the corresponding charging capacity, thereby generating a power-up signal PWRUP error of the output unit 120. Can be completely prevented. Since other operations are the same as those in the first embodiment of the present invention, description thereof will be omitted.

Third embodiment

As shown in FIG. 4, the third embodiment of the power-up signal generator of the semiconductor memory according to the present invention detects whether the external power supply (VDD) level is equal to or greater than the first set level for internal normal operation, and accordingly detects the signal. A detection unit 110 for outputting a signal, an output unit 120 for outputting a power-up signal PWRUP by changing the detection signal to a logic level signal, and a power-up signal PWRUP for generating the output unit 120. And a delay unit 150 for delaying the external power supply VDD for a predetermined time to maintain the power-up signal PWRUP in a disabled state during the delay time.

In this case, it is assumed that the first set level is 2VT which is twice the transistor threshold voltage (hereinafter, referred to as VT).

The detector 110 detects whether the voltage detector 111 detects the voltage of the external power supply VDD, and whether the output of the voltage detector 111 is equal to or greater than the first set level, and generates a signal corresponding thereto. And a protection circuit unit 112 for blocking the output of the voltage detector 111 from being applied to the signal generator 113 when the output of the voltage detector 111 is greater than or equal to a third set level. do. At this time, the third setting level is VDD + VT. In addition, the voltage detector 111 includes distribution resistors R1 and R2 connected in series between an external power supply VDD terminal and a ground terminal. The protection circuit 112 includes a transistor N10 having a drain connected to the external power supply VDD terminal and a source and a gate commonly connected to an output terminal of the voltage detector 111. The signal generator 113 has a source connected to the external power supply VDD terminal, a gate connected to the first transistor P11, and a source connected to the drain of the first transistor P11. Is grounded and includes a second transistor N11 connected to an output terminal of the voltage detector 111.

At this time, when the external power supply VDD rises to a target level capable of generating the power-up signal PWRUP at 0V, the P-type transistor and the N-type transistor each have a threshold voltage VT level. Therefore, although there may be a difference due to device characteristics and circuit design characteristics, the optimum target level for the normal operation of the power-up circuit is 2VT where the external power supply (VDD) is the sum of the threshold voltages of the P-type transistor and the N-type transistor. It is when Therefore, in order to detect that the external power supply VDD becomes 2VT, the voltage level output from the output node A of the distribution resistors R1 and R2 should be 1/2 VDD, and the 1/2 VDD is greater than or equal to VT. In this case, a circuit must be configured to satisfy a condition for turning on a predetermined transistor. Therefore, the distribution resistors R11 and R12 have the same resistance value.

The output unit 120 includes an inverter 121 and a transistor N13 for latching an output of the inverter 121.

The delay unit 150 includes a delay element connected between an external power supply VDD terminal and the output unit 120, that is, a resistor R13. The resistor R13 may use an active resistor or a passive resistor.

The operation of the third embodiment of the present invention configured as described above is as follows.

First, the level of the external power supply VDD is divided by 1/2 VDD by the distribution resistors R11 and R12 of the voltage detector 111 so that the gate of the transistor N11 of the signal generator 113 is passed through the node A. Is applied to.

Subsequently, when the 1/2 VDD rises above VT of the transistor N11, the transistor N10 is turned on to output a low level detection signal through the node DET.

At this time, the fact that 1/2 VDD rises above VT of the transistor N11 means that VDD becomes 2VT or more.

The low level detection signal is output as a high level power up signal PWRUP through the inverter 121 of the output unit 120. That is, the power up signal PWRUP is enabled. At this time, the node DET output level is buffered through the inverter 121 to be changed to a power-up signal PWRUP of a complete logic level.

In addition, the output of the inverter 121 is latched through the transistor N13 to maintain an enable level, that is, a high level.

On the other hand, since the transistor N10 operates as a diode, when the voltage of the node A becomes VDD + VT or more, the voltage of the node A is blocked from being applied to the signal generator 113. That is, the charge of the node A flows to the external power supply terminal VDD to prevent damage to the internal circuit due to the high voltage.

On the other hand, before the external power source VDD reaches VT, the inverter 121 does not operate because the external power source VDD drops by the resistor R13 of the delay unit 150.

Subsequently, when the external power supply VDD continues to rise, the inverter 121 may normally operate from a predetermined level or more, for example, from the VT level even if the external power supply VDD continues to rise. In this case, it is preferable to use the resistor R13 having a resistance value that allows the inverter 121 to operate normally when the voltage level dropped by itself when the external power supply VDD is higher than VT and lower than 2VT. .

Therefore, a problem of the related art in which the gate level of the latch transistor N13 becomes higher than the ground level due to the pull-up of the inverter at the initial supply of the external power supply VDD is abnormally enabled. Can be solved.

Fourth Embodiment

In the fourth embodiment of the power-up signal generator of the semiconductor memory according to the present invention, as shown in FIG. 5, the second delay unit 160 is added between the output unit 120 and the delay unit 150. Except for the configuration thereof, the third embodiment of the present invention shown in FIG. 4 is identical.

The second delay unit 160 includes a capacitor NC20 configured using a transistor.

At this time, the second delay unit 160 is the inverter 121 by the delay unit 150 when the surface resistance value of the delay unit 150 is small or the level rise of the supplied external power supply VDD is made very slowly. This is to prepare for the case that control operation is not performed normally or control ability decreases.

The operation of the fourth embodiment of the present invention configured as described above is as follows.

Although the delay unit 150 does not normally control the inverter 121 due to the above-described surface resistance value problem and the external power source VDD problem during the period in which the external power source VDD is less than VT, the second delay unit 160 By charging the external power (VDD) output to the inverter 121 through the delay unit 150 to correspond to the corresponding charging capacity can completely prevent the power-up signal (PWRUP) generation error of the output unit 120. have. Since other operations are the same as those in the third embodiment of the present invention, the description thereof will be omitted.

6 illustrates the power-up signal PWRUP output waveform according to the external power supply VDD variation in the first to fourth embodiments of the present invention.

That is, assuming that VT is 0.5V, in the conventional case (left), it can be seen that the power-up signal PWRUP is abnormally enabled before VDD rises to 1V (2VT).

However, according to the present invention, a slight difference may occur in the power-up signal PWRUP timing and voltage level in each embodiment. However, when VDD is less than 1V, the power-up signal PWRUP remains disabled. The power-up signal PWRUP is enabled from the time point when 1V or more becomes 1V.

Of course, the above example is limited to the example that the VT is 0.5V, it can be changed as much as the actual circuit design depending on the environmental conditions and device characteristics.

As those skilled in the art to which the present invention pertains may implement the present invention in other specific forms without changing the technical spirit or essential features, the embodiments described above should be understood as illustrative and not restrictive in all aspects. Should be. The scope of the present invention is shown by the following claims rather than the detailed description, and all changes or modifications derived from the meaning and scope of the claims and their equivalents should be construed as being included in the scope of the present invention. do.

The power-up signal generator of the semiconductor memory according to the present invention prevents a malfunction of the inverter and the latch in the initial stage of the external power supply to enable the power-up signal after the external power source reaches the target level accurately, thereby enabling stable power supply. There is an effect that can improve the reliability of the memory.

Claims (23)

Detecting means for detecting whether the external power source is above the first set level and outputting a detection signal according thereto; Output means for converting the detection signal into a logic level signal and outputting the power-up signal; And And output control means for controlling the output means to maintain the power-up signal in a disabled state when the external power source is less than a second set level. The method of claim 1, And the first set level is a voltage level corresponding to twice the threshold voltage of any one of transistors used in the power up signal generator. The method of claim 1, And the second set level is the same voltage level as the threshold voltage of any one of transistors used in the power up signal generator. The method of claim 1, The detecting means includes a voltage detector for detecting a voltage of the external power source, and And a signal generator for detecting whether an output of the voltage detector is equal to or greater than the first set level and outputting a detection signal according to the output of the voltage detector. The method of claim 4, wherein And the voltage detection unit is a distribution resistor having one end connected to the external power supply terminal and the other end grounded, and an output terminal connected to a node between the resistors. The method of claim 5, And a distribution ratio of the distribution resistor is determined by the first set level. The method of claim 4, wherein The signal generator includes a first transistor having a source connected to the external power supply terminal and a gate grounded; And a second transistor having a source connected to a drain of the first transistor, a drain connected to a ground, and an output terminal of the voltage detector connected to a gate thereof. The method of claim 4, wherein And a protection circuit unit which blocks the output of the voltage detector from being applied to the signal generator when the output of the voltage detector is greater than or equal to a third set level. The method of claim 8, The third set level is a voltage level corresponding to the sum of the threshold voltage VT of any one of the transistors used in the power-up signal generator and the external power supply voltage. . The method of claim 8, The protection circuit is a power up signal generating device of a semiconductor memory, characterized in that the drain is connected to the external power supply terminal, the source and the gate is a transistor commonly connected to the output terminal of the voltage detector. The method of claim 1, The output means is an inverter, and And a transistor configured to latch an output of the inverter. The method of claim 1, The output control means is a switching unit for supplying or cutting off the external power to the output means, A first switching controller which turns on the switching unit when the external power is higher than or equal to the second set level, and And a second switching control unit which keeps the switching unit in the off state until the switching unit is turned on by the first switching control unit. The method of claim 12, And the switching unit is a transistor having a drain connected to the external power supply terminal and a source connected to the output unit. The method of claim 12, The first switching controller is a power up signal generating device of a semiconductor memory, characterized in that the drain is connected to the switching unit, the source is grounded, the gate is connected to the external power source. The method of claim 12, And the second switching controller is a transistor having the external power connected to a drain and a gate and a source connected to the switching unit. The method of claim 1, And an output stabilization means connected between said output means and said output control means. The method of claim 16, And said output stabilization means is a capacitor. Detecting means for detecting whether the external power source is above a first set level for internal normal operation and outputting a detection signal according thereto; Output means for converting the detection signal into a logic level signal and outputting the power up signal; And And a delay means for delaying a power supply for generating a power-up signal of the output means for a predetermined time to maintain the power-up signal in a disabled state for the delay time. The method of claim 18, And the delay means includes a delay element connected between the external power supply terminal and the output means. The method of claim 19, And the delay element includes a resistor. The method of claim 20, And the resistor is an active resistor or a passive resistor. The method of claim 18, And a second delay means connected to said delay means. The method of claim 22, And said second delay means comprises a capacitor.

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