KR20120042273A - Power-up signal generating circuit and semiconductor device including the same - Google Patents

Power-up signal generating circuit and semiconductor device including the same Download PDF

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Publication number
KR20120042273A
KR20120042273A KR1020100103890A KR20100103890A KR20120042273A KR 20120042273 A KR20120042273 A KR 20120042273A KR 1020100103890 A KR1020100103890 A KR 1020100103890A KR 20100103890 A KR20100103890 A KR 20100103890A KR 20120042273 A KR20120042273 A KR 20120042273A
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KR
South Korea
Prior art keywords
power
voltage
signal
target level
power supply
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KR1020100103890A
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Korean (ko)
Inventor
임희준
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에스케이하이닉스 주식회사
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Priority to KR1020100103890A priority Critical patent/KR20120042273A/en
Publication of KR20120042273A publication Critical patent/KR20120042273A/en

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    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
    • G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
    • G11C11/4072—Circuits for initialization, powering up or down, clearing memory or presetting
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
    • G11C29/08—Functional testing, e.g. testing during refresh, power-on self testing [POST] or distributed testing
    • G11C29/12—Built-in arrangements for testing, e.g. built-in self testing [BIST] or interconnection details
    • G11C29/12005—Built-in arrangements for testing, e.g. built-in self testing [BIST] or interconnection details comprising voltage or current generators
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
    • G11C29/08—Functional testing, e.g. testing during refresh, power-on self testing [POST] or distributed testing
    • G11C29/12—Built-in arrangements for testing, e.g. built-in self testing [BIST] or interconnection details
    • G11C29/14—Implementation of control logic, e.g. test mode decoders
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/20—Memory cell initialisation circuits, e.g. when powering up or down, memory clear, latent image memory

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computer Hardware Design (AREA)
  • Semiconductor Integrated Circuits (AREA)

Abstract

PURPOSE: A power up signal generating circuit and a semiconductor device including the same are provided to stably control a target level by testing the variation of the target level of a power up signal with regard to a low power voltage. CONSTITUTION: A control signal generating unit(101) is driven with a first power voltage. The control signal generating unit generates a control signal for varying a target level of the power up signal with regard to a second power voltage. A power up signal generating unit(103) varies a target level in response to a control signal and activates the power up signal if a second power voltage rises over the target level. The first power voltage is higher than the second power voltage.

Description

Power-up signal generation circuit and semiconductor device including the same {POWER-UP SIGNAL GENERATING CIRCUIT AND SEMICONDUCTOR DEVICE INCLUDING THE SAME}

The present invention relates to a power-up signal generation circuit and a semiconductor device including the same.

In general, semiconductor devices such as DRAMs include power-up signal generation circuits to ensure stable operation of internal circuits. The power supply voltage input to the semiconductor device gradually increases to reach a target voltage level. When the power supply voltage is directly applied to the semiconductor internal circuit before reaching the target level, the latch-up and The same problem occurs, which causes great damage to the semiconductor device. Therefore, the power-up signal generation circuit activates the power-up signal when the power supply voltage rises to a target level for stable operation of the internal circuit so that the semiconductor device is initialized.

As such, the target level of the power-up signal is an important factor in determining the operation timing of the semiconductor device. However, a problem often arises in that the target level intended for circuit design varies depending on the operating conditions of the semiconductor device or the process state of the transistor used. Therefore, there is a need for a method for adjusting a target level even in a wafer state in which a process is completed after circuit design. Therefore, a method of finding an activation point of a more efficient and stable power-up signal through a test of varying the target level has been proposed.

However, in the conventional semiconductor device to which one power supply voltage is applied, it is virtually impossible to perform a test that varies the target level of the power-up signal in the same circuit. The semiconductor device is initialized by a power-up signal that is activated from the time when the power supply voltage reaches the target level. In a circuit that is applied with the same power supply voltage, varying the target level of the power-up signal may occur when the circuit is not initialized. This is because a control signal for controlling the circuit is generated.

The present invention has been proposed to solve the above problems, and by performing a test for varying a target level of a power-up signal for a low power supply voltage in a semiconductor device receiving two power supply voltages, the target level is more efficiently and stably. It is an object of the present invention to provide a power-up signal generation circuit that can adjust.

The power-up signal generation circuit according to the present invention for achieving the above object is driven by receiving a first power supply voltage, the control signal for generating a control signal for varying the target level of the power-up signal for the second power supply voltage A generator and a power-up signal generator configured to vary the target level in response to the control signal, and activate the power-up signal when the second power supply voltage rises above the target level. It is characterized in that higher than the second power supply voltage.

The power up signal generator may include a voltage divider configured to distribute the second power voltage, a switching unit configured to select a divided voltage corresponding to the target level from the voltage divider in response to the control signal, and using the selected divided voltage. And a voltage detector configured to detect the level of the second power supply voltage and a signal output unit to activate the power-up signal when the second power supply voltage is greater than or equal to the target level.

The semiconductor device including the power-up signal generation circuit according to the present invention is driven by receiving a first power supply voltage, and generates a control signal for varying a target level of the power-up signal with respect to the second power supply voltage in a test mode. A control signal generation unit, a power-up signal generation unit for varying the target level in response to the control signal and activating the power-up signal when the second power supply voltage rises above the target level and programming according to the test result. And a fuse circuit for setting the target level, wherein the first power supply voltage is higher than the second power supply voltage.

According to the present invention, a control signal generation unit for varying a target level of a power-up signal for a low power supply voltage is provided, and the control signal generation unit is driven by being supplied with a high power supply voltage, thereby powering up a signal in one semiconductor device. The test can be performed stably to adjust the target level.

In addition, when the target level intended for the circuit design is changed according to the operating conditions of the semiconductor device or the process state of the transistor used, the target level can be readjusted even in the wafer state where the process operation is completed.

1 is a block diagram of an embodiment of a power-up signal generation circuit according to the present invention;
FIG. 2 is a diagram illustrating in detail the power-up signal generator 103 of FIG. 1.
3 is a view showing a change in a target level according to the distribution voltage selected in FIG.
4A and 4B show waveforms of a power-up signal PWRUP according to a target level determined in FIG.
5 is a block diagram of a semiconductor device including a power-up signal generation circuit according to the present invention.

Hereinafter, the most preferred embodiments of the present invention will be described with reference to the accompanying drawings so that those skilled in the art may easily implement the technical idea of the present invention.

1 is a configuration diagram of an embodiment of a power-up signal generation circuit according to the present invention.

Referring to FIG. 1, the power-up signal generation circuit is driven by being supplied with a first power supply voltage VPP, and a control signal for varying a target level of the power-up signal PWRUP with respect to the second power supply voltage VDD. The target level is varied in response to the control signal generator 101 generating the CTRL <0: N> and the control signal CTRL <0: N>, and the second power supply voltage VDD is above the target level. It includes a power-up signal generator 103 for activating the power-up signal PWRUP when raised.

The semiconductor device using the power-up signal generating circuit according to the present invention is assumed to receive two power supply voltages VPP and VDD, unlike in the prior art. For example, in the case of DRAM, a conventional DDR3 type DRAM receives only one power supply voltage VDD, whereas a DDR4 type DRAM in which the present invention is used is driven by applying two power supply voltages VPP and VDD. . Here, the first power supply voltage VPP has a higher voltage level than the second power supply voltage VDD. In this embodiment, it is assumed that VPP = 1.8V and VDD = 1.2V.

In the initialization process of the semiconductor device, the first and second power supply voltages VPP and VDD are simultaneously applied. Generally, the first power supply voltage VPP is 0 to 1.8V for a predetermined time (about 20 ms or more), and the second power supply is applied. The voltage VDD maintains a constant level after ramping up from 0 to 1.2V. Here, in order to prevent the latch-up phenomenon of the semiconductor device, the first power supply voltage VPP should always be maintained at a level of 0.3V or more higher than the second power supply voltage VDD after a predetermined time after the power is applied. Therefore, the power-up signal of the first power supply voltage VPP is activated before the power-up signal of the second power supply voltage VDD.

Therefore, the control signal generator 101 receiving the first power supply voltage VPP is initialized earlier than the power-up signal generator 103 receiving the second power supply voltage VDD to control signals CTRL <0: N. >), And the power-up signal PWRUP for the second power voltage VDD is activated by the power-up signal generator 103 using the control signals CTRL <0: N>. The level can be changed.

FIG. 2 is a diagram illustrating in detail the power-up signal generator 103 of FIG. 1.

Referring to FIG. 2, the power-up signal generator 103 may supply a voltage in response to the voltage divider 201 for distributing the second power supply voltage VDD and the control signals CTRL <0> to CTRL <N>. A switching unit 203 for selecting a distribution voltage corresponding to a target level from the distribution unit 201, a voltage sensing unit 205 and a second power source for detecting a level of the second power supply voltage VDD using the selected distribution voltage. The signal output unit 207 activates the power-up signal PWRUP when the voltage VDD is equal to or higher than the target level.

The voltage divider 201 includes a plurality of resistors R_0 to R_N + 1 that are connected in series between the second power supply voltage VDD terminal and the sensing node DET to distribute the second power supply voltage VDD. The switching unit 203 includes a plurality of passgates PG_0 to PG_N connected in parallel to the plurality of nodes ND_0 to ND_N between the plurality of resistors R_0 to R_N + 1, respectively. Respectively receive control signals CTRL <0> to CTRL <N>. At this time, the signals CTRLb <0> to CTRLb <N> inverting the control signals CTRL <0> to CTRL <N> are also simultaneously input.

The control signals CTRL <0> to CTRL <N> select a voltage of one node among the plurality of nodes ND_0 to ND_N as a distribution voltage, and transfer the voltage to the voltage sensing unit 205. To this end, only one signal for selecting the distribution voltage among the plurality of control signals CTRL <0> to CTRL <N> is activated as 'high', and the passgate to which the activated control signal is applied is turned on so that The voltage is selected as the divider voltage.

The voltage detector 205 includes an NMOS transistor T1 having a drain-source connection between the sensing node DET and the ground voltage VSS, and gated at a divided voltage selected by an activated control signal. The NMOS transistor T1 is turned on when the input distribution voltage is greater than or equal to the threshold voltage VTh. When the NMOS transistor T1 is turned on, the voltage level of the sensing node DET is lowered.

The signal output unit 207 activates and outputs the power-up signal PWRUP when the voltage of the sensing node DET is lower than a predetermined level. The activated power-up signal PWRUP has a form transitioned to the same level as the external voltage VDD.

3 is a diagram illustrating a change in a target level according to the distribution voltage selected in FIG. 2.

As shown in FIG. 3, both the second power supply voltage VDD and the node voltages V0 to VN increase linearly from the time point at which the second power supply voltage VDD is applied until the normal level is reached. The node voltages V0 to VN represent voltage levels at the nodes ND_0 to ND_N, respectively.

The threshold voltage VTh at which the NMOS transistor T1 of the voltage sensing unit 205 is turned on always has a constant level. Therefore, when the node voltage V0 is selected as the distribution voltage, the power-up target level of the second power supply voltage VDD becomes VTG0, and when the node voltage V1 is selected as the distribution voltage, the target level becomes VTG1. In this way, the target level can be varied from VTG0 to VTGN by selecting one of the plurality of node voltages V0 to VN as the distribution voltage using the control signals CTRL <0> to CTRL <N>.

In addition, the voltage divider 201 may finely adjust the target level by adjusting the number and size of the resistors.

4A and 4B illustrate waveforms of the power-up signal PWRUP according to the target level determined in FIG. 3.

When the target level is VTG0 (FIG. 4A), the power-up signal PWRUP is activated from the time point when the second power supply voltage VDD reaches VTG0 to transition to the same level as the second power supply voltage VDD. Similarly, when the target level is VTG1 (FIG. 4B), the power-up signal PWRUP is activated from the time when the second power supply voltage VDD reaches VTG1, and transitions to the same level as the second power supply voltage VDD.

5 is a configuration diagram of a semiconductor device including a power-up signal generation circuit according to the present invention.

Referring to FIG. 5, the semiconductor device is driven by being supplied with a first power supply voltage VPP and controls a control signal for varying a target level of the power-up signal PWRUP with respect to the second power supply voltage VDD in a test mode. The control signal generator 101 generating CTRL <0: N> varies the target level in response to the control signal CTRL <0: N>, and the second power supply voltage VDD rises above the target level. And a fuse circuit 501 programmed according to a test result and a fuse circuit 501 for setting a target level.

The control signal generator 101 and the fuse circuit 501 may be implemented to operate under the control of the test signal TM_EN as follows.

First, when the test signal TM_EN becomes 'high' in the test mode, the control signal generator 101 generates a plurality of control signals CTRL <0: N>, and accordingly, the power-up signal generator A test for varying the target level of 103 is performed. The test result TM_RST is transmitted to the fuse circuit 501, and the test result TM_RES may include information about a target level set through the test.

Subsequently, in the normal mode, the test signal TM_EN becomes 'low' and the fuse circuit 501 operates. The fuse circuit 501 performs fuse cutting according to the test result TM_RST, and accordingly, the control signal generator 101 controls the control signal CTRL <0: N> corresponding to the fixed target level. Create a. That is, the fuse circuit 501 may be programmed according to the test result TM_RST to set a desired target level.

As described above, in the present invention, in a semiconductor device receiving two power supply voltages, a control signal generation unit for varying a target level of a power-up signal for a low power supply voltage is provided, and the control signal generation unit applies a high power supply voltage. A power up signal generation circuit and a semiconductor device including the same have been proposed in which a target level can be adjusted more efficiently and stably in one semiconductor device by being driven and driven. As a result, when the target level intended for circuit design is changed according to an operating condition of a semiconductor device or a process state of a transistor used, the target level may be readjusted even in a wafer state in which a process operation is completed.

The present invention described above is capable of various substitutions, modifications, and changes without departing from the spirit of the present invention for those skilled in the art to which the present invention pertains. It is not limited by.

Claims (12)

A control signal generator which is driven by receiving a first power supply voltage and generates a control signal for varying a target level of a power-up signal with respect to the second power supply voltage; And
A power-up signal generator that varies the target level in response to the control signal and activates the power-up signal when the second power supply voltage rises above the target level;
Including,
The first power supply voltage is higher than the second power supply voltage.
Power up signal generation circuit.
The method of claim 1,
The power up signal generator
A voltage divider for distributing the second power voltage;
A switching unit selecting a division voltage corresponding to the target level from the voltage division unit in response to the control signal;
A voltage detector configured to sense a level of the second power voltage using the selected divided voltage; And
And a signal output unit activating the power-up signal when the second power supply voltage is greater than or equal to the target level.
Power up signal generation circuit.
The method of claim 2,
The voltage divider
A plurality of resistors connected in series between the second supply voltage terminal and the sensing node;
Power up signal generation circuit.
The method of claim 3, wherein
The switching unit
A plurality of passgates connected in parallel between the plurality of resistors,
The plurality of passgates are turned on / off by the control signal to transfer the divided voltages to the voltage detector.
Power up signal generation circuit.
The method of claim 3, wherein
The voltage detector
A drain-source connection between the sensing node and a ground voltage terminal, the NMOS transistor receiving a gate input of the divided voltage;
Power up signal generation circuit.
6. The method of claim 5,
The signal output unit
When the voltage of the sensing node is less than a predetermined value to activate the power-up signal
Power up signal generation circuit.
A control signal generator configured to be driven by receiving a first power supply voltage and to generate a control signal for varying a target level of a power-up signal with respect to the second power supply voltage in a test mode;
A power-up signal generator for varying the target level in response to the control signal and activating the power-up signal when the second power supply voltage rises above the target level; And
Fuse circuit programmed according to the test result to set the target level
Including,
The first power supply voltage is higher than the second power supply voltage.
Semiconductor device.
The method of claim 7, wherein
The power up signal generator
A voltage divider for distributing the second power voltage;
A switching unit selecting a division voltage corresponding to the target level from the voltage division unit in response to the control signal;
A voltage detector configured to sense a level of the second power voltage using the selected divided voltage; And
And a signal output unit activating the power-up signal when the second power supply voltage is greater than or equal to the target level.
Semiconductor device.
The method of claim 8,
The voltage divider
A plurality of resistors connected in series between the second supply voltage terminal and the sensing node;
Semiconductor device.
The method of claim 9,
The switching unit
A plurality of passgates connected in parallel between the plurality of resistors,
The plurality of passgates are turned on / off by the control signal to transfer the divided voltages to the voltage detector.
Semiconductor device.
The method of claim 9,
The voltage detector
A drain-source connection between the sensing node and a ground voltage terminal, the NMOS transistor receiving a gate input of the divided voltage;
Semiconductor device.
12. The method of claim 11,
The signal output unit
When the voltage of the sensing node is less than a predetermined value to activate the power-up signal
Semiconductor device.
KR1020100103890A 2010-10-25 2010-10-25 Power-up signal generating circuit and semiconductor device including the same KR20120042273A (en)

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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR20170069510A (en) * 2015-12-11 2017-06-21 에스케이하이닉스 주식회사 Circuit for setting test mode and semiconductor device including the same

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR20170069510A (en) * 2015-12-11 2017-06-21 에스케이하이닉스 주식회사 Circuit for setting test mode and semiconductor device including the same

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