KR100650760B1 - Method of manufacturing transistor of memory device - Google Patents

Abstract

A method for manufacturing a transistor of a memory device is provided to obtain high driving current and long refresh time by forming the transistor with protuberance and recess structure. A trench(32) is formed at a field region of a substrate(31). A sidewall oxide layer(33), a linear nitride layer(34), a linear oxide layer(35) and a gap-fill oxide layer(36) are sequentially formed in the trench, thereby forming an isolation layer(37). The exposed sidewall oxide layer, the linear nitride layer and the linear oxide layer are removed by using a hard mask pattern. A groove is formed by recessing the exposed active region to shallow depth, wherein the bottom of the groove is protruded. The hard mask pattern is eliminated. A gate(45) is then formed on the protrudent groove. A source/drain region is formed in the substrate.

Description

Method of manufacturing transistor of memory device

1 is a perspective view showing a conventional fin transistor.

2 is a cross-sectional view showing a conventional recessed transistor.

3A to 3F are cross-sectional views of processes for describing a method of manufacturing a transistor of a memory device according to the present invention.

Explanation of symbols on the main parts of the drawings

31 semiconductor substrate 32 trench

33 sidewall oxide film 34 linear nitride film

35: linear oxide film 36: buried oxide film

37: device isolation layer 38: buffer oxide film

39: first polysilicon film 40: groove

41 gate oxide film 42 second polysilicon film

43 tungsten silicide film 44 hard mask nitride film

45: gate S / D: source / drain area

The present invention relates to a method of manufacturing a memory device, and more particularly, to a transistor manufacturing method that can implement a high speed and low power memory device.

As the design rule of the memory device is drastically reduced, correspondingly, the channel length and width of the transistor become very short while the doping concentration of the junction region increases, so that the junction leakage is increased due to the increase of the electric field. The current increased. As a result, it is difficult to obtain a threshold voltage value required by a high density device with a conventional two-dimensional planar channel structure, and reaches a limit in improving refresh characteristics. Recently, researches on the implementation of transistors having a three-dimensional channel structure capable of extending the channel length have been actively conducted.

As one of the research results, a fin transistor having a three-dimensional channel structure has recently been proposed in the field of logic devices.

As shown in FIG. 1, the protruding transistor protrudes the active region 2 of the semiconductor substrate 1 and forms a gate 5 so as to surround the protruding active region. Channels are designed to be simultaneously formed on three surfaces of the enclosed active region 2.

Such protruding transistors can obtain excellent current driving characteristics through instantaneous increase in current amount, and also have excellent on-off characteristics, enabling high-speed devices, and having low back bias dependency. Desired device characteristics can be obtained even at voltage.

In addition, as another result of the research, a recessed transistor has recently been proposed in the field of memory devices.

As shown in FIG. 2, the recessed transistor has a structure in which the gate forming portion of the substrate active region is recessed by a predetermined depth, and the gate 5 is formed on the recessed active region portion.

Such a recessed transistor can improve the short channel effect by increasing the channel length by the recess depth, and can also improve the refresh characteristics.

In FIG. 1 and FIG. 2, reference numeral 3 denotes an isolation layer, and 4 denotes a gate insulating layer.

However, the protruding transistor has a high driving current, so the response speed of the device is very fast, but the refresh characteristic is not good because the data retention time is short.

On the other hand, the recessed transistor is capable of low power driving and has a very good advantage in terms of refresh, but has a disadvantage of low driving current. In particular, the recessed transistor inevitably generates a horn due to the inclined side profile of the device isolation layer when the substrate active region is etched to form the recessed transistor. By concentrating the electric field, it is difficult to expect normal operation, and there is a fatal disadvantage of failing to secure reliability.

Accordingly, the present invention has been made to solve the conventional problems as described above, while improving the refresh characteristics, which is a disadvantage of the projection transistor, while improving the driving current, which is a disadvantage of the recess transistor, and prevents the occurrence of horns. It is an object of the present invention to provide a method for manufacturing a transistor of a memory device.

In addition, another object of the present invention is to provide a method of manufacturing a transistor of a memory device capable of realizing a high speed and a low power memory device by simultaneously having the advantages of the protrusion transistor and the recess transistor.

In order to achieve the above object, the present invention, forming a trench in the field region of the semiconductor substrate; Forming a device isolation layer defining an active region by sequentially forming a sidewall oxide film, a linear nitride film, a linear oxide film, and a buried oxide film in the trench; Forming a hard mask film on the entire surface of the substrate to expose a portion of the active region where a gate is to be formed, and to expose a sidewall oxide film, a linear nitride film, and a linear oxide film formed on the trench sidewalls of the device isolation film; Using the hard mask layer as an etch barrier to remove sidewall oxide, linear nitride and linear oxide on the exposed sidewalls of the trench; Recessing the exposed portion of the active region to a depth shallower than a trench to form a groove and to protrude the bottom of the groove; Removing the hard mask layer; Forming a gate on the bottom protruding groove; And forming a source / drain region in the surface of the substrate on both sides of the gate.

Here, the trench is formed to a depth of 1500 to 5000 kPa, and the groove is formed to a depth of 1000 to 4000 kPa.

Sidewall oxide, linear nitride, and linear oxide removal of the exposed trench sidewalls are simultaneously performed by dry etching, and the dry etching is performed by flowing a gas of CxFx / O2 / Ar in a MERIE device, and having a pressure of 10-30 mTorr and a pressure of 1000-3000 W. It is performed under the condition of applying a power to form a high density plasma. In addition, the sidewall oxide film, the linear nitride film, and the linear oxide film of the exposed trench sidewalls may be removed to the bottom of the trench or may be shallower than the bottom of the trench.

(Example)

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings.

Briefly describing the technical principle of the present invention, the present invention manufactures a transistor having a complex structure having both the protruding transistor structure and the recessed transistor structure. In addition, the present invention, in recessing the portion of the substrate active region in which the gate is to be formed, exposes the horn generation region through a mask process, and then removes the sidewall oxide film, the linear nitride film and the linear oxide film from the exposed area, Subsequently, the recess is performed.

In this way, the present invention implements a transistor having both the advantages of the protruding transistor and the advantages of the recessed transistor, thereby realizing high speed and low power memory devices through high driving current and long refresh time. In addition, the present invention can eliminate horns that are a problem in manufacturing recessed transistors, thereby ensuring device reliability.

In detail, FIGS. 3A to 3F are cross-sectional views illustrating processes for manufacturing a transistor of a memory device according to the present invention. In each figure, the left figure shows the cross section along the longitudinal direction of the active area, and the right figure shows the cross section along the width direction of the active area.

Referring to FIG. 3A, the trench 32 is formed by etching the field region of the semiconductor substrate 31 to a depth of 1500 to 5000 GPa. Then, a sidewall oxide layer 33, a liner nitride 34, and a liner oxide 35 are sequentially formed on the surface of the trench 32 in a thickness of 30 to 100 μm, respectively. In order to fill the trench 32 on the linear oxide layer 35, the buried oxide layer 36 is deposited by, for example, HDP-CVD. Then, the buried oxide film 36, the linear oxide film 35, the linear nitride film 34, and the sidewall oxide film 33 are chemical mechanical polished (CMP) to form a trench type device isolation film 37 defining an active region. do.

Although not shown and described in detail, the device isolation layer 37 is formed by a well-known shallow trench isolation (STI) process. Therefore, the etching of the substrate field region is performed by using a pad nitride film formed to expose the field region on the substrate as an etching mask, and after removing the pad nitride film after performing the CMP process on the stacked layer, an element isolation film. It can be understood that (37) is formed.

Referring to FIG. 3B, a buffer oxide film 38 is formed on the entire surface of the semiconductor substrate 31 including the device isolation film 37 at a thickness of 100 to 500 microseconds, and then, on the buffer oxide film 38, The thickness of the first polysilicon film 39 for hard mask is formed. Then, the first polysilicon film 39 and the buffer oxide film 38 are patterned to expose the portion of the active region where the gate is to be formed.

At this time, the patterning of the first polysilicon film 39 and the buffer oxide film 38 is formed in a dot shape exposing only the active region, not in the form of a line. In particular, as shown in the right figure, the width direction of the active region The sidewall oxide film 33, the linear nitride film 34, and the linear oxide film 35 formed on the sidewalls of the trench 32 in the device isolation film 37 are exposed together.

Referring to FIG. 3C, portions of the sidewall oxide layer 33, the linear nitride layer 34, and the linear oxide layer 35 of the exposed sidewalls of the trench 32 are removed using the patterned first polysilicon layer 39 as an etch barrier. do. Here, the sidewall oxide layer 33, the linear nitride layer 34, and the linear oxide layer 35 flow CxFx / O2 / Ar gas in a MERIE (Magnetric Enhanced Reactive Ion Etching) device, and have a pressure of 10 to 30 mTorr and a pressure of 1000 to 3000 W. Etching of the sidewall oxide layer 33, the linear nitride layer 34, and the linear oxide layer 35 is performed at the same time by a dry etching method of forming a high-density plasma by applying a power of. It is preferable to proceed to the bottom of 32, and it is also possible to proceed to a shallower depth.

Meanwhile, when etching the sidewall oxide layer 33, the linear nitride layer 34, and the linear oxide layer 35, a part of the exposed substrate active region portion where the gate is to be formed may be etched together, which may be subsequently etched. Since it is an area, it does not matter.

Referring to FIG. 3D, the patterned first polysilicon film 39 is used as an etch barrier to recess the exposed portion of the substrate active region to form the groove 40. At this time, the depth of the recess, that is, the depth of the groove 40 is preferably shallower than the depth of the trench, for example, about 1000 ~ 4000Å.

Here, since the sidewall oxide film 33, the linear nitride film 34 and the linear oxide film 35 are removed before the recess is performed on the portion of the substrate active region where the gate is to be formed, Horn is not generated. Therefore, the present invention prevents horn generation during substrate recess, thereby ensuring the reliability of the manufactured device.

In addition, as shown in the figure on the right, since the present invention makes the depth of the groove 40 shallower than the depth of the trench 42, a structure in which the active region protrudes from the bottom of the groove 40 is obtained.

Referring to FIG. 3E, the first polysilicon film and the buffer oxide film are sequentially removed according to a known method. Then, a gate oxide film 41 is formed on the substrate resultant, especially on the surface of the substrate active region including the grooves 40 to a thickness of 30 to 100 microseconds. Here, the gate oxide film 41 is formed by depositing by a CVD method or by oxidizing a substrate. Oxidation of the substrate proceeds by supplying O2 and N2 gas at a temperature of 800 to 900 ° C.

Next, the second polysilicon film 42 for the gate is deposited on the gate oxide film 41 to a thickness that completely fills the grooves 40, for example, 500 to 2000 microns, and then an etch back or CMP process is performed. Planarizes its surface through.

Referring to FIG. 3F, a metal silicide film, for example, a tungsten silicide film 43, is deposited on the second polysilicon film 42 for the gate to have a thickness of 1000 to 2000 Å. Then, a nitride layer 44 for hard mask is deposited on the tungsten silicide layer 44 to a thickness of 1000 to 3000 GPa.

Next, after the hard mask nitride film 44 is patterned according to a known process, the tungsten silicide film 43 and the second polysilicon under the patterned hard mask nitride film 44 are used as an etch barrier. The film 42 and the gate oxide film 41 are etched to form a gate 45 having a recess structure.

Then, the source / drain regions S and D are formed in the substrate surfaces on both sides of the gate 45 to complete the manufacture of the transistor of the memory device according to the present invention.

Here, the transistor of the present invention has a recessed transistor structure in the longitudinal direction of the active region as shown in the left figure, whereas, as shown in the right figure, in relation to the protrusion of the active region in the width direction of the active region. It has a protruding transistor structure.

Therefore, since the transistor of the present invention has both the protrusion transistor structure and the recess transistor structure, low power driving is possible and excellent refresh characteristics, and high driving current is possible due to the high driving current. In addition, since the horn is not generated in the transistor of the present invention, the reliability thereof can be secured.

As mentioned above, although the present invention has been illustrated and described with reference to specific embodiments, the present invention is not limited thereto, and the following claims are not limited to the scope of the present invention without departing from the spirit and scope of the present invention. It can be easily understood by those skilled in the art that can be modified and modified.

As described above, the present invention can implement a memory device capable of low power and high speed operation by having a high driving current and a very long refresh time by forming a transistor having both a protrusion structure and a recess structure.

In addition, the present invention can secure the reliability of the manufactured memory device by preventing the generation of horns when forming the recessed transistor structure.

Claims (19)

Forming a trench in the field region of the semiconductor substrate; Forming a device isolation layer defining an active region by sequentially forming a sidewall oxide film, a linear nitride film, a linear oxide film, and a buried oxide film in the trench; Forming a hard mask film on the entire surface of the substrate to expose a portion of the active region where a gate is to be formed, and to expose a sidewall oxide film, a linear nitride film, and a linear oxide film formed on the trench sidewalls of the device isolation film; Using the hard mask layer as an etch barrier to remove sidewall oxide, linear nitride and linear oxide on the exposed sidewalls of the trench; Recessing the exposed portion of the active region to a depth shallower than a trench to form a groove and to protrude the bottom of the groove; Removing the hard mask layer; Forming a gate on the bottom protruding groove; And And forming a source / drain region in the surface of the substrate on both sides of the gate. The method of claim 1, And the trench is formed to a depth of 1500 to 5000 microns. The method of claim 1, And the sidewall oxide film, the linear nitride film, and the linear oxide film are formed to have a thickness of 30 to 100 microseconds, respectively. The method of claim 1, And the hard mask layer is formed of a laminated layer of an oxide layer and a polysilicon layer. The method of claim 4, wherein And the oxide film is formed to a thickness of 100 to 500 mW. 5. The method of claim 4, wherein the polysilicon film is formed to a thickness of 1000 to 5000 GPa. The method of claim 1, Removing the sidewall oxide layer, the linear nitride layer, and the linear oxide layer of the exposed trench sidewalls at the same time by dry etching. The method of claim 7, wherein The dry etching is performed in a condition of forming a high-density plasma by flowing a gas of CxFx / O2 / Ar in a MERIE device and applying a pressure of 10-30 mTorr and a power of 1000-3000 W. . The method of claim 1, And removing the sidewall oxide layer, the linear nitride layer, and the linear oxide layer of the exposed trench sidewalls to the bottom of the trench. The method of claim 1, And removing sidewall oxides, linear nitrides, and linear oxides on the exposed sidewalls of the trenches at a shallower depth than the bottom of the trench. The method of claim 1, And the groove is formed to a depth of 1000 to 4000 micrometers. The method of claim 1, Forming the gate, Forming a gate oxide film on the substrate active region including the groove; Sequentially forming a gate conductive film and a gate hard mask film on the gate oxide film to fill the grooves; And And etching the gate hard mask layer, the gate conductive layer, and the gate oxide layer. 2. The method of claim 12, And the gate oxide film is formed to a thickness of 30 to 100 kHz. The method of claim 12, And said gate conductive film is formed of a laminated film of a polysilicon film and a metal silicide film. The method of claim 14, Wherein said polysilicon film is formed to a thickness of 500 to 2000 kHz. The method of claim 14, The metal silicide film is a tungsten silicide film, characterized in that the transistor manufacturing method of the memory device. The method of claim 16, And the tungsten silicide film is formed to a thickness of 1000 to 2000 micrometers. The method of claim 12, And said gate hard mask film is a nitride film. The method of claim 18, And the nitride film is formed to a thickness of 1000 to 3000 mW.

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