KR100650246B1 - Apparatus for increasing in operation speed of handset - Google Patents

Abstract

1. TECHNICAL FIELD OF THE INVENTION

The present invention relates to an apparatus for increasing the operating speed of a portable terminal.

2. The technical problem to be solved by the invention

The present invention provides an oscillation signal having a more diverse frequency by using a CODEC PLL oscillation signal as a main PLL oscillation signal, thereby providing an operation speed increasing apparatus of a portable terminal that can increase the operation speed of the terminal. Its purpose is to.

3. Summary of Solution to Invention

The present invention provides an apparatus for increasing the operating speed of a portable terminal, comprising: a basic clock signal generator 210 for generating a basic clock signal having a basic frequency; A CODEC clock signal generator 220 generating a CODEC clock signal having a frequency different from that of the fundamental frequency; Receives a basic clock signal from the basic clock signal generator 210, receives a CODEC clock signal from the CODEC clock signal generator 220, and one of the basic clock signal and the CODEC clock signal according to a clock selection signal A selection unit 230 for transmitting a signal; A divider 240 for dividing the signal received from the selector 230 and outputting the divided signal; And a main processor configured to be driven based on a clock signal input from the divider 240, to generate the clock select signal according to a required speed of a driving operation, and to output the clock select signal to the selector 230. 250).

4. Important uses of the invention

The present invention is used in a portable terminal.

Dispensing, Multiplication, PLL, CODEC, Terminal

Description

APAPATUS FOR INCREASING IN OPERATION SPEED OF HANDSET}             

1 is a block diagram showing a conventional reference frequency generator,

2 is a block diagram showing an operation speed increase apparatus of a portable terminal according to an embodiment of the present invention;

3 is a block diagram illustrating a basic clock signal generator of FIG. 2;

4 is a block diagram illustrating a CODEC clock signal generator of FIG. 2.

* Explanation of symbols for the main parts of the drawings

210: basic clock signal generator 220: CODEC clock signal generator

230: selection unit 240: dispensing unit

250: main processing unit

The present invention relates to an apparatus for increasing the operating speed of a portable terminal, and more particularly, to an apparatus for increasing the operating speed of a portable terminal for providing an operating clock signal of various frequencies.

1 is a block diagram illustrating a conventional reference frequency generator, which will be described below.

로 분주하여(예를 들면, 19.68 * 5 / 3 = 32.8MHz) 분주 신호(

TXCO)를 생성하고, 생성된 분주 신호(

TXCO)를 MSM(Mobile Station Modem)으로 출력하는 역할을 한다.The oscillation circuit 110 generates an oscillation signal having a fundamental frequency (for example, 19.68 MHz) and outputs the generated oscillation signal to the 5 multiplication circuit 120. In addition, the multiplication circuit 120 multiplies the frequency of the oscillation signal output from the oscillation circuit 110 by 5 times (for example, 19.68 * 5 = 98.4 MHz) to generate a multiplication signal, and generates the multiplied signal. It serves to output to the three division circuit 130. On the other hand, the three-dividing circuit 130 adjusts the frequency of the multiplication signal output from the five multiplication circuit 120.

Divided by (e.g. 19.68 * 5/3 = 32.8 MHz)

TXCO), and the generated divided signal (

TXCO) is outputted to MSM (Mobile Station Modem).

TXCO)보다 높은 주파수의 클럭 신호를 가지고 MSM을 동작시키는 경우가 없는데, 이는 MSM 내 메인 프로세서 및 복수개의 서브 프로세서가 필요로 하는 적정한 수준의 클럭 신호를 공급하기 위해 5 체배, 3분주를 적용하는 것이 주요 권고 사항이기 때문이다.However, according to the conventional technique described above, the divided signal (

There is no case in which the MSM is operated with a clock signal of higher frequency than TXCO). It is recommended to apply 5 multiplications and 3 divisions to supply an appropriate level of clock signal required by the main processor and a plurality of subprocessors in the MSM. This is a major recommendation.

However, due to the demands of terminal users and mobile communication service providers, applications for additional services have been added to the terminal, and thus the demand for fast operation speed has increased.However, the frequency of the clock signal has increased due to the setting as recommended. There is a problem that the operation speed of the terminal does not meet the needs of the terminal user and the mobile communication service provider.

The present invention has been proposed to solve the above problems, by using a CODEC PLL oscillation signal as the main PLL oscillation signal, to provide an oscillation signal having a more diverse frequency, thereby increasing the operating speed of the terminal An object of the present invention is to provide an operation speed increasing device of a portable terminal.

Other objects and advantages of the present invention can be understood by the following description, and will be more clearly understood by the embodiments of the present invention. In addition, it will be readily appreciated that the objects and advantages of the present invention may be realized by the means and combinations thereof indicated in the claims.

In accordance with one aspect of the present invention, an apparatus for increasing an operation speed of a portable terminal includes: a basic clock signal generator 210 generating a basic clock signal having a fundamental frequency; A CODEC clock signal generator 220 generating a CODEC clock signal having a frequency different from that of the fundamental frequency; Receives a basic clock signal from the basic clock signal generator 210, receives a CODEC clock signal from the CODEC clock signal generator 220, and one of the basic clock signal and the CODEC clock signal according to a clock selection signal A selection unit 230 for transmitting a signal; A divider 240 for dividing the signal received from the selector 230 and outputting the divided signal; And a main processor configured to be driven based on a clock signal input from the divider 240, to generate the clock select signal according to a required speed of a driving operation, and to output the clock select signal to the selector 230. 250).

The above objects, features and advantages will become more apparent from the following detailed description taken in conjunction with the accompanying drawings, whereby those skilled in the art may easily implement the technical idea of the present invention. There will be. In addition, in describing the present invention, when it is determined that the detailed description of the known technology related to the present invention may unnecessarily obscure the gist of the present invention, the detailed description thereof will be omitted. Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings.

2 is a block diagram illustrating an apparatus for increasing an operation speed of a portable terminal according to an exemplary embodiment of the present invention, wherein a basic clock signal generator 210, a CODEC clock signal generator 220, a selector 230, and a divider are provided. And a main processor 250.

The basic clock signal generator 210 generates a basic clock signal having a basic frequency and outputs the generated basic clock signal to the selector 230. Here, the basic clock signal may be 98.4 MHz according to the MSM driving recommendation, but is not limited thereto.

In addition, the CODEC clock signal generator 220 generates a CODEC clock signal having a frequency different from the fundamental frequency and outputs the generated CODEC clock signal to the selector 230. Here, the CODEC clock signal may be 83.968 MHz according to a CODEC driving recommendation, but is not limited thereto.

On the other hand, the selector 230 receives a basic clock signal from the basic clock signal generator 210, a CODEC clock signal from the CODEC clock signal generator 220, and a clock from the main processor 250. It receives a selection signal, and selects one of the basic clock signal and the CODEC clock signal according to the clock selection signal and transfers it to the division unit 240.

In addition, the divider 240 receives one of the basic clock signal and the CODEC clock signal from the selector 230, divides the received signal, and divides the divided signal into the main processor 250. It plays a role of outputting. Herein, the dispensing unit 240 may perform the dispensing operation in a dispensing mode selected from 1, 2, 3, 4, 8, and 16 divisions, but is not limited thereto.

On the other hand, the main processor 250 is driven based on the clock signal input from the dividing unit 240, generates the clock selection signal according to the required speed of the drive operation, and the clock selection signal to the selection unit ( 230) to output. Here, the main processor 250 determines whether the driving operation requires a high speed, but an example of the operation requiring a high speed includes a booting operation and the like.

3 is a block diagram illustrating the basic clock signal generation unit 210 of FIG. 2.

The main oscillator 311 mounted in the basic clock signal generator 210 generates a preceding clock signal that is the basis of the basic clock signal and the CODEC clock signal and divides the generated first clock signal into a first divider. Output to 312. In this case, the preceding clock signal may be 19.68 MHz, but is not limited thereto.

In addition, the first divider 312 mounted in the basic clock signal generator 210 receives the preceding clock signal from the main oscillator 311 and controls a control signal of the main processor 250 (not shown). Divides the preceding clock signal and outputs the divided signal to the first selector 314. Here, the first divider 312 may output a divided signal of 19.68 MHz by performing one division operation according to the MSM driving recommendation, but is not limited thereto.

Meanwhile, the sleep oscillator 313 mounted in the basic clock signal generator 210 generates a sleep clock signal for driving a sleep mode of a portable terminal and converts the generated sleep clock signal into a first selector ( 314).

In addition, the first selector 314 mounted in the basic clock signal generator 210 receives a signal divided from the first divider 312 and receives the sleep clock signal from the sleep oscillator 313. It receives an input, selects one of the divided signal and the sleep clock signal by the selection signal (not shown) of the main processor 250 to output to the base clock PLL (315) and the second selector (316) Play a role. Here, the selection signal of the main processor 250 is set to a second logic step High in the case of the sleep mode so that the sleep clock signal is selected, and in the terminal operation mode except the sleep mode, the first logic step ( Low) to allow the divided signal to be selected.

On the other hand, the basic clock PLL (Phase Locked Loop) 315 mounted in the basic clock signal generator 210 receives a multiplication signal from the main processor 250 and is input from the first selector 314. The signal is multiplied according to the multiplication number (e.g., 5) set by the multiplying signal, and the second selector is stabilized through the phase locked loop process after the multiplied signal (e.g., 19.68 * 5 = 98.4 MHz) It serves to output to (316). Here, the multiplication signal from the main processor 250 is generally 5 by the MSM driving recommendation, but may be 4 when a fast driving speed such as a booting operation is required, but is not limited thereto.

In addition, the second selector 316 mounted in the base clock signal generator 210 receives a signal multiplied by the base clock PLL 315, and receives a signal selected from the first selector 314. And selecting one of the multiplied signal and the selected signal by the selection signal (not shown) of the main processor 250 and outputting the selected signal to the second divider 317 and the third selector 318. do. Here, when the multiplication operation is not necessary, the selection signal of the main processor 250 is set to the first logic step (Low) so that the output signal of the first selector 314 is transmitted as it is, and the multiplication operation is required. In this case, the second logic step (High) is set so that the multiplied signal is selected.

Meanwhile, the second divider 317 mounted in the basic clock signal generator 210 receives a signal selected from the second selector 316 and controls a control signal of the main processor 250 (not shown). And divides the selected signal, and outputs the divided signal to the third selector 318. Here, the first divider 312 may output divided clock signals applied to various subprocessors in the MSM by performing a two-division or four-division operation according to the MSM driving recommendation, but is not limited thereto.

In addition, the third selector 318 mounted in the basic clock signal generator 210 receives a signal divided from the second divider 317 and inputs a signal selected from the second selector 316. And selects one of the divided signal and the selected signal by the selection signal (not shown) of the main processor 250 and outputs the selected signal to the selection unit 230. In this case, the selection signal of the main processor 250 is set to a second logic step High when an undivided signal is required as an ARM clock signal of the main processor of the MSM. The output signal is transmitted as it is, and if a divided signal is needed, it is set to a first logic step (Low) so that the divided signal is selected. In addition, the divided signal is not limited to the input to the third selector 318 and may be input to another component and used as a divided signal for operating the subprocessor of the MSM.

FIG. 4 is a block diagram illustrating the CODEC clock signal generator 220 of FIG. 2.

The third divider 421 mounted in the CODEC clock signal generator 220 receives the preceding clock signal from the main oscillator 311 and controls a control signal of the main processor 250 (not shown). By dividing the preceding clock signal by the output signal, and outputs the divided signal to the fourth selector 423. Here, the third divider 421 may output a divided signal of 19.68 / 12 = 1.312 MHz by performing a 12-division operation according to a CODEC driving recommendation, but is not limited thereto.

In addition, the sleep oscillator 422 mounted in the CODEC clock signal generator 220 generates a sleep clock signal for driving a sleep mode of the portable terminal and converts the generated sleep clock signal into a fourth selector ( 423 and the fifth selector 425.

On the other hand, the fourth selector 423 mounted in the CODEC clock signal generator 220 receives a signal divided by the third divider 421 and receives the sleep clock signal from the sleep oscillator 422. It receives an input, and selects one of the divided signal and the sleep clock signal by the selection signal (not shown) of the main processor 250 to output to the CODEC clock PLL (424) and the fifth selector (425) Play a role. Here, the selection signal of the main processor 250 is set to a second logic step High in the case of the sleep mode so that the sleep clock signal is selected, and in the terminal operation mode except the sleep mode, the first logic step ( Low) to allow the divided signal to be selected.

In addition, the CODEC clock PLL 424 mounted in the CODEC clock signal generator 220 receives a multiplication signal (not shown) and a division signal (not shown) from the main processor 250, 4 multiplies the signal input from the selector 423 according to the multiplication number (e.g., 128) set by the multiplying signal, and multiplies the multiplied signal (e.g., 1.312 * 128 = 167.936 MHz). It divides according to the number of divisions (for example, 2) to be set, and stabilizes the divided signal (167.936 / 2 = 83.968 MHz) through a phase locked loop process, and outputs it to the fifth selector 425. Here, the divided signal from the main processing unit 250 is generally 2 according to the CODEC driving recommendation, but is not limited thereto. The multiplied signal may be divided by a predetermined number of divisions (for example, 41). It is recommended that the divided signal be about 4.096 MHz (167.936 / 41 = 4.096 MHz).

Meanwhile, the fifth selector 425 mounted in the CODEC clock signal generator 220 receives a plurality of divided signals from the CODEC clock PLL 424 and receives a sleep clock signal from the sleep oscillator 422. It receives an input and selects one of the divided signal and the sleep clock signal by the selection signal (not shown) of the main processor 250 and outputs the selected signal to the selection unit 230. Here, the selection signal of the main processor 250 is set to 0 (00) in the case of the sleep mode, so that the output signal of the slip oscillator 422 is transmitted as it is, and 1 (01) when the division operation is necessary. Or 2 (10) to select the divided signal.

Referring to the operation of the operation speed increase device of the portable terminal of the present invention described above are as follows.

First, in order to increase the frequency of the clock signal input to the main processor 250 during the booting operation, the frequency division number of the divider 240 may be switched from 3 to 2. At this time, if the basic clock signal (98.4MHz) of the basic clock signal generator 210 is used as it is, the output signal of the division unit 240 has a frequency of 49.2MHz (98.4 / 2 = 49.2MHz), The frequency size tends to be too large for the processing unit 250 to operate.

Therefore, during the booting operation, the selector 230 selects the CODEC clock signal (83.968 MHz) and transmits it to the divider 240 so that the output signal of the divider 240 is 41.984 MHz (83.968 / 2 = 41.984 MHz). It is desirable to lower the frequency magnitude.

More preferably, the frequency magnitude of the CODEC clock signal may be reduced to 77.9 MHz by adjusting the multiplication number and the division number of the CODEC clock PLL 424, but the present invention is not limited thereto.

In addition, the frequency division of the clock signal input to the main processor 250 is reduced by lowering the multiplication number of the basic clock PLL (Phase Locked Loop) 315 from 5 to 4 while the frequency division of the division 240 is fixed. You can also bring it down.

The present invention described above is capable of various substitutions, modifications, and changes without departing from the technical spirit of the present invention for those skilled in the art to which the present invention pertains. It is not limited by the drawings.

The present invention as described above, by using the CODEC PLL oscillation signal as the main PLL oscillation signal, there is an advantage that can provide an oscillation signal having a more diverse frequency, thereby increasing the operating speed of the terminal.

Claims (5)

In the device for increasing the operating speed of a portable terminal, A base clock signal generator 210 generating a base clock signal having a base frequency; A CODEC clock signal generator 220 generating a CODEC clock signal having a frequency different from that of the fundamental frequency; Receives a basic clock signal from the basic clock signal generator 210, receives a CODEC clock signal from the CODEC clock signal generator 220, and one of the basic clock signal and the CODEC clock signal according to a clock selection signal A selection unit 230 for transmitting a signal; A divider 240 for dividing the signal received from the selector 230 and outputting the divided signal; And The main processor 250 is driven based on the clock signal input from the division unit 240, generates the clock selection signal according to a required speed of the driving operation, and outputs the clock selection signal to the selection unit 230. Device for increasing the operation speed of a portable terminal comprising a). The method of claim 1, The basic clock signal generator 210, A main oscillator (311) for generating a preceding clock signal on which the basic clock signal is based; And The multiplication signal generated according to the required speed of the driving operation is input from the main processor 250, the main clock signal is received from the main oscillator 311, and the base clock signal according to the multiplication signal is generated. And a base clock PLL (315) for stabilizing the base clock signal through a loop operation. The method of claim 1, The main processor (250), the operation speed increasing apparatus of the portable terminal, characterized in that for changing the number of division of the dispensing unit 240 according to the required speed of the drive operation. The method of claim 3, The main processor (250), the operation speed increasing apparatus of the portable terminal, characterized in that for reducing the number of divisions of the division unit 240 as outputting the clock selection signal for selecting the CODEC clock signal. The method of claim 2, The CODEC clock signal generator 220, The main processor 250 receives a CODEC multiplication signal and a CODEC division signal generated according to a required speed of a driving operation, receives the preceding clock signal from the main oscillator 311, and performs a multiplication operation according to the CODEC multiplication signal. And a CODEC clock PLL 424 for generating the CODEC clock signal by performing a division operation according to the CODEC division signal and stabilizing the CODEC clock signal through a phase locked loop operation. Speed increasing device.

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