KR20000027050A - Low power circuit using plurality of clocks - Google Patents

Abstract

PURPOSE: A low power circuit using a plurality of clocks is provided to reduce the power consumption by supplying an appropriate clock source out of a plurality of asynchronous clock sources according to the present operating state of a mobile communication system. CONSTITUTION: A low power circuit using a plurality of clocks comprises: a plurality of oscillation elements; a plurality of selection elements for selecting respective clock sources from the respective oscillation elements by a switching time signal from a micro processor; and a multiplexer for selecting a predetermined clock source out of the respective clock sources from the respective selection elements by a selection signal of the clock source from the micro processor, and outputting the selected clock source to a clock-dividing logic circuit.

Description

Circuit for consuming low power by using multi-clock source

The present invention is to implement a low-power circuit using a plurality of clocks, and more specifically, by selecting a suitable clock source according to the current operating state of the device by using multiple clock sources to reduce the power of the mobile communication device circuit power A low power circuit using a plurality of clocks that can reduce consumption.

At present, the interest and demand for mobile communication has exploded, and the personal communication system (PCS) and cellular phone markets are booming. Accordingly, with the rapid development of related products and technologies, attention has been focused on low power consumption technologies.

In a typical processor, power is saved by using a single clock to save power and dividing the clock when needed. However, this method has a problem in that the pad power and the power and area of the division logic circuit increase because the clock source always oscillates and the division logic circuit operates.

In addition, a mobile communication terminal such as a cellular phone does not always operate at the maximum operating speed, but operates at the maximum operating speed only at the time of a traffic channel or initialization. Most of them are in standby mode. In this case, check the status or detect the external input signal. In this case, the processor speed is not enough to reduce the power by reducing the operating speed. I'm using.

This method has the disadvantage of using a large clock area and pad power consumption by using a single clock source as shown in FIG.

Accordingly, an object of the present invention is to use a plurality of clock sources with different synchronization in a mobile communication device to provide an appropriate clock source according to the current operation state of the device, thereby reducing power consumption and simultaneously eliminating a plurality of clocks. The purpose is to provide a low-power circuit using.

A low power circuit using a plurality of clocks according to the present invention for achieving the above object comprises a plurality of oscillation means and a plurality of oscillation means for respectively selecting a clock source from each oscillation means by a switching time signal from a microprocessor. And a multiplexer which selects a predetermined clock source by means of a clock source selection signal from the microprocessor and outputs each clock source from the respective selection means to a clock division logic circuit.

1 is a block diagram of a processor clock logic using a conventional single clock source,

2 is a low power circuit diagram using a plurality of clocks according to the present invention;

3 is a clock timing diagram of a low power circuit using a plurality of clocks shown in FIG. 2.

* Description of the symbols for the main parts of the drawings *

10,11,12: oscillation means 20,21,22: selection means

30: multiplexer 40: clock division logic

Hereinafter, a low power circuit using a plurality of clocks according to the present invention will be described in detail with reference to the accompanying drawings.

As shown in FIG. 1, the use of a single clock source has a disadvantage of large circuit area and pad power consumption. Therefore, a plurality of clock sources having different frequencies may be used, and a suitable clock source may be used depending on operating status. Consider selecting power to turn off unnecessary clock sources to reduce power consumption.

2 is a low power circuit using a plurality of clocks according to the present invention. As shown, the low power circuit comprises a plurality of oscillation means (10, 11, 12) and clock sources (10 KHz, 1 MHz, 80 MHz) from the respective oscillation means (10, 11, 12). A plurality of selection means 20, 21, 22 respectively selected by the switching time signal Switching_time, and respective clock sources 10KHz, from each of the selection means 20, 21, 22, respectively. 1 MHz and 80 MHz), and a multiplexer 30 for selecting a predetermined clock source by the clock source selection signal from the microprocessor and outputting the predetermined clock source to the clock division logic circuit 40.

The selecting means 20, 21, and 22 are composed of a D flip-flop and a selector, and the plurality of oscillating means 10, 11, and 12 generate clock sources of up to 10 KHz, 1 MHz, and 80 MHz, respectively. It is not limited.

On the other hand, if you are generating a processor clock using multiple clock sources that are out of sync, you should avoid glitches when selecting the clock source. In order to prevent such glitches, as shown in FIG. 2, a flip-flop is added to fix all clock sources at a low level in the clock switch section, and the glitches are not generated when the clock sources are switched.

3 is a clock timing diagram of a low power circuit using a plurality of clocks shown in FIG. 2. As shown in the figure, when the switching_time signal is switched to the high level, the X-tal <A> source used as the current processor clock is changed to the low level at the next negative edge (Fig. 3). 1) clock), a new source X-tal <B> is also changed to the low level at the next negative edge (2 clock shown in Figure 3).

When both clock sources ① and ② maintain the low level, the clock source switching is performed. When the switching time signal switching_time changes to the low level, the next X-tal <B> positive edge X-tal <B> is used as the processor clock. Next, after performing the clock source selection, disable the unused X-tal <A>, and the switching time signal (switching_time) must be maintained at the high level for at least two cycles of the slowest clock among the multiple clock sources. .

In general, the cellular channel operates at the maximum speed, but operates in a standby mode by dividing the clock. In this case, the clock does not use various clock speeds but only one or two set clocks. Will be used. In addition, by dividing the clock into which the maximum operating speed is generated, a considerable amount of power is consumed in the oscillator pad (not shown) and the divider circuit.

In fact, when X-tal is high frequency (40MHz or more), current of several mA flows only on the oscillator pad (not shown). However, when using multiple clock sources and high speed as shown in FIG. When tal <A> is used, and the clock source can be operated at a low speed such as the standby state of the cellular phone, the clock source is changed to X-tal <B> and the X-tal <A> is turned off. Conversely, if high speed is required, such as during a call, turn on X-tal <A>, change the clock source, and turn off X-tal <B>.

On the other hand, the present invention is not limited to the above-described specific embodiments and can be carried out by variously modified and modified within the scope and spirit of the present application.

According to the low-power circuit using a plurality of clocks according to the present invention, the actual drive of 40MHz or more can reduce the current of several mA consumed in the oscillator pad, and also eliminates the need for an additional clock divider circuit.

In addition, the pad driving low speed (10KHz ~ 1MHz) consumes only a few tens of microwatts, which reduces the power consumption considerably compared to the conventional clock control method, and adds a clock divider circuit after the multi-clock source selection logic. Various clock ranges can be provided to the user.

Claims (4)

A plurality of oscillation means, A plurality of selection means for respectively selecting a clock source from each oscillation means by a switching time signal from a microprocessor, A low power circuit using a plurality of clocks comprising a multiplexer which selects a predetermined clock source by a clock source selection signal from the microprocessor and outputs each clock source from each of the selection means to a clock division logic circuit. . The method of claim 1, And said selecting means comprises a D flip-flop and a selector. The method of claim 2, The flip-flop fixes a clock source from the oscillating means at a low level in a clock switching section, and outputs a source clock by a switching time signal from a microprocessor, thereby preventing a plurality of clocks. Low power circuit. The method of claim 1, And said plurality of oscillating means generates clock sources of up to 10 KHz, 1 MHz, and 80 MHz, respectively.