JP4079959B2 - Local oscillation circuit, portable information terminal, and local oscillation control method - Google Patents

Description

  The present invention relates to a local oscillation circuit included in a portable information terminal that performs wireless communication by TDMA (Time Division Multiplex Access) / TDD (Time Division Duplex).

  Conventionally, as a kind of portable information terminal such as PHS (registered trademark) that performs wireless communication by TDMA / TDD, there is a terminal that includes a plurality of local oscillation means in order to increase the speed of wireless communication. In particular, regarding a technique called a so-called dual synthesizer in which two local oscillation means are mounted on a terminal, for example, there is one described in Patent Document 1 described later. In the technology described in Patent Document 1, two PLL (Phase Locked Loop) frequency synthesizer ICs, each connected to a separate 1st local VCO, are prepared in a PHS terminal that transmits and receives 1 slot and 2 slots, and these PLL synthesizers This is to reduce the number of control lines between the IC and the modem IC.

  By the way, it is known that communication by PHS transmits and receives radio waves with a frame period of 5 msec using a frequency of 1.9 GHz band. As shown in FIG. 5, the frame period is divided into eight time slots of first to fourth transmission slots and first to fourth reception slots. In normal communication, for example, a combination of time slots of the same number in transmission and reception is processed, for example, processing of the first reception slot is executed following processing of the first transmission slot.

  In addition, variable slot type communication using a plurality of time slots for communication is known for the purpose of improving the communication speed of PHS. In this slot variable type communication, it is possible to increase the number of slots to be used according to the situation, and at the maximum, all of the first to fourth transmission slots and the first to fourth reception slots can be used for communication. Is possible. In general, in slot variable communication in PHS, communication in the 1.9 GHz band is performed by combining two frequency band signals of 1650 MHz band and 250 MHz band.

  A schematic configuration for realizing the variable slot type communication is shown in FIG. In the configuration shown in FIG. 6, first local oscillators 1A and 1B that output a 1650 MHz band signal and a second local oscillator 2 that outputs a 250 MHz band signal are provided. The first local oscillators 1A and 1B operate alternately by switching the switch, and the frequency of the output signal varies depending on the communication channel. The second local oscillator 2 outputs a signal having a fixed frequency in the 250 MHz band.

  FIG. 7 shows an example of the operation timing of each local oscillator in the slot variable communication. In the illustrated example, for the first local oscillators 1A and 1B that output signals in the 1650 MHz band, the former is assigned a third slot, and the latter is assigned a fourth slot. Also, the third and fourth slots are assigned to the second local oscillator 2 in the 250 MHz band.

  Since each local oscillator requires about 200 to 500 μs from the start of operation until the frequency of the output signal is stabilized, the local oscillation unit is started at the expected timing. As described above, continuous time slots are assigned to the first local oscillators 1A and 1B. Therefore, the first local oscillators 1A and 1B operate so as to compensate for the period required for frequency stabilization.

  In addition, in order to suppress current consumption, the power supply of each local oscillation unit is controlled so as to be in a battery saving state except for the assigned slot. Therefore, for example, in the case of the first local oscillator 1A to which the third slot is assigned, as shown in FIG. 7, when the process is started in the immediately preceding second slot and the processing in the third slot is completed, The battery save state is maintained until activated in the middle of the second slot in the cycle.

  FIG. 8 shows a basic configuration of the local oscillation unit. The local oscillating unit includes an oscillator 3 that oscillates a signal of a reference frequency, a PLLIC 4 that is an integrated circuit in which a PLL circuit is formed, a VCO 5 that is a voltage controlled oscillator, and an output stage amplifier 6 that is provided as necessary. In recent years, two PLL circuits corresponding to two frequency bands (1650 MHz band and 250 MHz band) handled by the local oscillation unit are provided in one PLL IC in consideration of miniaturization / cost reduction of the terminal.

  FIG. 9 shows a specific configuration of a local oscillator using a PLLIC having two PLL circuits. In the illustrated configuration, the PLLIC 4a includes a first PLL circuit 7A corresponding to the 1650 MHz band and a second PLL circuit 8A corresponding to the 250 MHz band. Similarly, the other PLLIC 4b includes a first PLL circuit 7B and a second PLL circuit 8B corresponding to the 1650 MHz band and the 250 MHz band, respectively.

  Each PLL circuit (7A, 8A, 7B, 8B) is wired so that a reference frequency signal from the oscillator 3 is input in parallel, as shown in FIG. In addition, a power control signal for controlling power supplied from a power signal line (not shown) is input to each PLL circuit through each signal line (7AC, 8AC, 7BC, 8BC).

  When the above configuration is made to correspond to FIG. 6, the first PLL circuits 7A and 7B correspond to the first local oscillators 1A and 1B in FIG. 6, and the second PLL circuit 8A corresponds to the second local oscillator 2 in FIG. . Therefore, conventionally, in performing slot variable communication, the second PLL circuit 8B of the PLLIC 4b is not necessary. Therefore, the second PLL circuit 8B is always connected without connecting the VCO 5 or the amplifier 6 serving as an output circuit. Action is taken to maintain the battery save state.

  FIG. 10 shows an operation example according to the configuration of FIG. While the first PLL circuit 7A, the second PLL circuit 8A, and the first PLL circuit 7B operate in the same manner as the operations of the local oscillation units corresponding to each of them in FIG. 7, the second PLL circuit 8B is always activated without being activated. Put in the save state.

Here, in the PLLIC 4a and the PLLIC 4b, when the PLL circuit is activated or enters the battery saving state, a change in bias potential occurs at the input terminal 9a and the input terminal 9b to which the reference frequency signal is input. . Therefore, in order to prevent the bias voltage from being transmitted to other devices, a DC component is removed between the input terminal 9a and the input terminal 9b and the output terminal 9c of the oscillator 3 as shown in FIG. A DC cut capacitor 10a and a DC cut capacitor 10b are arranged.
JP-A-11-331021

  As shown in FIG. 10, in the PLLIC 4b, while the second PLL circuit 8B is always in the battery saving state, the other first PLL circuit 7B is activated in the middle of the third slot in advance for communication in the fourth slot. At this time, that is, at the timing indicated by the arrow in FIG. 10, the bias potential at the input terminal 9b of the PLLIC 4b changes. However, the AC component of the bias voltage generated by this change is not removed by the DC cut capacitor 10b. A situation occurs in which the DC cut capacitor 10b is pulled out in the reverse direction.

  Then, the frequency of the signal handled by the first PLL circuit 7A and the second PLL circuit 8A may fluctuate due to the influence of the bias potential at the input terminal 9a on the other PLLIC 4a side. Alternatively, when the AC component that has passed through the DC cut capacitor 10b is input to the oscillator 3 in the reverse direction from the output terminal 9c, the reference frequency itself of the oscillator 3 may be changed. When such frequency fluctuations occur in the third slot during communication, there is a problem that data modulation / demodulation accuracy in the third slot deteriorates.

  As a technique for avoiding the above problem, for example, as shown in FIG. 11, a circuit 11 composed of an amplifier and a capacitor is provided between the DC cut capacitor 10b on the PLLIC 4b side and the output terminal 9c of the oscillator 3. It is possible to insert. By adopting the configuration shown in the figure, it is possible to prevent the above-mentioned AC component from coming off in the reverse direction, but there is a disadvantage that the mounting area and cost for adding the circuit 11 increase.

  The present invention has been made in view of the above problems, and an object of the present invention is to provide a technique for preventing frequency fluctuation in variable slot type communication in consideration of miniaturization / cost reduction of a portable information terminal. .

The local oscillation circuit according to the present invention includes a first integrated circuit and a second integrated circuit each having two PLL circuits corresponding to signals of two frequency bands to be output in a TDMA / TDD frame period, A reference oscillation circuit connected to both the first and second integrated circuits to supply a reference frequency signal to each PLL circuit in parallel, and output signals of the first integrated circuit and the second integrated circuit An output circuit for outputting signals in the two frequency bands based on the first PLL circuit, and one PLL circuit of the second integrated circuit in the same system as the first integrated circuit, The other PLL circuit of the first integrated circuit is connected to a signal line to which a control signal for operating each PLL circuit in a different time slot during a frame period is supplied and the output circuit. Is connected to a signal line to which a control signal for operating the PLL circuit in both different time slots and the output circuit are connected, and the other PLL circuit of the second integrated circuit is It is connected to any one of the signal lines to which the PLL circuit of the first integrated circuit is connected, and is not connected to the output circuit.

  A portable information terminal according to the present invention includes the local oscillation circuit, and performs wireless communication using signals in two frequency bands output from the local oscillation circuit.

A local oscillation control method according to the present invention includes a first integrated circuit and a second integrated circuit each having two PLL circuits corresponding to signals of two frequency bands to be output in a TDMA / TDD frame period; A reference oscillation circuit connected to both the first and second integrated circuits to supply a signal of a reference frequency in parallel to each PLL circuit, and outputs of the first integrated circuit and the second integrated circuit In a local oscillation circuit comprising an output circuit that outputs signals in the two frequency bands based on the signal, a signal of a reference frequency is input in parallel to the PLL circuits of the first and second integrated circuits, With respect to one PLL circuit of the first integrated circuit and one PLL circuit of the second integrated circuit that is in the same system as the circuit, each PLL circuit is connected to a different time slot during a frame period. A control signal for operating the PLL circuit, an output signal of each PLL circuit is input to the output circuit, and the PLL circuit is different from the other PLL circuit of the first integrated circuit. Without inputting a control signal for operating in both time slots, inputting the output signal of the PLL circuit to the output circuit, and connecting the other PLL circuit of the second integrated circuit to the output circuit Any control signal input to the PLL circuit of the first integrated circuit is input to the PLL circuit.

  According to the present invention, the control signal input to the other PLL circuit of the second integrated circuit is wired so as to be the same as that for any of the PLL circuits of the first integrated circuit. The timing at which the bias potential is generated at the input terminal of the circuit can be made the same as that of the other first integrated circuit. Thereby, it is possible to avoid the bias potential of the input terminal from changing during the time slot during communication without adding a circuit such as an amplifier.

  Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. FIG. 1 shows a configuration of a first embodiment of a local oscillation circuit according to the present invention. The local oscillation circuit of this embodiment includes an oscillator 30 that oscillates a signal of a reference frequency, a PLLIC 40a having a first PLL circuit 70A and a second PLL circuit 80A, a PLLIC 40b having a first PLL circuit 70B and a second PLL circuit 80B, and the present invention. VCO 50 and amplifier 60 corresponding to the output circuit in FIG.

  The PLLIC 40a and the PLLIC 40b are components corresponding to the first integrated circuit and the second integrated circuit in the present invention, and a power supply control signal is supplied to each PLL circuit (70A, 80A, 70B, 80B). Signal lines (70AC, 80AC, 70BC, 80BC) are connected.

  As shown in FIG. 1, the oscillator 30 is connected to the PLLIC 40a and the PLLIC 40b so as to supply a signal of a reference frequency to each PLL circuit (70A, 80A, 70B, 80B) in parallel. Further, a DC cut capacitor 100a / 100b is provided between the output terminal 90c of the oscillator 30 and the input terminal 90a / 90b of the PLLIC 40a / 40b to remove the direct current component of the bias voltage generated at the input terminal 90a / 90b. It has been.

  The first PLL circuit 70A and the first PLL circuit 70B perform PLL processing on signals in the 1650 MHz band in consecutive different time slots. Further, the second PLL circuit 80A performs PLL processing of signals in the 250 MHz band in two time slots in which the first PLL circuits 70A / 70B operate. The first PLL circuit 70A and the second PLL circuit 80A of the PLLIC 40a and the first PLL circuit 70B of the PLLIC 40b are respectively connected to the above-described output circuits, and the respective output signals are input to this output circuit.

  On the other hand, the second PLL circuit 80B is not connected to the output circuit as shown in FIG. Further, a signal line 80BC for supplying a voltage control signal to the second PLL circuit 80B is connected to 80AC of the second PLL circuit 80A at a connection point 91a. By wiring in this way, power control similar to that of the second PLL circuit 80A can be performed on the second PLL circuit 80B that has been conventionally controlled to always be in a battery saving state.

  FIG. 2 shows a list of operations according to the configuration of FIG. In the illustrated example, after the first PLL circuit 70A is operated in the third slot, the first PLL circuit 70B is operated in the fourth slot, while the second PLL circuit 80A is continuously operated in the third and fourth slots. It is a case to operate. Note that each PLL circuit is turned on in the middle of the slot immediately before the time slot to be operated in consideration of the frequency stabilization period as in the prior art.

  Here, as described above, since the second PLL circuit 80B receives the power control signal from the signal line 80BC at the same timing as the second PLL circuit 80A, the operating power is turned on in the middle of the second slot, During the fourth slot, power is supplied in the same manner as the second PLL circuit 80A. As a result, the change in the bias potential generated at the input terminal 90b in the PLLIC 40b is the same as that of the other PLLIC 40a as shown in FIG.

  According to the first embodiment described above, the power control of the second PLL circuit 80B is performed by connecting the signal line 80BC for supplying the power control signal to the second PLL circuit 80B to the signal line 80AC of the second PLL circuit 80A. Can be performed in the same manner as the second PLL circuit 80A. Accordingly, it is possible to avoid the bias potential of the input terminal 90b from changing during the time slot during communication without adding the circuit 11 as shown in FIG.

  FIG. 3 shows the configuration of the second embodiment of the local oscillation circuit according to the present invention. In the first embodiment described above, the power supply control signal for the second PLL circuit 80B is wired to be the same as that of the second PLL circuit 80A, but in this embodiment, the power supply control signal is wired to be controlled in the same manner as the first PLL circuit 70A. To do. Specifically, as shown in FIG. 3, the signal line 80BC of the second PLL circuit 80B is connected to the signal line 70AC of the first PLL circuit 70A at a connection point 91b. Other configurations are the same as those of the first embodiment shown in FIG.

  FIG. 4 shows a list of operations according to the configuration of the present embodiment. From the list shown in the drawing, the second PLL circuit 80B is controlled to be activated in the middle of the second slot and receive operating power in the third slot, like the first PLL circuit 70A. Further, in the subsequent fourth slot, the second PLL circuit 80B returns to the battery saving state similarly to the first PLL circuit 70A, but the other first PLL circuit 70B operates.

  As a result, the change in the bias potential generated at the input terminal 90b of the PLLIC 40b is the same as that of the other PLLIC 40a. Therefore, the second embodiment shown in FIG. 3 can provide the same effects as those of the first embodiment.

  The local oscillation circuit of the present invention is suitable for a portable information terminal as a PHS terminal adopting TDMA / TDD. As a mode of the terminal, a so-called PC card mounted on a personal computer or the like in addition to a cellular phone is called. Data communication cards and the like.

1 is a circuit diagram of a first embodiment of a local oscillation circuit according to the present invention. It is explanatory drawing of operation | movement by 1st Embodiment. FIG. 4 is a circuit diagram of a second embodiment of a local oscillation circuit according to the present invention. It is explanatory drawing of the operation | movement by 2nd Embodiment. It is explanatory drawing of the conventional frame period. It is a circuit diagram which shows the structure of the conventional portable information terminal. It is explanatory drawing of operation | movement of the conventional local oscillation part. It is a circuit diagram which shows the structure of the conventional local oscillation part. It is a circuit diagram which shows the structure of the conventional local oscillation circuit. It is explanatory drawing of the operation | movement in the conventional local oscillation circuit. It is a circuit diagram which shows the other structure of the conventional local oscillation circuit.

Explanation of symbols

30 Oscillator (fundamental frequency)
40a / 40b PLLIC
50 VCO
60 Amplifier 70A / 70B First PLL circuit 80A / 80B Second PLL circuit 90a / 90b Input terminal 90c Output terminal 91a / 91b Connection point 100a / 100b DC cut capacitor

Claims (6)

A first integrated circuit and a second integrated circuit each having two PLL circuits corresponding to signals of two frequency bands to be output in a TDMA / TDD frame period, and a signal of a reference frequency for each of the PLL circuits Based on the reference oscillation circuit connected to both the first and second integrated circuits and the output signals of the first integrated circuit and the second integrated circuit. An output circuit for outputting a signal,
One PLL circuit of the first integrated circuit and one PLL circuit of the second integrated circuit that is in the same system as the circuit are configured to operate the PLL circuits in different time slots during a frame period. Connected to a signal line to which a control signal is supplied and the output circuit;
The other PLL circuit of the first integrated circuit is connected to a signal line to which a control signal for operating the PLL circuit in both the different time slots is supplied and the output circuit,
The other PLL circuit of the second integrated circuit is connected to any one of the signal lines to which the PLL circuit of the first integrated circuit is connected and is not connected to the output circuit. circuit.   2. The local oscillation circuit according to claim 1, wherein a capacitor is connected between each of the first and second integrated circuits and the reference oscillation circuit.   A portable information terminal comprising the local oscillation circuit according to claim 1 or 2 and performing wireless communication using signals of two frequency bands output from the local oscillation circuit.   4. The portable information terminal according to claim 3, wherein the portable information terminal is a data communication card that is detachable from the information processing apparatus.   4. The portable information terminal according to claim 3, wherein the portable information terminal is a mobile phone. A first integrated circuit and a second integrated circuit each having two PLL circuits corresponding to signals of two frequency bands to be output in a TDMA / TDD frame period, and a signal of a reference frequency for each of the PLL circuits Based on the reference oscillation circuit connected to both the first and second integrated circuits and the output signals of the first integrated circuit and the second integrated circuit. In a local oscillation circuit including an output circuit that outputs a signal,
A reference frequency signal is input in parallel to the PLL circuits of the first and second integrated circuits,
To operate each PLL circuit in a different time slot during a frame period with respect to one PLL circuit of the first integrated circuit and one PLL circuit of the second integrated circuit in the same system as the circuit The control signal is input, and the output signal of each PLL circuit is input to the output circuit,
A control signal for operating the PLL circuit in both of the different time slots is input to the other PLL circuit of the first integrated circuit, and an output signal of the PLL circuit is input to the output circuit And
Any control signal input to the PLL circuit of the first integrated circuit is input to the PLL circuit without connecting the other PLL circuit of the second integrated circuit to the output circuit. A characteristic local oscillation control method.

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