JP2006191405A - Semiconductor integrated circuit for radio communication and radio communication apparatus - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To prevent the occurrence of data omission when data is transferred between a radio communication processing part and an application processing part in a radio communication apparatus such as a Bluetooth communication device. <P>SOLUTION: The radio communication apparatus such as the Bluetooth communication device is provided with a radio communication processing circuit (110), a sampling circuit for sampling an analog signal to be transmitted and a processing circuit (121) for processing the sampled signal, wherein a clock (ϕs) for driving the sampling circuit is generated by sampling a clock (ϕsc) for driving the radio communication processing circuit (110) by a clock (ϕTX) for driving the processing circuit. <P>COPYRIGHT: (C)2006,JPO&NCIPI

Description

  The present invention relates to a radio communication control technique, and further to an analog sampling clock in a radio communication apparatus configured so that a radio communication processing unit and an application processing unit are operated by clock signals generated by separate clock generation circuits. For example, the present invention relates to a technique that is particularly effective when used for a wireless communication IC (semiconductor integrated circuit) of the Bluetooth communication standard and a wireless communication apparatus using the same.

  One of the wireless communication standards is called Bluetooth and performs short-range wireless communication using a frequency band of 2.4 GHz to 2.48 GHz. The Bluetooth standard wireless communication system is a packet communication system that transmits a predetermined amount of data with a header, and includes asynchronous communication (ACL: Asynchronous Connectionless) having a retransmission function and packet transmission at a predetermined cycle without a retransmission function. Two communication modes of synchronous communication (SCO: Synchronous Connection Oriented) for transmission are provided, and transmission and reception are performed in time division.

  In Bluetooth communication, a clock signal (hereinafter simply referred to as a clock) is synchronized between a master device and a slave device, and a communication connection is established, based on a 3.2 kHz clock signal called a Bluetooth clock. Packet data is exchanged at a period twice that of 3.2 kHz (625 μs).

  Devices that are capable of Bluetooth communication can communicate by freely using asynchronous communication and synchronous communication. If you want to send data that requires high reliability, such as text data, use asynchronous communication. For transmission of data such as audio data that requires real-time performance, the use of synchronous communication is performed.

  As described above, in Bluetooth communication, a Bluetooth clock is used on the wireless communication processing unit side to establish a communication connection by synchronizing the clock between the master device and the slave device, while the application processing unit side uses audio. Since it is necessary to transfer and process the audio data at a speed suitable for reproduction of the data, a clock different from that on the wireless communication processing unit side is used. However, if the wireless communication processing unit and the application processing unit are operated with separate clocks that are not synchronized with each other as described above, data is transferred between the wireless communication processing unit and the application processing unit due to a clock phase shift. There is a risk of data loss when exchanging data. In particular, the frequency of the communication device may change due to movement of the communication device, thereby causing a large phase shift from the clock of the application processing unit, and data loss is likely to occur.

In the conventional Bluetooth communication system, in order to prevent such data omission, an invention in which a buffer memory is interposed between the wireless communication processing unit and the application processing unit (Patent Document 1) and a clock of the wireless communication processing unit In order to synchronize the clocks of the application processing unit, there has been proposed an invention (Patent Document 2) in which the other clock is generated by a PLL circuit using one clock as a reference clock.
JP 2003-018133 A JP 2002-141862 A

  However, in the technique in which a buffer memory is interposed between the wireless communication processing unit and the application processing unit, the capacity of the buffer memory must be increased in order to reliably prevent data loss. If the size is increased, the chip size increases and the cost is increased. On the other hand, if the capacity of the buffer memory is reduced, the memory overflows or underflows, resulting in data loss. As countermeasures against overflow and underflow, there are data discarding processing and data interpolation processing. However, if data is lost in the transmission of audio data by means of synchronous communication that does not have a retransmission function, the data reproduction quality will be degraded by data interpolation. There are challenges.

  Further, in the technology using a clock generation circuit using a PLL circuit, as is well known, the PLL circuit is a large-scale circuit including a voltage controlled oscillation circuit, a phase comparison circuit, a loop filter, and the like. In addition to increasing costs and increasing power consumption, portable devices that operate on batteries have a problem of shortening the battery life.

  An object of the present invention is to provide a technique capable of preventing occurrence of data loss when data is exchanged between a wireless communication processing unit and an application processing unit in a wireless communication device such as a Bluetooth communication device. There is to do.

  Another object of the present invention is to prevent data loss when exchanging data between a wireless communication processing unit and an application processing unit without using a large-scale circuit in a wireless communication device such as a Bluetooth communication device. It is an object of the present invention to provide a technique capable of preventing the occurrence and reducing the chip size and the power consumption.

  Furthermore, another object of the present invention is to reduce the quality of audio and video reproduced on the receiving side when the audio communication function and the moving image communication function are provided in a synchronous communication mode without a retransmission function such as Bluetooth communication. It is an object to provide a communication control technique and a wireless communication apparatus that can prevent communication and improve communication quality.

  The above and other objects and novel features of the present invention will be apparent from the description of this specification and the accompanying drawings.

Outlines of representative ones of the inventions disclosed in the present application will be described as follows.
That is, the present invention provides a Bluetooth including a wireless communication protocol processing circuit and a data processing circuit that processes a signal sampled by a sampling circuit that samples an analog signal to be transmitted or processes received data and passes the data to the sampling circuit. In a wireless communication apparatus such as a communication device, a clock for operating the sampling circuit is generated by sampling a clock synchronized with a clock for operating the wireless communication processing circuit with a clock for operating the data processing circuit. It is.

  According to the above-described means, since the clock for wireless communication processing and the sampling clock of the analog signal to be transmitted are synchronized, the wireless communication processing unit (wireless communication protocol processing circuit) and the application processing unit (data processing circuit) Data can be prevented from being lost when data is exchanged between them, and the clock of the wireless communication processing unit and the application processing unit can be controlled by an open loop synchronization circuit that does not have a feedback path such as a PLL circuit. Since the clocks can be synchronized, data loss can be prevented without using a large-scale circuit, and the chip size and power consumption can be reduced.

  In addition, when audio data or moving image data is transmitted in a synchronous communication mode that does not have a retransmission function, it is possible to prevent data loss, so that no data interpolation processing is required, and audio that is played back on the receiving side. And the quality of video can be prevented from being lowered and communication quality can be improved.

The effects obtained by the representative ones of the inventions disclosed in the present application will be briefly described as follows.
That is, according to the present invention, in a wireless communication device such as a Bluetooth communication device, data is prevented from being lost when data is exchanged between the wireless communication processing unit and the application processing unit, thereby improving communication reliability. Can be improved.

Preferred embodiments of the present invention will be described below with reference to the drawings.
The most suitable wireless communication apparatus to which the present invention is applied is a wireless communication apparatus having a Bluetooth communication function. As a specific example of a wireless communication device having a Bluetooth communication function, for example, a wireless headphone that receives and reproduces audio data from an audio player or a head that enables a hands-free call by performing voice communication with a mobile phone There is a set.

  The Bluetooth standard is a standard that guarantees mutual connection even when the Bluetooth communication device built in each of the mobile phone and the headset or the mobile phone and the headset is provided by different vendors. If the Bluetooth communication device built into each of the mobile phone and the headset has a unique function that is out of the Bluetooth standard (protocol), they cannot be connected to each other. Such a property that communication devices that communicate with each other according to a predetermined standard cannot be connected to each other when having a unique function that is out of the predetermined standard is called interoperability.

  Note that one electronic device (base device) that performs Bluetooth communication has a plurality of functions such as a display function such as a liquid crystal panel and an input operation function using a numeric keypad. An electronic device such as an IC (semiconductor integrated circuit) that supports Bluetooth communication or a module in which a plurality of ICs and electronic components are mounted on an insulating substrate or in a ceramic package so as to have a Bluetooth communication function is referred to as a Bluetooth communication device.

FIG. 1 shows a configuration of a first embodiment of a Bluetooth communication device having a communication function according to the Bluetooth standard.
As shown in FIG. 1, the Bluetooth communication device of this embodiment can be roughly divided into a wireless communication processing unit 110 that transmits and receives data via an antenna ANT, and a transmission data encoding and reception data composite. An application processing unit 120 that performs processing according to the application, such as conversion, and a control unit 130 that controls them. In addition, a buffer memory 140 is provided between the wireless communication processing unit 110 and the application processing unit 120 to absorb a difference in data transfer speed.

  The radio communication processing unit 110 includes a high-frequency signal processing unit 111 as a physical layer (a radio layer) having a transmission signal up-conversion function, a modulation function, an amplification function, a reception signal amplification function, a demodulation function, a down-conversion function, and the like. A protocol processing circuit that processes data transmitted / received by the high-frequency signal processing unit 111 according to a Bluetooth communication protocol, establishes a communication connection state with a communication partner device, and performs packet analysis, decoding, reconstruction, etc. The baseband control unit 112, the operation of the high-frequency signal processing unit 111 and the baseband control unit 112, the clock generation unit 113 that generates clocks φRF and φBB necessary for data transfer, and the like.

  The baseband control unit 112 is functionally composed of a so-called link controller, a link manager that manages link control between the link controller and the physical layer, and the hardware includes a microprocessor (CPU) and its operation program. Consists of stored memory. The high frequency signal processing unit 111 generates a timing signal φt for synchronous communication based on a received signal from a communication partner device, and supplies the timing signal φt to the clock generation unit 113. The clock generation unit 113 performs high frequency in accordance with the timing signal φt. By generating clocks φRF and φBB to be supplied to the signal processing unit 111 and the baseband control unit 112, Bluetooth synchronous communication is enabled. The clock generation unit 113 generates a synchronization clock φsc for synchronizing data transfer with the application processing unit 120.

  The control unit 130 controls the entire system in accordance with a predetermined sequence or generates a control signal for the wireless communication processing unit 110 in accordance with the Bluetooth communication protocol. As hardware, a microprocessor (CPU) 131 and its operation program are stored. It comprises a stored memory 132, a clock generator 133, and the like. The clock generation unit 133 generates an operation clock φcpu for the CPU 131 and a transfer clock φTX used by the application processing unit 120.

  The application processing unit 120 is provided at a voice input / output processing unit 121 that performs processing such as compression and decompression of voice data, AD conversion processing of a transmission signal, and DA conversion processing of received data, and an entrance of the voice input / output processing unit 121. And a clock synchronization processing unit 122 that generates a sampling clock φs of a sampling circuit that takes in an analog signal such as an audio signal. The clock synchronization processing unit 122 samples the synchronization clock φsc from the clock generation unit 113 of the wireless communication processing unit 110 with the transfer clock φTX from the clock generation unit 133 of the control unit 130, thereby obtaining a sampling clock φs synchronized with φsc. Generate.

  The application processing unit 120 also includes an LLCA protocol unit that performs depacketization of data from the wireless communication processing unit 110 and packetization of data to be passed to the wireless communication processing unit 110, and confirmation of valid services of the communication partner device. Functions such as an SD protocol unit that performs communication, an SCE protocol unit that emulates RS-232C, and a profile unit that bridges the application and the Bluetooth communication protocol and standardizes device-specific communication procedures for each product characteristic.

  FIG. 2 shows the configurations and the interrelationships of the clock generators 113 and 133 and the clock synchronization processor 122. The clock generation unit 113 of the wireless communication processing unit 110 divides the oscillation circuit OSC1 for RF that generates the RF clock φRF necessary for the RF transmission / reception processing unit 111, and the oscillation output φRF of the oscillation circuit, thereby dividing the baseband control unit 112 includes a necessary data transfer clock φBB and a frequency dividing circuit DIV1 for generating a synchronizing clock φsc. Further, the clock generation unit 133 of the control unit 130 divides the oscillation output φcpu of the oscillation circuit OSC2 that generates the CPU clock φcpu and the audio input / output processing unit 121 by dividing the oscillation output φcpu of the oscillation circuit. And a frequency dividing circuit DIV2 to be generated.

  The clock synchronization processing unit 122 includes D-type flip-flops FF1 and FF2 connected in series, and the synchronization clock φsc from the wireless communication processing unit 110 is input to the data terminal D of the flip-flop FF1 in the previous stage, and FF1 and FF2 When the application data transfer clock φTX and its inverted clock / φTX are input to the clock terminal CK, the clock φsc is sampled with the clock φTX to generate a sampling clock φs synchronized with φsc.

  FIG. 3 shows an example of the timing of each clock. The RF clock φRF and the application data transfer clock φTX are high-frequency clocks such as 13 MHz and 20 MHz, respectively, and the synchronous clock φsc and the sampling clock φs are low-frequency clocks such as 8 KHz, respectively. The clock φBB supplied to the baseband control unit 112 is a reference clock signal called a Bluetooth clock that determines the period of Bluetooth communication and has a frequency such as 3.2 kHz. Further, the CPU clock φcpu has a frequency such as several hundred MHz.

  As shown in FIG. 3, if the synchronization clock φsc is at a high level at the time T1 when the application data transfer clock φTX rises, the sampling clock φs output from the clock synchronization processing unit 122 by taking this is high. If φsc is low level at the time T2 of the next rise of φTX, the sampling clock φs output from the clock synchronization processing unit 122 changes to low level by capturing this.

  The 8 KHz synchronous clock φsc is generated by dividing the 13 MHz RF clock φRF, and this is sampled with the 20 MHz application data transfer clock φTX to generate φs. Therefore, the generated sampling clock φs is It has a frequency of (8 KHz ± α), and the maximum value of α is the frequency of the application data transfer clock φTX, which is 20 MHz here. Therefore, since the fluctuation range of the frequency of the sampling clock φs is only ± 0.04% centering on 8 KHz, it can be considered that the synchronization is almost achieved. This makes it possible to synchronize the data transfer processing on the wireless communication processing unit 110 side and the sampling processing on the application processing unit 120 side. Further, since there is a fluctuation range of the frequency of the sampling clock φs as described above, more accurate data processing can be performed by providing the buffer 140 to prevent data omission, but the frequency of the sampling clock φs Since the fluctuation range is not a large size, there is no problem even if the memory capacity of the buffer 140 is small compared to the conventional case.

Next, as a second embodiment of the present invention, an embodiment suitable for a Bluetooth communication device for communicating audio data such as an audio player and wireless headphones will be described.
In the DV audio standard, three types of sampling modes of 32 kHz, 44.1 kHz, and 48 kHz are defined. Therefore, when transmitting audio data by Bluetooth communication, it is desirable that audio data sampled in any of these three types of sampling modes can be handled. Here, as an example, the frequency plan of each clock when designing a device that can handle two sampling frequencies of 32 kHz and 48 kHz will be described with reference to FIG.

  The RF clock φRF and the application data transfer clock φTX are high-frequency clocks such as 13 MHz and 20 MHz, respectively, as in the first embodiment, and the synchronization clock φsc is 96 kHz which is the least common multiple of 32 kHz and 48 kHz. That is, the frequency dividing circuit DIV1 of FIG. 2 is designed so that the 96 kHz synchronous clock φsc can be generated by dividing the RF clock φRF. The sampling clock φs is set to 32 KHz or 48 kHz depending on the sampling mode of audio data to be transmitted. The clock φBB supplied to the baseband control unit 112 has a frequency of 3.2 kHz, and the CPU clock φcpu has a frequency of several hundreds of MHz.

  Also in this embodiment, as shown in FIG. 4, the sampling clock φs output from the clock synchronization processing unit 122 is set to the high level by capturing the synchronous clock φsc at the rising timing T1 of the application data transfer clock φTX. The sampling clock φs outputted by taking in φsc at the next rising timing T2 of φTX changes to the low level. By selecting 96 kHz which is the least common multiple of 32 kHz and 48 kHz as the synchronization clock φsc, data between the wireless communication processing unit 110 and the application processing unit 120 can be obtained regardless of the sampling data of 32 kHz or 48 kHz. It is possible to transfer without causing omission.

  In the frequency plan of this embodiment, 96 kHz, which is the least common multiple of 32 kHz and 48 kHz, is selected as the frequency of the synchronous clock φsc. However, the present invention is not limited to this and may be an integral multiple, that is, a common multiple. Further, instead of using a variable frequency dividing circuit as the frequency dividing circuit DIV1 that divides the RF clock φRF and generating a synchronous clock φsc fixed at 96 KHz, the variable frequency dividing circuit is switched according to the sampling mode to 32 kHz or 48 kHz. The synchronous clock φsc may be generated and output.

  When the audio data to be transmitted is 32 KHz or 44.1 kHz, 352 KHz which is the least common multiple of “32” and “44.1” or approximately the least common multiple of “32” and “44” or an integer thereof. You may make it select a double frequency. Further, when the audio data to be transmitted is 32 kHz, 44.1 kHz, or 48 kHz, the least common multiple of “32”, “44.1”, and “48” or approximately “32”, “44”, and “48”. The frequency of 1056 KHz, which is the least common multiple of ", or an integer multiple thereof, may be selected.

Next, a modification of the second embodiment will be described with reference to FIG.
This modification is another example of the frequency plan of each clock when designing a device that can handle two sampling frequencies of 32 kHz and 48 kHz. The difference from the frequency plan of FIG. 4 is that the application data transfer clock φTX Instead of 20 MHz, a clock with a higher frequency of 30 MHz is used. By applying this modification, the number of determinations of the synchronous clock φsc for generating the sampling clock φs increases, so that there is an advantage that the synchronization shift can be made smaller than in the second embodiment.

  Specifically, the fluctuation (α) of the frequency of the sampling clock φs can be reduced from ± 20 MHz to ± 30 MHz, that is, from ± 0.04% to ± 0.027%. A clock φTX having a frequency of 40 MHz may be used instead of the clock φTX having a frequency of 30 MHz. According to this modified example, particularly when applied to a device that transmits audio data, it is possible to reduce the reproduction of an annoying sound caused by the jitter of the sampling clock.

FIG. 6 shows a more specific configuration of the Bluetooth communication device to which the embodiment is applied. In FIG. 6, blocks having the same functions as those in FIG.
The Bluetooth communication device according to this embodiment includes a baseband control unit 112 of the wireless communication processing unit 110, a digital circuit portion excluding an analog circuit portion of the voice input / output processing unit 121 of the application processing unit 120, and a control unit 130 The portion excluding the memory 132 is configured as a semiconductor integrated circuit (Bluetooth communication IC) 100 on one semiconductor chip.

  The RF module 200 as a high-frequency signal processing device constituting the RF transmission / reception processing unit (physical layer) 111 and the flash memory 310 storing the application program among the memory 132 of the control unit 130 and the SRAM 320 providing the work area of the CPU An analog processing LSI 500 that is an analog circuit portion of the voice input / output processing unit 121 is further mounted on the printed wiring board, and is connected to the Bluetooth communication IC 100 as an external component. An audio signal from a microphone or an audio signal read from a medium is input to the analog processing LSI 500 and sampled, and a headphone drive signal is output from the analog processing LSI 500.

  In the system of this embodiment, an oscillator 210 having a high frequency such as 13 MHz is connected to the RF module 200 to generate a clock signal φRF necessary for the operation of the RF transmission / reception processor 111, and the clock signal φRF is The signal is supplied to a frequency dividing circuit DIV1 as a clock generation circuit in the Bluetooth communication IC 100, and is used as a clock signal serving as a reference for the data transfer clock (Bluetooth clock) φBB and the synchronization clock φsc of the baseband control unit 112. Further, the Bluetooth communication IC 100 of this embodiment is provided with a clock pulse generator (CPG) 122 that multiplies the clock signal φRF from the RF module 200 to generate a CPU clock φcpu of a frequency such as 26 MHz or 52 MHz. Yes.

  The RF module 200 includes a modulation / demodulation IC, a power amplifier (high frequency power amplifier), a filter for removing unnecessary waves, a transmission / reception changeover switch, and the like. The Bluetooth communication IC 100 according to the present embodiment is provided with a function of supplying a voltage Vpc for determining and controlling the power of the power amplifier to the RF module 200, which is converted into an analog voltage by a DA converter DAC inside the chip. It is configured to output.

  Further, although not particularly limited, in the system of the present embodiment, a power supply voltage from a battery power source such as 3.3V is applied to the Bluetooth communication IC 100 and the RF module 200 such as 2.8V. A voltage regulator (DC-DC converter) 400 for converting to a power supply voltage and an external SRAM (static memory) 320 for providing a temporary storage area for data and a work area for the CPU are provided. Since the SRAM 320 is provided, the previously received data can be stored, and when the received data is detected, the data can be interpolated based on the already received data. . Since voice data does not require as much accuracy as text data, data interpolation is performed based on previously received data in voice communication using Bluetooth communication, thereby avoiding deterioration in sound quality due to voice interruptions. There is an advantage that you can.

  In this embodiment, a cache memory 181, a RAM 182, and a memory access controller (MAC) 183 are connected to the CPU 131 via a first CPU bus L-bus. The cache memory 181 and the RAM 182 are connected between the first CPU bus L-bus and the second CPU bus I-bus, and a bus for exchanging data between the buses between the second CPU bus I-bus and the peripheral bus HPB. A bridge PPBS is provided. A DMA controller DMAC for performing DMA (direct memory access) transfer control is connected to the second CPU bus I-bus.

  Further, in the Bluetooth communication device of this embodiment, the second CPU bus I-bus is provided with a bus state controller BSC for performing control such as timing adjustment of signals on the bus, and the second CPU bus I-bus is provided with the bus state controller. Data signals can be exchanged with the external system bus 330 to which the flash memory 310 and the SRAM 320 are connected via the BSC. The RAM 182 (or SRAM 320) corresponds to the buffer memory 140 in FIG.

  The peripheral bus HPB includes a timer unit TMU for various time management, serial communication interfaces SCIF1 and SCIF0 for serially inputting / outputting signals to / from an external device, an interrupt controller INTC for receiving an interrupt from the external device, an analog Peripheral circuits such as a conversion circuit DAC that performs digital, conversion, and digital / analog conversion are connected.

  As described above, in the above-described embodiment, the wireless communication processing circuit (112) is synchronized with the rising (or falling) of the clock φTX that operates the data processing circuit (121) that processes the sampled signal. Since the clock φsc synchronized with the clock φBB to be operated is taken into the synchronization circuit (122), that is, by sampling φsc with φTX, the clock φs for operating the analog signal sampling circuit (500) is generated. The communication processing clock φBB and the sampling clock φs of the analog signal to be transmitted are synchronized. Therefore, it is possible to prevent data loss when data is exchanged between the wireless communication processing unit and the application processing unit, and an open loop synchronization circuit that does not have a feedback path such as a PLL circuit. This makes it possible to synchronize the clock of the wireless communication processing unit and the clock of the application processing unit, thereby preventing data loss without using a large-scale circuit and reducing the chip size and power consumption. be able to.

  In addition, since data loss can be prevented when audio data or moving image data is transmitted in a synchronous communication mode that does not have a retransmission function, no data interpolation processing is required, and audio or It is possible to prevent deterioration in video quality and improve communication quality.

  The invention made by the present inventor has been specifically described based on the embodiments. However, the present invention is not limited to the above embodiments, and various modifications can be made without departing from the scope of the invention. Nor.

  For example, in the above-described embodiment, the clock generation circuit that divides the oscillation output φRF of the oscillation circuit OSC1 for the RF clock to generate the data transfer clock φBB and the synchronization clock φsc by the frequency divider DIV1, and the CPU clock The clock generation circuit for generating the application data transfer clock φTX by dividing the oscillation output φcpu of the oscillation circuit OSC2 is configured by the frequency divider DIV2, but each of the frequency dividers DIV1 and DIV2 has a reference In order to generate a clock having a different phase with respect to the other clock, a phase shift function for shifting the phase may be included.

  As described above, the case where the present invention is mainly applied to communication using the Bluetooth standard, specifically, an example assuming a music data transmission system including an audio player and wireless headphones has been described, but the present invention is not limited thereto. Voice communication between a headset and a personal computer, which is used as a transceiver or extension telephone by Bluetooth communication, or a voice communication system (so-called Internet phone) using the Internet, communication of a hands-free system consisting of a mobile phone and a headset Furthermore, it can be widely used for synchronous communication using packets other than Bluetooth communication.

FIG. 1 is a block diagram showing a configuration of a first embodiment of a Bluetooth communication device having a communication function according to the Bluetooth standard. FIG. 2 is a block diagram showing the configuration and interrelationships of the clock generation unit and the clock synchronization processing unit in the Bluetooth communication device of FIG. FIG. 3 is a timing chart showing timings of various clocks used in the Bluetooth communication device of the first embodiment. FIG. 4 is a timing chart showing timings of various clocks used in the Bluetooth communication device of the second embodiment. FIG. 5 is a timing chart showing timings of various clocks in a modification of the second embodiment. FIG. 6 is a block diagram showing a more specific configuration example of the Bluetooth communication device to which the first embodiment is applied.

Explanation of symbols

DESCRIPTION OF SYMBOLS 110 Communication processing part 111 High frequency signal processing part 112 Baseband control part 113 Clock generation part 120 Application processing part 121 Audio | voice input / output processing part 122 Clock synchronous processing part 130 Control part 130
131 Microprocessor (CPU)
132 Memory 133 Clock Generator 140 Buffer Memory

Claims (11)

A data processing circuit for processing a signal sampled by a sampling circuit for sampling a data signal to be transmitted;
A protocol processing circuit that receives the output of the data processing circuit and generates data to be transmitted by wireless communication according to a predetermined protocol;
By sampling a second clock signal synchronized with a first clock signal for operating the protocol processing circuit with a third clock signal having a higher frequency than the second clock signal and operating the data processing circuit, A clock generation circuit for generating a fourth clock signal for operating the sampling circuit;
A semiconductor integrated circuit for wireless communication, comprising:   Between the protocol processing circuit and the data processing circuit, there is provided a buffer memory that temporarily holds transmission data transferred between these circuits. The buffer memory is configured to store the first clock signal and the third clock signal. 2. The semiconductor integrated circuit for wireless communication according to claim 1, wherein a read / write operation is performed by each of the clock signals.   The control circuit for controlling the protocol processing circuit and the data processing circuit, wherein the third clock signal is generated based on a fifth clock signal for operating the control circuit. Semiconductor integrated circuit for wireless communication. A protocol processing circuit for generating received data based on a signal received by wireless communication according to a predetermined protocol;
A data processing circuit that receives an output of a sampling circuit that samples the received data and generates a signal corresponding to the received data;
By sampling a second clock signal synchronized with a first clock signal for operating the protocol processing circuit with a third clock signal having a higher frequency than the second clock signal and operating the data processing circuit, A clock generation circuit for generating a fourth clock signal for operating the sampling circuit;
A semiconductor integrated circuit for wireless communication, comprising:   Between the protocol processing circuit and the data processing circuit, there is provided a buffer memory that temporarily holds transmission data transferred between these circuits. The buffer memory is configured to store the first clock signal and the third clock signal. 5. The semiconductor integrated circuit for wireless communication according to claim 4, wherein the read / write operation is performed by each of the clock signals.   5. The control circuit according to claim 4, further comprising a control circuit that controls the protocol processing circuit and the data processing circuit, wherein the third clock signal is generated based on a fifth clock signal that operates the control circuit. Semiconductor integrated circuit for wireless communication.   2. The semiconductor integrated circuit for wireless communication according to claim 1, wherein the predetermined protocol is a protocol according to a Bluetooth standard. A data processing circuit that processes a signal sampled by a sampling circuit that samples a data signal to be transmitted, and a protocol processing circuit that receives the output of the data processing circuit and generates data to be transmitted by wireless communication according to a predetermined protocol; Sampling a second clock signal synchronized with a first clock signal for operating the protocol processing circuit with a third clock signal for operating the data processing circuit having a higher frequency than the second clock signal; A wireless communication semiconductor integrated circuit comprising: a clock generation circuit for generating a fourth clock signal for operating the sampling circuit;
An analog processing circuit that includes the sampling circuit, converts an analog input signal into a digital signal, and generates transmission data to be supplied to the semiconductor integrated circuit for wireless communication;
A high-frequency signal processing circuit that transmits the data to be transmitted generated by the protocol processing circuit on a high-frequency carrier wave;
The wireless communication apparatus, wherein the fourth clock signal generated by the clock generation circuit is supplied from the wireless communication semiconductor integrated circuit to the analog processing circuit. A protocol processing circuit that generates received data based on a first signal received by wireless communication according to a predetermined protocol;
A data processing circuit that receives an output of a sampling circuit that samples the received data and generates a signal corresponding to the received data;
By sampling a second clock signal synchronized with a first clock signal for operating the protocol processing circuit with a third clock signal having a higher frequency than the second clock signal and operating the data processing circuit, A clock generation circuit for generating a fourth clock signal for operating the sampling circuit;
A semiconductor integrated circuit for wireless communication comprising:
An analog processing circuit that includes the sampling circuit, processes the output supplied from the semiconductor integrated circuit for wireless communication, converts the output into an analog signal, and outputs the analog signal; and extracts the first signal from the received signal to the protocol processing circuit A wireless communication device, wherein the fourth clock signal generated by the clock generation circuit is supplied from the wireless communication semiconductor integrated circuit to the analog processing circuit.   10. The wireless communication apparatus according to claim 9, wherein the frequency of the second clock signal is a common multiple of at least any two sampling frequencies of audio data defined by the DV audio standard. 2. The semiconductor integrated circuit for wireless communication according to claim 1, wherein the clock generation circuit is an open loop synchronization circuit having no feedback path for synchronization.

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