KR100642486B1 - Method for fabricating a trench of dual damascene interconnection in semiconductor device - Google Patents

Abstract

A method for forming a dual damascene wire trench of a semiconductor device is provided to control the generation of micro trench phenomenon and ununiformity of trench etching depth by employing a first etching process where a second dielectric is etched and a second etching process where a second etch stop layer is over-etched. A first etch stop layer(14) is formed on a lower metal layer(12). A inter metal layer(16) including a first dielectric(16a), a second etch stop layer(16b), and a second dielectric(16c) is formed on the first etch stop layer. The inter-metal dielectric is etch by using a mask pattern to form trenches(T1,T2). Low dielectric constant SiH4 is used as the second etch stop layer. When the trenches are formed, the second dielectric is etched by the time that the second etch stop layer is exposed, the second etch stop layer is over etched.

Description

METHODE FOR FABRICATING A TRENCH OF DUAL DAMASCENE INTERCONNECTION IN SEMICONDUCTOR DEVICE}

1 is a cross-sectional view illustrating a method for forming a dual damascene wiring trench according to the prior art.

2 to 4 are cross-sectional views illustrating a method for forming a dual damascene wiring trench according to an exemplary embodiment of the present invention.

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for forming a wiring of a semiconductor device, and more particularly to a method for forming a dual damascene wiring trench for a semiconductor device.

Recently, as copper (Cu) wiring having better electrical characteristics than aluminum (Al) or tungsten (W) has been introduced, a dual damascene process for overcoming the difficulty of dry etching of copper has been widely used. According to this dual damascene process, via holes and trenches are formed, and the via holes and trenches are filled with a copper film, followed by a planarization process.

In more detail, the etch stop film and the intermetallic insulating film are sequentially formed on the lower metal film.

Here, the intermetallic insulating film may be formed of a single layer structure of any one material selected from FSG, BPSG, d-TEOS, or USG film, or may be formed of a multilayer structure of two or more layers of the insulating film of the material.

When the intermetallic insulating film has a multilayer structure, a material film having a high etching selectivity with respect to the insulating film is formed between the lower first insulating film and the upper second insulating film, for example, a SiN or SiC film. The film acts as an etch stop film during trench formation.

After the intermetallic insulating film is formed, the via holes and the trenches are formed by the via first method or the trench first method. Here, the via first method refers to a method of forming a trench after forming a via hole first, and the trench first method refers to a method of forming a via hole after forming a trench first.

Thereafter, the etch stop film exposed by the via hole is removed to expose the lower metal film, and then the barrier metal film and the upper metal film are sequentially formed.

However, in the dual damascene process, when the intermetallic insulating film 106 is formed in a single layer structure as shown in FIG. 1, a difference occurs in the etching depths D1 and D2 of the trenches T1 and T2. , A micro trench phenomenon (part A) in which corner portions of the trenches T1 and T2 are more etched is generated. In FIG. 1, reference numeral 100 denotes a lower insulating film, 102 a lower metal film, and 104 an etch stop film, respectively.

Although not shown, the following problem occurs when the intermetallic insulating film is formed in a multilayer structure having SiN or SiC film as an etch stop film.

As is well known, since the SiN or SiC film is a high-k material, when the SiN or SiC film cannot be completely removed, the RC delay is increased to degrade the device performance. Thus, the effect of using an insulating film having a low dielectric constant (low-k) as the intermetallic insulating film to reduce the RC delay is halved.

The technical problem to be achieved by the present invention is to provide a method for forming a dual damascene wiring trench of a semiconductor device that can reduce the RC delay due to the use of the etch stop layer, and can suppress the variation of trench etching depth and the occurrence of micro trench phenomenon. .

The present invention to achieve the above technical problem,

Forming a first etch stop layer on the lower metal layer;

Forming an intermetallic insulating film including a first insulating film, a second etch stop film, and a second insulating film on the first etch stop film; And

Forming a trench by etching the intermetallic insulating layer using a mask pattern;

And a trench forming method for dual damascene interconnection of a semiconductor device using SiH ₄ having a low dielectric constant as the second etch stop layer.

Forming the trench,

Etching the second insulating layer until the second etch stop layer is exposed; And

A second etching step of over-etching the second etching stop layer;

It includes.

In the first and second etching steps, the etching process is performed using a process gas including C ₅ F _{8. In} the first etching step, C ₅ F ₈ and O ₂ gases are supplied at a ratio of 0.5 to 1: 1. In the second etching step, C ₅ F ₈ and O ₂ gas is preferably supplied at a ratio of 1-2: 1.

In the first etching step, C ₅ F _{8 having} 10-25 sccm of process gas while maintaining a pressure of 20-40 mT and a temperature of 10-20 ° C. while applying a source power of 1400-1900 W and a bias power of 1000-1500 W. And 15 to 30 sccm O ₂ and 500 to 1000 sccm Ar are preferable.

In the second etching step, C ₅ F ₈ having 15 to 30 sccm of process gas while maintaining a pressure of 20 to 40 mT and a temperature of 10 to 20 ° C. while a source power of 1000 to 1500 W and a bias power of 1000 to 1500 W are applied. And 10 to 25 sccm O ₂ and 500 to 1000 sccm Ar are preferable.

The etch selectivity with the second etch stop layer is controlled by a ratio of C ₅ F ₈ : O ₂ , and the thickness of the second etch stop layer is 500 to 1500 1 within 10 to 20% of the total intermetallic thickness. It is desirable to.

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings. However, embodiments of the present invention may be modified in many different forms, and the scope of the present invention should not be construed as being limited by the embodiments described below.

2 to 4 are cross-sectional views illustrating a method for forming a trench for dual damascene wiring in a semiconductor device according to the present invention.

First, referring to FIG. 2, a first etch stop layer 14 is formed on a lower insulating layer 10 and a lower metal layer 12 disposed in the insulating layer 10, and a first etch stop layer 14 is formed on the first etch stop layer 14. The first insulating film 16a, the second etch stop film 16b, and the second insulating film 16c are sequentially formed. The first insulating layer 16a, the second etch stop layer 16b, and the second insulating layer 16c form an intermetallic insulating layer 16.

Although not shown, a first capping layer may be formed between the first etch stop layer 14 and the first insulating layer 16a, and a second capping layer may be further formed on the second insulating layer 16c. The lower metal layer 12 may be connected to another lower metal layer or directly connected to an impurity region of the semiconductor substrate.

The lower metal film 12 is a copper (Cu) film, although only two are shown in the drawing, which may be more or only one as an example. The second etch stop layer 16b forms SiH ₄ having a low dielectric constant at a thickness t of 500 to 1500 kPa within a range corresponding to 10 to 20% of the total thickness T of the intermetallic insulating film. The second insulating films 16a and 16c are formed of any one of FSG, BPSG, d-TEOS or USG.

3 and 4, a trench forming mask pattern (not shown) is formed on the second insulating film 16c as a photoresist film pattern. The trenches T1 and T2 are formed by etching the second insulating layer 16c and the second etch stop layer 16b by an etching process using the mask pattern as an etching mask.

In more detail, the etching process for forming the trenches T1 and T2 may include a first etching step of etching the second insulating layer 16c until the second etching stop layer 16b is exposed, and a second etching process. A second etching step of over-etching the stop film 16b is performed.

In the first and second etching steps, etching is performed using a process gas including C ₅ F ₈ and O ₂ , wherein the etching selectivity with the second etching stop layer is C ₅ F ₈ : O ₂ Adjust the ratio of.

First, in the first etching step, the etching is performed while supplying C ₅ F ₈ and O ₂ gas at a ratio of 0.5 to 1: 1.

For example, in the first etching step, C ₅ F ₈ of 10-25 sccm, O ₂ of 15-30 sccm and Ar of 500-1000 sccm are used as a process gas, and a source power of 1400-1900 W and a bias power of 1000-1500 W are applied. Etching is performed while maintaining a pressure of 20-40 mT and a temperature of 10-20 ° C. in one state.

When the first etching step is completed, as shown in FIG. 3, the second etch stop layer 16b is exposed. However, after the first etching step is completed, the second etch stop layer 16b may not be exposed in some trenches T1 due to the non-uniformity of the etching depth, and a micro trench phenomenon (part A) may occur. have.

Therefore, after the first etching step is completed, a second etching step is performed to eliminate the problems caused by nonuniformity (D1 ≠ D2) of the etching depths D1 and D2 and the occurrence of the micro trench phenomenon. Etching is performed while supplying C ₅ F ₈ and O ₂ gas at a ratio of 1 to 2: 1.

For example, in the second etching step, C ₅ F ₈ of 15 to 30 sccm, O ₂ of 10 to 25 sccm, and Ar of 500 to 1000 sccm are used as the process gas, and source power of 1000 to 1500 W and bias power of 1000 to 1500 W are used. Etching is performed while maintaining a pressure of 20-40 mT and a temperature of 10-20 ° C. in the applied state.

As such, when the second etching step is completed, the etching depths D1 ′ and D2 ′ of the trenches T1 and T2 are uniformly formed as shown in FIG. 4, and the micro trench phenomenon is removed.

In addition, since the second etch stop layer 16b is made of SiH ₄ having a low dielectric constant, performance degradation of the device due to RC delay can be suppressed.

Although not shown, a via hole formed inside the trenches T1 and T2 may be formed before or after the trenches T1 and T2, and the via holes and the trenches T1 and T2 may be filled. After the upper metal film is formed of a copper (Cu) film, a conventional chemical mechanical planarization process is performed to complete the dual damascene wiring.

As described above, according to the method for forming a dual damascene wiring trench for a semiconductor device according to the present invention, the second etching stop film used for trench etching is formed of SiH ₄ having a low dielectric constant, thereby deteriorating device characteristics due to RC delay. You can prevent it.

In addition, the trench etching process may include a first etching step of etching the second insulating layer and a second etching step of over-etching the second etching stop layer, thereby suppressing nonuniformity of trench etching depth and occurrence of micro trench phenomenon. There is.

Although the present invention has been described in detail with reference to preferred embodiments, the present invention is not limited to the above embodiments, and various modifications may be made by those skilled in the art within the technical spirit of the present invention. Do.

Claims (9)

Forming a first etch stop layer on the lower metal layer; Forming an intermetallic insulating film including a first insulating film, a second etch stop film, and a second insulating film on the first etch stop film; And Forming a trench by etching the intermetallic insulating layer using a mask pattern; Including; As the second etch stop layer, SiH ₄ having a low dielectric constant is used, Forming the trench, Etching the second insulating layer until the second etch stop layer is exposed; And A second etching step of over-etching the second etching stop layer; Dual damascene wiring trench formation method of a semiconductor device comprising a. delete The method of claim 1, In the first and the second etching step, the etching method using a process gas containing C ₅ F ₈ to etch the dual damascene wiring trench of the semiconductor device. The method of claim 3, wherein And forming a C ₅ F ₈ and O ₂ gas in a ratio of 0.5 to 1: 1 in the first etching step. The method of claim 4, wherein In the first etching step, C ₅ F _{8 having} 10-25 sccm of process gas while maintaining a pressure of 20-40 mT and a temperature of 10-20 ° C. while applying a source power of 1400-1900 W and a bias power of 1000-1500 W. And 15 to 30 sccm O ₂ and 500 to 1000 sccm Ar for dual damascene wiring trench formation method for a semiconductor device. The method according to any one of claims 1 and 3 to 5, The method of forming a dual damascene wiring trench for a semiconductor device, characterized in that in the second etching step, C ₅ F ₈ and O ₂ gas are supplied at a ratio of 1 to 2: 1. The method of claim 6, In the second etching step, C ₅ F ₈ having a process gas of 15 to 30 sccm while maintaining a pressure of 20 to 40 mT and a temperature of 10 to 20 ° C. while applying a source power of 1000 to 1500 W and a bias power of 1000 to 1500 W is applied. And 10 to 25 sccm of O ₂ and 500 to 1000 sccm of Ar, for forming a dual damascene wiring trench for a semiconductor device. The method of claim 7, wherein And forming an etching selectivity ratio with the second etch stop layer in a ratio of C ₅ F ₈ : O ₂ . The method of claim 8, And forming a thickness of the second etch stop layer within a range of 10 to 20% of the total thickness of the intermetallic insulating film.

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