KR100641499B1 - Method for formating contact hole in semiconductor device - Google Patents
Method for formating contact hole in semiconductor device Download PDFInfo
- Publication number
- KR100641499B1 KR100641499B1 KR1020050045260A KR20050045260A KR100641499B1 KR 100641499 B1 KR100641499 B1 KR 100641499B1 KR 1020050045260 A KR1020050045260 A KR 1020050045260A KR 20050045260 A KR20050045260 A KR 20050045260A KR 100641499 B1 KR100641499 B1 KR 100641499B1
- Authority
- KR
- South Korea
- Prior art keywords
- focus
- contact hole
- semiconductor device
- forming
- pattern
- Prior art date
Links
- 238000000034 method Methods 0.000 title claims abstract description 34
- 239000004065 semiconductor Substances 0.000 title claims abstract description 15
- 238000005530 etching Methods 0.000 claims abstract description 13
- 229920000642 polymer Polymers 0.000 claims abstract description 8
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims abstract description 4
- 229910052710 silicon Inorganic materials 0.000 claims abstract description 4
- 239000010703 silicon Substances 0.000 claims abstract description 4
- 239000000758 substrate Substances 0.000 claims abstract description 4
- 238000000151 deposition Methods 0.000 claims description 4
- 230000007423 decrease Effects 0.000 claims description 3
- 229920002120 photoresistant polymer Polymers 0.000 abstract description 6
- 238000013461 design Methods 0.000 abstract description 5
- 238000000059 patterning Methods 0.000 description 3
- 239000010949 copper Substances 0.000 description 2
- 230000003247 decreasing effect Effects 0.000 description 2
- 230000008021 deposition Effects 0.000 description 2
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 1
- 230000006978 adaptation Effects 0.000 description 1
- 229910052802 copper Inorganic materials 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
- 238000011161 development Methods 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 230000000873 masking effect Effects 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 239000007769 metal material Substances 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 230000010363 phase shift Effects 0.000 description 1
- 239000007787 solid Substances 0.000 description 1
- 238000012360 testing method Methods 0.000 description 1
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 description 1
- 229910052721 tungsten Inorganic materials 0.000 description 1
- 239000010937 tungsten Substances 0.000 description 1
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
- H01L21/76816—Aspects relating to the layout of the pattern or to the size of vias or trenches
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3105—After-treatment
- H01L21/311—Etching the insulating layers by chemical or physical means
- H01L21/31144—Etching the insulating layers by chemical or physical means using masks
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
- Drying Of Semiconductors (AREA)
Abstract
Description
도 1은 본 발명에 따른 반도체 소자의 컨택 홀 형성과정을 도시한 도면, 1 is a view illustrating a process of forming a contact hole in a semiconductor device according to the present invention;
도 2는 도 1에 도시된 컨택 홀 형성과정에서 수직 초점을 기준으로 쉬프트시켜 포토 공정이 진행되는 것을 도시한 도면,FIG. 2 is a diagram illustrating a photo process by shifting a vertical focus based on the contact hole forming process illustrated in FIG. 1;
도 3은 본 발명에 따른 반도체 소자의 컨택 홀을 형성할 경우, 포토 공정에서의 초점에 대한 CD 바이어스 량을 도시한 그래프.3 is a graph showing the amount of CD bias with respect to the focus in the photo process when forming the contact hole of the semiconductor device according to the present invention.
본 발명은 반도체 소자의 컨택 홀 형성방법에 관한 것으로, 보다 상세하게 설명하면, 컨택을 패터닝함에 있어서, 감광막(Photo Resist, PR) 패턴 초점을 쉬프트시키는 방식으로 컨택 홀을 형성함으로써, 선폭(Critical Dimension, CD) 바이어스를 감소시킬 수 있는 방법에 관한 것이다. The present invention relates to a method for forming a contact hole in a semiconductor device, and in more detail, in forming a contact, by forming a contact hole in a manner of shifting the focus of the photo resist pattern (PR) pattern, a critical dimension is obtained. , CD).
주지된 바와 같이, 반도체 소자를 제조하는 경우, 점차적으로 그 소자의 초 고집적화에 따라 회로 CD가 감소하고, 반도체 층과 층, 그리고, 패턴과 패턴의 구조가 복잡하게 이루어져 있어 층과 층을 연결하는 컨택의 역할은 매우 중요하다.As is well known, when manufacturing a semiconductor device, the circuit CD gradually decreases due to the ultra-high integration of the device, and the semiconductor layer and the layer, and the pattern and the structure of the pattern are complicated to connect the layers and the layers. The role of the contact is very important.
이러한 컨택은 소자의 크기가 나노기술(Nano tech)로 점점 미세하게 됨에 따라 컨택의 크기 또한 많이 줄어들고 있다. 여기서, 컨택은 텅스텐(W), 구리(Cu) 등의 금속 재료 물질을 사용한다. As these contacts become more and more fine with nano tech, the size of contacts is also decreasing. Here, the contact uses a metal material material such as tungsten (W) or copper (Cu).
상술한 바와 같이, 컨택의 크기가 줄어들고, 그 공정 과정이 복잡해짐에 따라 컨택 홀을 형성하기 위한 디자인 룰이 0.42㎛(0.20/0.22 : 폭/공간) 피치(pitch)일 때, 이를 제작하기 위해서는 식각 CD 바이어스를 고려하여 약 20㎚로 하고, DI CD일 경우, 0.24/0.18㎛(폭/공간)로 타겟팅되어야 한다. As described above, when the size of the contact is reduced and the process is complicated, the design rule for forming the contact hole has a pitch of 0.42 μm (0.20 / 0.22: width / space). In consideration of the etching CD bias, it should be about 20 nm, and in the case of DI CD, it should be targeted to 0.24 / 0.18 μm (width / space).
상술한 바와 같이, DI(Development Image) CD(Critical Dimension)를 0.24/0.18㎛로 타겟팅되도록 구현하기 위해서 248㎚ DUV를 사용하여야만 한다. 그렇지만, 이러한 248㎚ DUV를 사용할 경우, 기존의 이진 마스크(Mask)보다 해결이 개선된 PSM(Phase Shift Masking) 마스크(Mask)를 사용하여야 하며, PSM 마스크(Mask)를 사용할 경우에도 마스킹되는 지역의 PR도 어느 정도 빛이 통과하는 특성 때문에 약 30㎚ 정도 언더 노광 공정을 사용해야 한다. 따라서, 마스크(Mask) CD는 0.27/0.15 ㎛ 정도로 만들어야 하는데, 이럴 경우 홀과 홀 사이 CD 0.15㎛는 그 간격이 너무 작기 때문에 경우에 따라서는 홀과 홀이 붙어버리게 되는 불량이 발생하게 되는 문제점을 갖는다. As described above, a 248 nm DUV should be used to implement a development image (DI) critical dimension (CD) to be 0.24 / 0.18 μm. However, when using such a 248nm DUV, it is necessary to use a PSM (Phase Shift Masking) mask, which has an improved resolution compared to a conventional binary mask, and even when using a PSM mask. PR should also use an under exposure process of about 30 nm because of the light passing through to some extent. Therefore, the mask CD should be made about 0.27 / 0.15 μm. In this case, since the gap between holes and the CD 0.15 μm is too small, there is a problem that holes and holes are stuck in some cases. Have
따라서, 본 발명은 상술한 문제점을 해결하기 위해 안출한 것으로, 그 목적은 컨택을 패터닝함에 있어서, PR 패턴 초점을 일정 크기로 쉬프트시키는 방식으로 컨택 홀을 형성함으로써, 식각 CD 바이어스를 감소시킬 수 있는 반도체 소자의 컨택 홀 형성방법을 제공함에 있다.Accordingly, the present invention has been made to solve the above-described problems, and its object is to form an etch hole in a manner of shifting the PR pattern focus to a certain size in patterning the contact, thereby reducing the etching CD bias. A method of forming a contact hole in a semiconductor device is provided.
이러한 목적을 달성하기 위한 본 발명에 따른 반도체 소자의 컨택 홀 형성방법은 실리콘 기판과 산화막을 순차적으로 형성하며, 상기 형성된 산화막 상에 PR을 도포하는 제1단계와, 상기 도포된 PR을 포토 공정으로 수직 초점을 기준으로 쉬프트시켜 PR 프로파일을 기울어지게 진행하여 PR 패턴을 형성하는 제2단계와, 상기 형성된 PR 패턴 상에 폴리머를 증착하고 식각 공정을 진행하여 CD 바이어스가 감소된 패턴 홀을 형성하는 제3단계를 포함하는 것을 특징으로 한다. The method for forming a contact hole of a semiconductor device according to the present invention for achieving the above object is to form a silicon substrate and an oxide film sequentially, the first step of applying a PR on the formed oxide film, and the applied PR in a photo process A second step of forming a PR pattern by tilting the PR profile by shifting the vertical focus, and depositing a polymer on the formed PR pattern and performing an etching process to form a pattern hole having a reduced CD bias Characterized in that it comprises three steps.
이하, 본 발명의 실시예는 다수개가 존재할 수 있으며, 이하에서 첨부한 도면을 참조하여 바람직한 실시 예에 대하여 상세히 설명하기로 한다. 이 기술 분야의 숙련자라면 이 실시 예를 통해 본 발명의 목적, 특징 및 이점들을 잘 이해하게 될 것이다. Hereinafter, a plurality of embodiments of the present invention may exist, and a preferred embodiment will be described in detail with reference to the accompanying drawings. Those skilled in the art will appreciate the objects, features and advantages of the present invention through this embodiment.
도 1은 본 발명에 따른 반도체 소자의 컨택 홀 형성과정을 도시한 도면이다.1 is a view illustrating a process of forming a contact hole in a semiconductor device according to the present invention.
즉, 도 1a 내지 도 1c를 참조하면, 실리콘 기판(10)상에 산화막(20)을 순차적으로 형성하며, 이 형성된 산화막(20)상에 PR을 도포(30)한다. That is, referring to FIGS. 1A to 1C, the
이후, 도 1d를 참조하면, 포토 공정을 진행할 경우, 도 2에 도시된 바와 같이, 수직 초점을 기준으로 -0.1 내지 -0.3㎛의 범위 내에 속하는 크기(40)로 쉬프트시켜 PR 프로파일을 기울어지게(Slope) 포토 공정을 진행하여 PR 패턴(30-1)을 형성한 다음에 식각을 위한 폴리머(35)를 증착한다. 여기서, PR 프로파일은 "-" 초점일수록 네가티브(Nagative)이고, "+" 초점일수록 포지티브(Positive) 프로파일을 형성한다. 1D, when the photo process is performed, as illustrated in FIG. 2, the PR profile is tilted by shifting to a
끝으로, 도 1e와 같이, PR 패턴(30-1)상에 식각 폴리머가 증착된 상태에서, 식각 공정을 진행하면 CD 바이어스가 감소된 패턴 홀(45)을 형성할 수 있다. Lastly, as shown in FIG. 1E, when the etching polymer is deposited on the PR pattern 30-1, the etching process may form a
한편, 도 3을 참조하면, 도 3은 본 발명에 따른 반도체 소자의 컨택 홀을 형성할 경우, 포토 공정에서의 초점에 대한 CD 바이어스 량을 도시한 그래프이다. Meanwhile, referring to FIG. 3, FIG. 3 is a graph showing the amount of CD bias with respect to a focus in a photo process when forming a contact hole of a semiconductor device according to the present invention.
즉, 초점에 따른 CD 바이어스 량은 동일한 에너지(mJ) 조건에서 "-" 초점일수록 CD 바이어스 량이 감소하고, "+" 초점일수록 CD 바이어스 량이 증가하게 되는 것을 볼 수 있다. 그리고, 초점에 따른 CD 바이어스 량은 PR 측면의 손실 정도와 PR 측면에 식각 폴리머가 증착되는 정도에 의하여 그 량이 결정된다.That is, the CD bias amount according to the focus may be seen to decrease the CD bias amount as the "-" focus under the same energy (mJ) conditions, the CD bias amount increases as the "+" focus. The amount of CD bias according to the focus is determined by the degree of loss on the PR side and the amount of etching polymer deposited on the PR side.
특히, 산화막 식각일 경우, 물리적인 식각이 주요 펙터로 작용하여 폴리머 증착 정도가 CD 바이어스 량을 상대적으로 크게 좌우하게 된다. 즉, PR 프로파일이 "-" 초점인 네가티브한 상태일 때는 입체각이 적기 때문에 에천트가 산화막에 반응할 확률이 적어지며, 그 만큼 폴리머 증착량도 적어지게 됨으로써 CD 바이어스 량이 감소하게 된다. In particular, in the case of oxide etching, physical etching acts as a major factor, and thus the degree of polymer deposition greatly influences the CD bias amount. In other words, when the PR profile is negative in the "-" focus, the solid angle is small, so the probability of the etchant reacting to the oxide film is reduced, and the amount of polymer deposition is also reduced, thereby decreasing the CD bias amount.
더불어, 도 3에 도시된 그래프의 테스트 결과를 이용하면 바이어스가 없는 식각 공정도 가능하기 때문에 디자인 룰을 0.20/0.22㎛로 구현하기 위해서 식각 바이어스를 고려할 필요가 없기 때문에 DI CD도 0.20/0.22㎛로 구현 가능하고, 이 DI CD를 구현하기 위해서 PSM 마스크(Mask)를 사용할 경우에도 마스크(Mask) CD 마진을 0.23/0.19㎛로 확보할 수 있어 홀과 홀이 붙어버리게 되는 기존의 불량이 발생하지 않게 된다. In addition, since the test results of the graph shown in FIG. 3 enable the bias-free etching process, the DI CD is also reduced to 0.20 / 0.22㎛ since the etching bias is not necessary to implement the design rule at 0.20 / 0.22㎛. Even when using a PSM mask to implement this DI CD, the mask CD margin can be secured to 0.23 / 0.19㎛, so that existing defects that cause holes and holes to stick together do not occur. do.
따라서, 컨택을 패터닝함에 있어서, PR 패턴 초점을 일정 크기로 쉬프트시켜 PR 프로파일을 기울어지게(Slope) 포토 공정을 진행하는 방식으로 컨택 홀을 형성함으로써, 컨택의 크기가 줄어들고, 그 공정 과정이 복잡해질 경우에도 CD 바이어스를 최소화할 수 있어 PSM 마스크(Mask) 적용시 보다 안정적인 마스크(Mask) CD 마진을 확보할 수 있는 디자인 CD를 구현할 수 있다. Accordingly, in patterning the contact, the contact hole is formed by shifting the focus of the PR pattern to a predetermined size to form a photo process to incline the PR profile, thereby reducing the size of the contact and making the process complicated. In this case, the CD bias can be minimized, and a design CD can be realized to obtain a more stable mask CD margin when applying a PSM mask.
또한, 본 발명의 사상 및 특허청구범위 내에서 권리로서 개시하고 있으므로, 본원 발명은 일반적인 원리들을 이용한 임의의 변형, 이용 및/또는 개작을 포함할 수도 있으며, 본 명세서의 설명으로부터 벗어나는 사항으로서 본 발명이 속하는 업계에서 공지 또는 관습적 실시의 범위에 해당하고 또한 첨부된 특허청구범위의 제한 범위 내에 포함되는 모든 사항을 포함한다. In addition, since the present invention is disclosed as a right within the spirit and claims of the present invention, the present invention may include any modification, use and / or adaptation using general principles, and the present invention as a matter deviating from the description of the present specification. It includes everything that falls within the scope of known or customary practice in the art to which it belongs and falls within the scope of the appended claims.
상기에서 설명한 바와 같이, 본 발명은 컨택을 패터닝함에 있어서, PR 패턴 초점을 일정 크기로 쉬프트시켜 PR 프로파일을 기울어지게(Slope) 포토 공정을 진행하는 방식으로 컨택 홀을 형성함으로써, 컨택의 크기가 줄어들고, 그 공정 과정이 복잡해질 경우에도 CD 바이어스를 최소화할 수 있어 PSM 마스크(Mask) 적용시 보다 안정적인 마스크(Mask) CD로 디자인 CD를 구현할 수 있는 효과가 있다. As described above, in the present invention, in contact patterning, a contact hole is formed by shifting the PR pattern focus to a predetermined size to form a contact hole in a manner in which a PR profile is sloped, thereby reducing the size of the contact. In addition, the CD bias can be minimized even when the process is complicated, so that the design CD can be realized as a more stable mask CD when applying a PSM mask.
Claims (5)
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR1020050045260A KR100641499B1 (en) | 2005-05-27 | 2005-05-27 | Method for formating contact hole in semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR1020050045260A KR100641499B1 (en) | 2005-05-27 | 2005-05-27 | Method for formating contact hole in semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| KR100641499B1 true KR100641499B1 (en) | 2006-10-31 |
Family
ID=37621390
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| KR1020050045260A KR100641499B1 (en) | 2005-05-27 | 2005-05-27 | Method for formating contact hole in semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| KR (1) | KR100641499B1 (en) |
-
2005
- 2005-05-27 KR KR1020050045260A patent/KR100641499B1/en not_active IP Right Cessation
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US8101338B2 (en) | Method of forming micro pattern of semiconductor device | |
| KR100902711B1 (en) | Fabricating method for semiconductor device | |
| US7883822B2 (en) | Graded lithographic mask | |
| US7316872B2 (en) | Etching bias reduction | |
| KR100907898B1 (en) | Semiconductor device manufacturing method | |
| US7354682B1 (en) | Chromeless mask for contact holes | |
| US20090202925A1 (en) | Photomask defect correction method, photomask manufacturing method, phase shift mask manufacturing method, photomask, phase shift mask, photomask set, and pattern transfer method | |
| JP2004062088A (en) | Photomask, method for designing the same and method for manufacturing semiconductor device by using the same | |
| KR100641499B1 (en) | Method for formating contact hole in semiconductor device | |
| JP2005159264A (en) | Method of forming pattern and method of manufacturing semiconductor device | |
| CN101593725A (en) | The formation method of contact hole | |
| KR100861169B1 (en) | Method for manufacturing semiconductor device | |
| KR100917820B1 (en) | method of forming contact hole in semiconductor device | |
| TWI694309B (en) | Method of manufacturing semiconductor device | |
| KR100586549B1 (en) | Photo mask and method for manufacturing pattern by using it | |
| US6858375B2 (en) | Method for forming resist pattern | |
| KR20090086821A (en) | Method for forming semiconductor device | |
| US20210151321A1 (en) | Forming contact holes using litho-etch-litho-etch approach | |
| KR100586531B1 (en) | Method for settlement of etching time of pattern by pattern density | |
| Kim et al. | The improvement of DOF for sub-100nm process by focus scan | |
| US7776513B2 (en) | Method of manufacturing semiconductor device | |
| KR20100026732A (en) | Method for fabricating the semiconductor device | |
| KR20100011489A (en) | Method for forming the contact hole of semiconductor device | |
| JPH11251536A (en) | Manufacture of semiconductor device | |
| JP2007123356A (en) | Method of manufacturing semiconductor device |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| A201 | Request for examination | ||
| E902 | Notification of reason for refusal | ||
| E701 | Decision to grant or registration of patent right | ||
| GRNT | Written decision to grant | ||
| FPAY | Annual fee payment |
Payment date: 20110920 Year of fee payment: 6 |
|
| LAPS | Lapse due to unpaid annual fee |