KR100630662B1 - Semiconductor memory device having a redundant control circuit - Google Patents

Abstract

A redundancy control circuit of a semiconductor memory device is disclosed in which a repaired cell address is known even in a packaged state when a normal cell is replaced with a redundant cell. The redundancy control circuit of the present invention includes a circuit for a test mode. That is, when the redundancy control signal is enabled when the semiconductor memory device is tested, the redundant cell selecting means is forcibly disabled and the normal cell selecting means for selecting the normal cell is enabled. If the normal cell by the normal cell selection signal fails, it can be seen from the package state that the cell corresponding to the input address is a repaired cell.

Description

Redundant control circuit of semiconductor memory device

1 is a block diagram of a conventional redundancy control circuit.

2 is a block diagram illustrating a redundancy control circuit according to an embodiment of the present invention.

3 is a block diagram of redundant cell selecting means of FIG.

4 is a circuit diagram specifically illustrating a switching unit of FIG. 3.

5 is a circuit diagram specifically illustrating a redundant cell driver of FIG. 3.

6 is a circuit diagram specifically illustrating a programming unit of FIG. 3.

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor memory device, and more particularly to a redundant control circuit capable of replacing a defective normal cell with a redundant cell.

BACKGROUND OF THE INVENTION The need for redundancy cells in semiconductor memory devices, particularly dynamic random access memory, is increasing as memory devices become more integrated.

In other words, densification of the pattern of the memory device causes an increase in the defective rate and increases the possibility of lowering the manufacturing yield.

Therefore, the semiconductor memory device generally includes a spare memory cell, that is, a redundant cell. As the defective cell is replaced by the redundant cell, the manufacturing yield of the semiconductor memory device increases.

On the other hand, the redundancy control circuit programs the address of the cell in which the defect has occurred through the cutting of the fuse. When an address identical to the address programmed by such a redundancy control circuit is input from the outside, a defective cell is not selected and a redundant cell corresponding to the defective cell is selected.

1 shows a conventional redundancy control circuit. The input address ADD is input to the normal cell selecting means 11 for selecting the normal cell and the redundant cell selecting means 12 for selecting the redundant cell via the buffer means 10.

When the normal cell is failing, the redundant cell selecting means 12 is enabled. The normal cell selecting means 11 for selecting the normal cell is then disabled, so that the redundant cell is selected instead of the normal cell. When the normal cell has not failed, the redundant cell selector 12 is not enabled.

However, the existing redundancy control circuit has a problem that it is impossible to know whether a cell corresponding to an address is repaired in a packaged state when a defective normal cell is replaced with a redundant cell.

It is an object of the present invention to provide a redundancy control circuit so that a repaired address can be known even in a package state.

One aspect of the present invention for achieving the technical problem to be achieved by the present invention relates to a redundancy control circuit. The redundancy control circuit of the present invention comprises: buffer means 21 for buffering an input address ADD and providing an internal address signal DRA; Redundant cell selecting means (23) for generating a redundant cell selection signal (REDi) for selecting the redundant cell in response to the internal address (DRA) in a redundant mode; And a normal cell selecting means for generating a normal cell selection signal (NCSi) for selecting the normal cell in response to the internal address (DRA) and being disabled in response to the activation of the redundant cell selection signal (REDi). (22) is provided. The redundant cell selecting means 23 may be disabled in response to the redundancy control signal PIRE even in the redundant mode.

In order to fully understand the present invention, the operational advantages of the present invention, and the objects achieved by the practice of the present invention, reference should be made to the accompanying drawings which illustrate preferred embodiments of the present invention and the contents described in the accompanying drawings.

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings. For each figure, like reference numerals denote like elements.

2 is a block diagram illustrating a redundancy control circuit according to an embodiment of the present invention. The redundancy control circuit according to the embodiment of the present invention includes a buffer means 21, a normal cell selecting means 22, a redundant cell selecting means 23, and a redundancy controller 24.

The buffer means 21 buffers the input address signal ADD to provide the internal address signal DRA. The internal address signal DRA is provided to the normal cell selecting means 22 and the redundant cell selecting means 23.

The redundant cell selection means 23 generates a redundant cell selection signal REDi for selecting a redundant cell in response to the internal address signal DRA in a redundant mode in which a redundant cell is selected instead of a normal cell. do.

The normal cell selecting means 22 generates a normal cell selection signal NCSi for selecting a normal cell in response to the internal address signal ADD in a normal mode in which a normal cell is selected. The normal cell selecting means 22 is disabled in the 'redundant mode'.

The redundancy control unit 24 may disable the redundant cell selecting unit 23 in response to an internal test command signal (ITC) in a predetermined test mode. Occurs.

3 is a block diagram of the redundant cell selecting means 23 of FIG. Referring to FIG. 3, the redundant cell selecting unit 23 includes a switching unit 31, a redundant cell driver 32, and a programming unit 33. The switching unit 31 generates a master signal MASTER in response to a power up signal. The redundant cell driver 32 generates programming control signals PFU and PFD in response to the master signal MASTER and the redundancy control signal PIRE. The programming unit 33 generates a redundant cell selection signal REDi in response to the programming control signals PFU and PFD and the internal address signal DRA.

4 is a circuit diagram specifically illustrating the switching unit 31 of FIG. 3. First, when a power up state occurs, a power-up driving pulse signal VCCHP is applied to the gate of the NMOS transistor NMOS0 to which the drain terminal is connected to the first fuse FUS0. Is applied to logic 'high' and becomes logic 'low' after a certain pulse interval. Accordingly, in the 'normal mode' in which the first fuse FUS0 is not disconnected, the node NOD1 becomes logic 'high', and the node NOD2 that is the output of the inverter 41 becomes logic 'low'. . The output signal of the NMOS transistor NMOS1 having a gate connected to the node NOD2 and a drain connected to the node NOD1 becomes a logic 'high'. The node NOD3, which is the output of the inverter 42, is logic 'high', and the master signal MASTER, which is the output of the inverter 43, is logic 'low'.

Meanwhile, in the 'redundant mode' in which the first fuse FUS0 is cut in the power-up state, the NMOS transistor NMOS0 remains turned on during the period in which VCCHP is logic 'high'. After that, it is turned off, and the PMOS transistor PMOS0 is turned off. Therefore, when the NMOS transistor NMOS0 is turned on, the node NOD1 transitions to logic 'low', and the nodes NOD2 and NOD3 become logic 'high' and logic 'low', respectively. When the transistor NMOS0 is turned off, the state is maintained by the NMOS transistor NMOS1 and the inverter 41. Thus, the master signal MASTER becomes a logic 'high'.

FIG. 5 is a circuit diagram specifically showing the redundant cell driver 32 of FIG. 3. In FIG. 5, the operation of the redundant cell driver 32 in the state where the fuse FUS2 is not cut and the fuse FUS2 is cut while the redundancy control signal PIRE is not enabled is described in detail.

In the case of the 'normal mode' in which the fuse FUS0 of FIG. 4 is not blown, that is, the master signal MASTER is in the logic 'low' state, the output signal of the node NOD4 is determined by the inverter 51 to be logic 'high'. Becomes' The NOR gate 52 receives a redundancy control signal PIRE having a logic 'low' and a signal of a node NOD4 having a logic 'high', respectively. Accordingly, the signal of the node NOD5 becomes logic 'low' so that the NMOS transistor NMOS2 remains turned off.

In addition, the redundancy control signal PIRE having a logic 'low' state becomes a logic 'high' by the inverter 53. Therefore, since logic 'high' is applied to the gate terminal of the PMOS transistor PMOS2, the PMOS transistor PMOS2 is turned off. In addition, since the PMOS transistor PMOS1 is turned on, the signal of the node NOD6 becomes logic 'high'. Accordingly, the first program control signal PFU is logic 'low' by the inverter 54 and the second program control signal PPF is logic 'high'.

Even when the master signal MASTER is logic 'high', when the fuse FUS2 is disconnected, the first program control signal PFU is logic 'low' and the second program control signal PFD is logic 'high'. to be.

Subsequently, the operation of the redundant cell driver 32 in the state where the fuse FUS1 is cut and the fuse FUS2 is not cut is described. Since the redundancy control signal PIRE is logic 'low', the PMOS transistor PMOS2 remains turned off.

First, the operation of the redundant cell driver 32 when the master signal MASTER is logic 'low' is as follows. Since the master signal MASTER is inverted by the inverter 51, the signal of the node NOD4 becomes logic 'high'. In response to the redundancy control signal PIRE and the signal of the node NOD4, the logic of the node NOD5 is 'low' and the NMOS transistor NOMS2 is turned off. The signal PFU and the second program control signal PFD maintain their existing state.

Second, the fuse FUS0 of FIG. 4 is cut, and the operation of the redundant cell driver 32 in the 'redundant mode' in which the master signal MASTER is logic 'high' is as follows. Since the master signal MASTER is inverted by the inverter 51, the signal of the node NOD4 becomes logic 'low'. In response to the redundancy control signal PIRE and the signal of the node NOD4, the signal of the node NOD5 is logic 'high' and the NMOS transistor NOMS2 is turned on. Therefore, since the signal of the node NOD6 becomes logic 'low', the first program control signal PFU becomes logic 'high' and the second program control signal PFD becomes logic 'low'.

Third, the operation of the redundant cell driver 32 in which the redundancy control signal PIRE is in a logic 'high' state in the 'redundant mode' will be described below. Since the redundancy control signal PIRE is inverted by the inverter 53, the PMOS transistor PMOS2 remains turned on. Therefore, since the signal of the node NOD6 maintains a logic 'high', the first program control signal PFU is inverted by the inverter 54 so that the logic 'low' and the second program control signal PFD are logic 'high'. 'to be.

FIG. 6 is a circuit diagram specifically illustrating the programming unit 33 of FIG. 3. The predetermined programming fuse 62 embedded in the unit programming unit 61 of FIG. 6 can program an address of a cell in which a defect is generated by cutting a fuse.

First, the operation of the unit program unit 61 when the master signal MASTER is logic 'low' is described in detail. As described above, in the 'normal mode', the master signal MASTER is a logic 'low'. Therefore, the first program control signal PFU is logic 'low' and the second program control signal PPF is logic 'high'.

Therefore, even if the same address as the address programmed by the programming fuse 62 is input from the internal address DRA, the first program control signal PFU is applied to any of the NMOS transistors NMOS12, NMOS13, NMOS14 or NMOS15. Neither can turn on. However, since the second program control signal PFD turns on the NMOS transistor NMOS11, the signal of the node NOD7, which is the output of the unit programming unit 61, is logic 'low'. The NAND gate 63 receives signals of nodes NOD7 that are logic 'low'. Therefore, the signal of the node NOD8 becomes a logic 'high' and the signal of the node NOD8 is inverted by the inverter 64, so that the redundant cell selection signal REDi becomes a logic 'low' and instead of the redundant cell. The normal cell is selected.

Next, the operation of the unit programming unit 61 is described in detail. As described above, in the redundant mode, the master signal MASTER is a logic high. Therefore, the first program control signal PFU is logic 'high' and the second program control signal PFD is logic 'low'.

Therefore, when the same address as that programmed by the programming fuse 62 is input, the first program control signal PFU turns on at least one of the NMOS transistors NMOS12, NMO S13, NMOS14 or NMOS15. . However, since the second program control signal PFD does not turn on the NMOS transistor NMOS11, the signal of the node NOD7, which is the output of the unit programming unit 61, is logic 'high'. The NAND gate 63 receives signals of the nodes NOD7 that are logic 'high'. Thus, the signal of the node NOD8 becomes logic 'low' and the signal of the node NOD8 is inverted by the inverter 64 so that the redundant cell selection signal REDi becomes the logic 'high' and is redundant instead of the normal cell. The cell is selected.

Subsequently, when the redundancy control signal PIRE is enabled, as described above, the first program control signal PFU is logic 'low' and the second program control signal PPF is logic 'high'. Thus, as in the case of the 'normal mode', the redundant cell selection signal REDi becomes a logic 'low'. Therefore, even in the 'redundant mode', when the redundancy control signal PIRE is enabled, the normal cell is selected as described above.

In the test of the semiconductor memory device, when the redundancy control signal PIRE is enabled, the redundant cell selecting means 23 is forcibly disabled and the normal cell selecting means 22 for selecting the normal cell is enabled. .

Although the present invention has been described with reference to one embodiment shown in the drawings, this is merely exemplary, and those skilled in the art will understand that various modifications and equivalent other embodiments are possible therefrom.

Therefore, the true technical protection scope of the present invention will be defined by the technical details of the appended claims.

     When the normal cell by the normal cell selection signal NCSi fails, it is possible to know whether the cell corresponding to the input address is a repaired cell even in the package state.

Claims (3)

A semiconductor memory device capable of replacing a defective normal cell with a redundant cell, Buffer means for buffering an input address signal and providing an internal address signal; Redundant cell selection means for generating a redundant cell selection signal for selecting the redundant cell in response to the internal address signal; And And a normal cell selection means for generating a normal cell selection signal for selecting the normal cell in response to the internal address signal and being disabled in response to activation of the redundant cell selection signal. In the test mode, the redundant cell selecting means is disabled in response to the redundancy control signal. The redundancy control circuit of claim 1, further comprising a redundancy control unit activated by a test command signal to generate the redundancy control signal. The method of claim 1, wherein the redundant cell selection means A switching unit for generating a master signal activating in response to the cutting of the first fuse; A redundant cell driver which is enabled and activated in response to the master signal to generate a programming control signal, and disabled in response to activation of the redundancy control signal; And A programming unit which selects the redundant cell by cutting a predetermined programming fuse when the response is enabled in response to the programming control signal, and activates the internal address corresponding to the selected redundant cell to generate the redundant cell selection signal Redundancy control circuit comprising a.

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