KR100621033B1 - Memory access control signal generating method for operating by high-speed - Google Patents

Abstract

The present invention provides a fast memory access operation to achieve a faster memory access operation by generating a control signal in consideration of only the time necessary for SRAM control during the write and scan read operation in the memory access control signal generation circuit for high speed operation. A method for generating a memory access control signal, the method for generating a memory access control signal for a high speed operation, the method comprising: (1) generating an internal signal R22 for informing a write enable state in response to a command input from an external source; ; And (2) outputting a write enable signal when the internal signal R22 is at a high level to perform a write function, and performing a scan function when the internal signal R22 is at a low level. It features.

Display Driver Icy, High Speed, Memory Access, Control Signal

Description

Memory access control signal generation method for high speed operation {MEMORY ACCESS CONTROL SIGNAL GENERATING METHOD FOR OPERATING BY HIGH-SPEED}

1 is a block diagram for conceptually explaining a configuration of an LCD driver IC for accessing a memory;

2 is a timing diagram for generating a memory access control signal according to a conventional method in a memory access control signal generator;

3 is a timing diagram for generating a memory access control signal in a memory access control signal generator for high speed operation according to the present invention.

The present invention relates to a method for generating a memory access control signal for high speed operation.

In particular, in the memory access control signal generation circuit for high speed operation, a control signal is generated considering only the time necessary for SRAM control in a write and scan read operation, so that a faster memory access is possible. An access control signal generation method.

In general, the memory structure used in the LCD driver IC (hereinafter, abbreviated as 'LDI') should be written while the scan operation is performed. Addresses for write and scan operations are made through a single word line, and data that has been previously stored when an uncontrolled write / scan address is passed to the SRAM. Causes a problem that is lost.

In order to accurately display the LCD on the LCD using LDI's large-capacity SRAM, and to write accurate data to the SRAM embedded in the LDI and to support higher quality video, a scan address is used. ), A write address, a scan enable signal (SEN), and a write enable signal (WEN) can be quickly controlled to write at a high speed.

First, the signal shown in FIG. 2 is described before describing the prior art with reference to FIGS. 1 and 2 as follows.

The W_CK signal is an internally generated signal for write synchronization, WADDR is a write address for writing display data, SADDR is a scan address for scanning display data, and PRE_SEN signal is a scan enable for scanning display data. As a signal capable of generating a signal, a SEN signal is generated by combining with the XA_SEL signal.

The XA_SEL signal is a WADDR or SADDR selection signal, the XADDR is a write address WADDR or a scan address SADDR selected by the XA_SEL signal, and the WEN signal is a display data write enable signal.

The SEN signal is a display data scan enable signal.

In the conventional write / scan method, as illustrated in FIGS. 1 and 2, the memory control signal generator 100 first generates a write clock signal W_CK and uses the write clock signal W_CK. The write address signal WADDR for writing data to the memory 200 is generated.

Also, the memory control signal generator 100 generates a scan address SADDR and a prescan enable signal PRE_SEN using an internal oscillator clock.

In this case, the write address WADDR and the scan address SADDR have different synchronizations, and the two signals are transmitted to the memory through a line having one address.

Accordingly, the memory control signal generator 100 arbitrarily generates the reference signal XA_SEL for outputting the write address and the scan address, and outputs the write address WADDR in the high level section of the reference signal XA_SEL. The scan address SADDR is output in the low level section of the reference signal XA_SEL.

In addition, the memory control signal generator 100 has a predetermined setup time and hold time while each address is changed, and the scan enable signal WEN for write and scan for scan are performed. Outputs the enable signal SEN.

At this time, the setup time and hold time are designed in consideration of the time required for the actual SRAM access operation, but additional setup time and hold time are required for more stable circuit operation. In fact, the speed to be written to the memory must be taken into consideration until scanning, and since it gives more margin than the timing required by the actual memory, the speed to be written to the memory is inevitably slowed down.

In the timing diagram of FIG. 2, A and B represent an address setup time for a scan operation and an address setup time for a write operation, respectively, and C and D respectively represent an address hold time for a scan operation and an address for a write operation. The hold time is shown.

The four timings denoted by A, B, C, and D are arbitrarily generated by a delay in the memory control signal generator 100, and the timings are generated at target values according to the structure and wiring structure of the physical GRAM. Deviations can occur and are typically designed to have more timing than is actually needed.

Thus, as described above, since the memory access speed decreases, efforts to remove unnecessary timing added when a memory control signal is generated are required.

The present invention has been made in response to the above requirements, and an object of the present invention is to generate a control signal in consideration of only the time necessary for SRAM control during write and scan read operations in a memory access control signal generation circuit for high speed operation. It is to provide a memory access control signal generation method for a high speed operation to achieve a faster memory access operation.

In addition, an object of the present invention is to provide a memory access control signal generation method for a high-speed operation to control the SRAM used in the LDI at a faster speed to implement a low power and high quality video.

One embodiment of the present invention proposed to solve the above technical problem, in the memory access control signal generation method for high speed operation, (1) for informing the write enable state in response to a command input from the outside; Generating an internal signal R22; And (2) a write enable signal is output when the internal signal R22 is high level to perform a write function, and a write scan enable signal is output when the internal signal R22 is low level to provide a scan function. Characterized in that it comprises a step to be performed.

In addition, step (2) may include: (2-1) enabling the XA_SEL signal to a high level at the positive edge of the PRE_XAS signal; (2-2) disabling the XA_SEL signal to a low level at the negative edge of the write progress signal BUSY_W (write / read busy) generated in the memory; (2-3) selecting the display data write address or the display data read address in response to the XA_SEL signal; (2-4) generating a PRE_WEN signal at the positive edge of the XA_SEL signal; (2-5) When the AD_BUSY signal is generated from the memory due to the X-address change, masking the PRE_WEN signal to generate the write enable signal WEN, and then secure the write address setup time or the read address setup time. ; (2-6) checking the low level section of PRE_SEN at the negative edge of the XA_SEL signal, and generating a SEN_INT signal at the first low level section; (2-7) generating a scan enable signal SEN by masking with an AD_BUSY signal and securing a scan address setup time; (2-8) If the internal signal R22 is at a low level, it is determined that the write function or the read function is not being performed, and outputs a scan enable signal SEN using the PRE_SEN signal. It is characterized by determining the motivation.

Hereinafter, a method of generating a memory access control signal for high speed operation will be described in detail with reference to the accompanying drawings.

3 is a timing diagram for generating a memory access control signal in a memory access control signal generator for high speed operation according to the present invention.

Referring to the signal illustrated in the timing diagram of FIG. 3, first, the R22 signal is a memory access enable signal for writing display data to an internal memory, and the PRE_SEN signal is a scan enable signal for scanning a memory, and XA_SEL Generates SEN_INT signal in combination with signal.

The XA_SEL signal is an X-address selection signal for scanning or writing, the AD_BUSY signal is a signal indicating a X-address step section (high level section), and the PRE_WEN signal is a write enable signal for writing the memory 200. As a result, the WEN signal is generated in combination with the AD_BUSY signal.

The BUSY_W signal is a signal (High section) indicating that the internal memory 200 is accessing the internal memory for writing display data. The SEN_INT signal is a signal generated by a combination of the PRE_SEN signal and the XA_SEL signal. A SEN signal is generated in combination with the signal, where the WEN signal is a write enable signal for writing display data, and the SEN signal is a scan enable signal for scanning display data.

In addition, the configuration applied to the present invention includes a memory control signal generator and a memory as in the prior art, and the memory control signal generator considers only the time necessary for SRAM control as compared to the memory control signal generator applied to the prior art. The function has been enhanced to generate control signals. Accordingly, in describing the detailed description of the present invention, the names and reference numerals of the elements shown in FIG. 1 will be used.

As shown in FIGS. 1 and 3, the memory control signal generator 100 of an actual LDI has a write function of inputting display data into a memory through a bidirectional data bus, which in turn is bidirectional. It has a read function that reads into the data bus and a scan read function that outputs one line to display the display data written to the memory.

 Here, the write function and the read function may not be performed at the same time, but the write function and the scan function may occur at the same time, and the read function and the scan function may also be performed at the same time.

That is, as shown in FIG. 3, the memory control signal generator 100 generates an internal signal R22 for indicating a write enable state in response to a command input from an external MPU controlling the LDI. When the internal signal R22 is at a high level, it indicates that it is in a write enable state. Accordingly, the memory control signal generator 100 performs a write function in a high section of the internal signal and a scan read function in a low section. That is, an instruction R22 for enabling an external MPU (other control unit) to enable the write or read function of the LDI so that the display data can be written or read in the internal memory 200. Outputs

In this case, the scan function may be generated again in the next frame and performed, but since write data is input only once, when the write function and the scan read function are simultaneously generated, the memory control signal generator 100 ) Gives priority to the write function so that it is performed first.

As described above, the memory 200 needs only the write progress signal BUSY_W to check whether the write function is terminated. In this case, the scan function may be excluded. As a result, the maximum write speed can be referred to as the operation time until immediately before the scan function is performed.

In detail, the memory control signal generator 100 enables the XA_SEL signal to a high level at the positive edge of the PRE_XAS signal.

The memory control signal generator 100 disables the XA_SEL signal to a low level at the negative edge of the write progress signal BUSY_W (write / read busy) generated in the memory 200.

The memory control signal generator 100 selects the display data write address or the display data read address using the XA_SEL signal.

The memory control signal generator 100 generates a low level PRE_WEN signal at the positive edge of the XA_SEL signal. At this time, the low level section of the PRE_WEN signal is generated to be shorter than the high level section of the XA_SEL signal.

The RRE_WEN signal is an enable signal for writing to the internal memory 200 and is generated without considering a setup time with the XADDR.

The RRE_WEN signal generates a WEN signal in combination with the AD_BUSY signal to secure a setup time with the XADDR. The reason why the low level section of the PRE_WEN signal should be shorter than the high level section of the XA_SEL signal is to prevent the hold time problem when distinguishing whether it is a write address or a scan address using the XA_SEL signal. It is for. That is, when the low level section of the PRE_WEN signal is longer than the high level section of the XA_SEL signal, a problem may occur in the hold time with the XADDR (write address or scan address).

When the AD_BUSY signal is generated from the memory 200 due to the X-address change, the memory control signal generator 100 masks the PRE_WEN signal to generate a write enable signal WEN to generate a write address setup time or Secure the read address setup time.

The memory control signal generator 100 checks the low level section of the PRE_SEN signal at the negative edge of the XA_SEL signal, and causes the SEN_INT signal to be generated in the first low level section.

The memory control signal generator 100 masks the AD_BUSY signal to generate a scan enable signal SEN, and secures a scan address setup time.

Meanwhile, when the internal signal R22 is at the low level, the memory control signal generator 100 determines that the write function or the read function is not performed, and outputs a scan enable signal SEN by using the PRE_SEN signal.

By accessing the memory 200 as described above, it is dependent on the AD_BUSY signal and the write progress signal BUSY_W, which are signals output from the actual memory. That is, the memory control signal generator 100 determines the write and scan synchronization using the AD_BUSY signal and the write progress signal BUSY_W.

According to the present invention having the above-described configuration and operation and a preferred embodiment, the control signal is generated in consideration of only the time necessary for SRAM control during the write and scan read operation in the memory access control signal generation circuit for high speed operation. This has the effect of enabling fast memory access operations.

Accordingly, the present invention is effective to control the SRAM used in the LDI at a faster speed to implement a low power and high quality video.

Claims (2)

A memory access control signal generation method for high speed operation, (1) generating an internal signal R22 for indicating a write enable state in response to a command input from the outside; And (2) outputting a write enable signal when the internal signal R22 is high level to perform a write function, and performing a scan function when the internal signal R22 is low level; Memory access control signal generation method for a high speed operation, characterized in that consisting of. According to claim 1, wherein step (2), (2-1) enabling the XA_SEL signal to a high level at the positive edge of the PRE_XAS signal; (2-2) disabling the XA_SEL signal to a low level at the negative edge of the write progress signal BUSY_W (write / read busy) generated in the memory; (2-3) selecting the display data write address or the display data read address using the XA_SEL signal; (2-4) generating a PRE_WEN signal at the positive edge of the XA_SEL signal; (2-5) When the AD_BUSY signal is generated from the memory due to the X-address change, masking the PRE_WEN signal to generate the write enable signal WEN, and then securing the write address setup time or the read address setup time. ; (2-6) checking a low level section of the PRE_SEN signal at the negative edge of the XA_SEL signal, and generating a SEN_INT signal at the first low level section; (2-7) generating a scan enable signal SEN by masking with an AD_BUSY signal and securing a scan address setup time; And (2-8) outputting a scan enable signal SEN using the PRE_SEN signal when the internal signal R22 is at a low level; The memory access control signal generation method for a high-speed operation, characterized in that it comprises a to determine the write and scan synchronization.

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