KR100619567B1 - Semiconductor device - Google Patents

Abstract

A semiconductor device capable of absorbing heat stress effectively, a method of manufacturing the same, a circuit board, and an electronic device. The semiconductor element 12 having the electrodes 14, the passivation film 11 provided on the surface of the semiconductor element 12 to avoid at least a part of each electrode 14, and the surface on which the passivation film 11 is formed. Above, the conductive foil 22 provided at predetermined intervals in the thickness direction, the external electrode 26 formed on the conductive foil 22, the passivation film 11 and the conductive foil 22, The intermediate layer 16 which is formed in between and supports the conductive foil 22 and the wiring 18 which electrically connects the electrode 14 and the conductive foil 22 are included in the intermediate layer 16. Under the region including the junction with the external electrode 26 in (22), a concave portion 16a is formed in which the opening region widens as the passivation film 11 side approaches the conductive foil 22 side. It is.

Semiconductor element, conductive foil, passivation film, recess

Description

Semiconductor device

1 is a cross-sectional view showing a semiconductor device according to the first embodiment.

2 is a plan view of a semiconductor device according to the first embodiment.

3A to 3E show a method of manufacturing a semiconductor device according to the first embodiment.

4 is a diagram showing a semiconductor device according to a second embodiment.

FIG. 5 is a diagram showing a semiconductor device according to the third embodiment. FIG.

FIG. 6 is a diagram showing a semiconductor device according to a fourth embodiment. FIG.

7A to 7D are views for explaining a method for manufacturing a semiconductor device according to the fourth embodiment.

8A to 8C are diagrams for describing the method for manufacturing a semiconductor device according to the fourth embodiment.

9A to 9C show a method of manufacturing a semiconductor device according to the fifth embodiment.

10A to 10C show a method of manufacturing a semiconductor device according to the sixth embodiment.

11A and 11B show a semiconductor device according to the seventh embodiment.

12 is a diagram showing a semiconductor device according to the eighth embodiment.

13A to 13D show a method for manufacturing a semiconductor device according to the ninth embodiment.

14A and 14B show a method of manufacturing a semiconductor device according to the ninth embodiment.

15 is a diagram illustrating a modification of the ninth embodiment.

Fig. 16 shows a circuit board on which the semiconductor device according to the present embodiment is mounted.

Fig. 17 is a diagram showing an electronic device including a circuit board on which the semiconductor device according to the present embodiment is mounted.

The present invention relates to a semiconductor device, a manufacturing method thereof, a circuit board and an electronic device.

In pursuit of high-density mounting of semiconductor devices, bare chip mounting is ideal. However, bare chips are difficult to guarantee and handle in quality. Thus, a semiconductor device to which a Chip Scale / Size Package (CSP) is applied has been developed. Although there is no formal definition of CSP, it is generally known as an IC package whose package size is the same as or slightly larger than the IC chip. In order to promote high-density packaging, the development of CSP technology is important. As a publication which discloses a conventional example of a CSP, there is an international publication WO95 / 08856.

According to this, a gap is formed between the substrate having an external electrode and the semiconductor chip, and resin is injected into the gap. This resin has elasticity when cured. By this resin having elasticity, the stress (heat stress) applied to the external electrode is absorbed. This stress is caused by the difference in thermal expansion coefficient between the semiconductor device and the circuit board on which the semiconductor device is mounted.

However, since resin injected into the board | substrate of a semiconductor chip is extremely thin, sufficient heat stress was not absorbed.

SUMMARY OF THE INVENTION The present invention solves this problem, and an object thereof is to provide a semiconductor device, a manufacturing method thereof, a circuit board, and an electronic device capable of effectively absorbing thermal stress.

Disclosure of the Invention

(1) The semiconductor device according to the present invention includes a semiconductor element having an electrode,

A passivation film formed on the surface of said semiconductor element avoiding at least a part of each electrode,

A conductive foil formed at a predetermined interval in the thickness direction above the surface on which the passivation film is formed;

An external electrode formed on the conductive foil;

An intermediate layer formed between the passivation film and the conductive foil and supporting the conductive foil;

A wiring for electrically connecting the electrode and the conductive foil,

The said intermediate | middle layer is provided with the recessed part which consists of an opening area | region between the said passivation film and the said conductive foil below the area | region containing the junction part with the said external electrode in the said conductive foil.

The "semiconductor element" concerning this invention may refer not only to a semiconductor chip but also to a wafer type which is not divided into pieces. In other words, the semiconductor element referred to herein needs to be provided with a predetermined circuit which can be used even if it is separated into, for example, a base substrate made of silicon, and is not particularly limited as to whether it is separated into pieces or otherwise integrated. none.

According to the present invention, an external electrode is formed on the conductive foil, and the conductive foil is supported as the intermediate layer. A recess is formed in the intermediate layer, and an external electrode is located above the recess. In other words, the external electrode is not held directly by the intermediate layer, and is excited from the intermediate layer. By this fact, since the external electrode can move relatively freely, it is possible to absorb stress (thermal stress) caused by the difference in thermal expansion rate with the circuit board.

(2) In the recess, a resin having a Young's modulus lower than that of the intermediate layer may be filled.

By doing in this way, since the space of a recessed part can be filled, the crack by expansion of water vapor can be prevented at the time of heating, such as a reflow process.

(3) The said wiring is formed on the surface in which the said passivation film was formed, and is located in the bottom surface of the recessed part of the said intermediate | middle layer,

The said resin is an electrically conductive filler added, and may electrically connect the said wiring and the said conductive foil.

(4) The intermediate layer has an inclined surface between the electrode and the conductive foil,

The wiring may pass through the inclined surface and electrically connect the electrode and the conductive foil.

(5) The intermediate layer may be formed of a material having flexibility.

In this way, the stress can be alleviated also by the intermediate layer itself.

(6) The said conductive foil may have a hole in the position which avoids the connection part with the said external electrode as a position inside the opening area of the said recessed part.

By doing so, the conductive foil is easily deformed and the stress can be absorbed by the conductive foil.

(7) In this invention, the board | substrate with which the said conductive foil was formed is provided in the surface in which the said conductive foil was formed toward the said intermediate | middle layer,

The substrate has a through hole above the concave portion,

The external electrode may be formed in the conductive foil via the through hole.

According to this, the conductive foil phase is covered with a substrate and protected.

(8) In the present invention, a substrate formed of a flexible material is provided between the intermediate layer and the conductive foil,

The substrate has a through hole in a region excluding an upper portion of the concave portion,

The wiring and the conductive foil may be electrically connected through the through hole.

(9) The conductive foil and the wiring may be integrally formed.

(10) The conductive foil and the wiring may be separate bodies.

(11) The manufacturing method of the semiconductor device which concerns on this invention is a process of preparing the semiconductor element which has an electrode and formed the passivation film on the surface avoiding at least one part of each electrode,

A conductive foil is provided at a predetermined interval in the thickness direction above the surface on which the passivation film is formed, and an intermediate layer for supporting the conductive foil is formed between the passivation film and the conductive foil, and in the intermediate layer, Forming a recessed portion at the position avoiding the electrode;

Forming a wiring for electrically connecting the electrode and the conductive foil;

And forming an external electrode at an upper position of the concave portion in the conductive foil.

According to the semiconductor device manufactured by the present invention, an external electrode is formed on the conductive foil, and the conductive foil is supported as the intermediate layer. A recess is formed in the intermediate layer, and an external electrode is located above the recess. In other words, the external electrode is not held directly by the intermediate layer, and is excited from the intermediate layer. As a result, since the external electrode can move relatively freely, it is possible to absorb stress (heat stress) caused by the difference in thermal expansion rate with the circuit board.

(12) In this invention, the board | substrate which has a through-hole, and including the said through-hole is bonded to the said conductive foil was prepared,

Forming the intermediate layer on a surface on which the passivation film is formed, and forming the recess in the intermediate layer,

Thereafter, the through hole is positioned above the recess, the conductive foil is opposed to the recess, and the substrate is placed on the intermediate layer.

The external electrode may be formed in the conductive foil through the through hole.

According to this, since a conductive foil is adhere | attached on a board | substrate, the process of forming a conductive foil can be performed simply.

(13) In the present invention, a group formed of a flexible material having a through hole

Prepare the plate,

Forming the intermediate layer on a surface on which the passivation film is formed, forming the recess in the intermediate layer, and forming the wiring in the intermediate layer,

The substrate may be placed on the intermediate layer by placing the through hole on the wiring, the conductive foil may be formed on the substrate, and the wiring and the conductive foil may be electrically connected through the through hole.

According to this, since a conductive foil is adhere | attached on a board | substrate, the process of forming a conductive foil can be performed simply.

(14) The intermediate layer may be formed on the surface on which the passivation film is formed, the conductive foil may be formed in the intermediate layer, holes may be formed in the conductive foil, and the recess may be formed by etching the intermediate layer through the holes.

(15) The intermediate layer may be formed of a material which can be etched under conditions in which the semiconductor element cannot be etched.

By doing this, when etching the intermediate layer, it is possible to prevent the surface of the semiconductor element from being etched.

(16) The passivation film is etched under the etching conditions of the intermediate layer,

On the passivation film, a coating layer made of a material hardly etched under the etching conditions of the intermediate layer is formed, the intermediate layer is formed on the coating layer, the conductive foil is formed on the intermediate layer, and holes are formed in the conductive foil, You may form the said recessed part by etching the said intermediate | middle layer through the said hole.

Thus, by forming a coating layer in the passivation film, the etching of the passivation film can be prevented.

(17) The passivation film is etched under the etching conditions of the intermediate layer,

On the passivation film, a first coating layer made of a material hardly etched under the etching conditions of the intermediate layer is formed,

Forming the intermediate layer on the first coating layer,

While forming the conductive foil and the wiring on the intermediate layer, a hole is formed in the conductive foil,

Forming a solder resist layer on the wiring,

On the soldering resist layer, a second coating layer made of a material hardly etched under the etching conditions of the intermediate layer is formed,

You may etch the said intermediate | middle layer until it reaches under the said conductive foil through the hole of the said conductive foil.

(18) A step of forming the external electrode on the conductive foil before the step of etching the intermediate layer and forming an electrode coating layer made of a material that is difficult to be etched under the etching conditions of the intermediate layer on the external electrode. .

According to this, after forming an external electrode, an intermediate | middle layer is etched and a recess is formed. Therefore, since the etching can be performed after removing the residue caused by the formation of the external electrode, the residue does not remain in the recess.

(19) In the present invention, the recess may include a step of filling a resin having a Young's modulus lower than that of the intermediate layer.

(20) The semiconductor device is mounted on a circuit board according to the present invention.

(21) An electronic device according to the present invention includes the circuit board.

Example

EMBODIMENT OF THE INVENTION Hereinafter, preferred embodiment of this invention is described with reference to drawings.

In addition, each figure is enlarged in part in order to make description easy to understand. In the following description, since one semiconductor device at the time of finally reorganizing is assumed and described, there exists a slightly different place in terms, shapes, etc. which are used. In the following description, it is described as a semiconductor chip, and the meaning is that it is a separate piece (that is, a chip shape). However, the "semiconductor element" according to the present invention is not only a semiconductor chip but also a wafer type that is not to be separated In some cases, In other words, the semiconductor element referred to herein needs to be provided with a predetermined circuit which can be used even if it is separated into, for example, a base substrate type made of silicon, and it is necessary to specifically limit whether it is separated into pieces or otherwise integrated. none. In addition, since only the typical place of the location required for description of wiring etc. is a problem, the same thing and the other structure are abbreviate | omitted in other drawing in each drawing.

(First embodiment)

1 is a cross-sectional view showing a semiconductor device according to the first embodiment. The semiconductor device 10 shown in the drawing has a CSP type having a package size substantially the same as that of the semiconductor chip 12.

On the active surface 12a of the semiconductor chip 12, for example, an electrode 14 is formed of aluminum (A1). In addition, the passivation film 11 is formed in the semiconductor chip 12 to avoid at least a part of each electrode 14. Here, avoiding at least part of the reason is that it is necessary to derive an electrical signal or the like from the electrode 14. Therefore, the passivation film 11 needs to avoid the electrode 14 to such an extent that an electrical signal or the like can be derived from the electrode 14. The passivation film 11 can be formed with SiO ₂ , SiN, polyimide resin, or the like, for example. The intermediate layer 16 is formed on the active surface 12a to avoid the electrode 14. In detail, the intermediate layer 16 is formed on the passivation film 11. Moreover, the recessed part 16a is formed in the intermediate | middle layer 16, and the active surface 12a is exposed in the recessed part 16a. However, the recessed part 16a should just be a recessed shape, and the active surface 12a does not need to be exposed. In addition, the inclined surface 16b inclined from the electrode 14 is formed in the intermediate layer 16, and the wiring 18 is formed over the intermediate layer 16 from the electrode 14 via the inclined surface 16b. have. The opening end of the concave portion 16a shown in FIG. 1 is considerably larger than the size of the root portion of the external electrode 26, but is not limited to this, and is substantially equal to the size of the root portion of the external electrode 26. As shown in FIG. It may be the same or more. In addition, the opening of the recessed part 16a may be located in a part of the root of the external electrode 26, and in this case, this opening allows deformation | transformation of an intermediate | middle layer, and can exhibit a stress relaxation effect. In addition, although the recessed part 16a may penetrate the intermediate | middle layer 16, and may expose the passivation film 11 below, the intermediate | middle layer 16 may be in the bottom part of the recessed part 16a so that it may not penetrate the intermediate | middle layer 16. FIG. You can leave part of

Here, the intermediate layer 16 is made of an insulating resin, for example, a polyimide resin, and the circuit board mounted with the semiconductor chip 12 when the semiconductor device 10 is mounted on a circuit board (not shown); The stress caused by the difference in thermal expansion coefficients can be alleviated. In addition, it is not an essential requirement of the present invention that the intermediate layer 16 has a stress relaxation function. The stress relaxation function is achieved by forming the concave portion 16a (details will be described later).

The insulating resin also has insulation property against the wiring 18, can protect the active surface 12a of the semiconductor chip 12, and also has heat resistance when melting solder during mounting. In consideration of adding a stress relaxation function to be described later, polyimide resins and the like are generally used, and among them, the Young's modulus is low (for example, BCB manufactured by Dow Chemical Co., Ltd. except for olefin-based polyimide resin and polyimide resin). Etc.), and a Young's modulus is particularly preferably about 300 kg / mm ² or less. The thicker the intermediate layer 16 is, the larger the stress relaxation force becomes. However, in consideration of the size of the semiconductor device, manufacturing cost, and the like, it is preferable that the intermediate layer 16 has a thickness of about 1 to 100 µm. However, when the Young's modulus uses a polyimide resin of about 300 kg / mm ² , a thickness of about 10 μm is sufficient.

Alternatively, for example, a silicone-modified polyimide resin, an epoxy resin, a silicone-modified epoxy resin, or the like may be used as the intermediate layer 16, and a material having a low Young's modulus and capable of performing stress relaxation may be used. The passivation layer (SiN, SiO ₂ , MgO, etc.) may be formed as the intermediate layer 16, and the stress relaxation itself may be performed by forming the concave portion 16a as described later.

The wiring 18 is formed from, for example, copper (Cu), chromium (Cr), titanium (Ti), nickel (Ni), titanium tungsten (Ti-W), or a plurality of them laminated thereon, and conductive thereon. The foil 22 is formed. The electrically conductive foil 22 is formed in the board | substrate 20 previously, and is adhere | attached on the wiring 18 with the board | substrate 20 through the adhesive agent 24. In addition, the conductive foil 22 is also made of copper (Cu), for example.

The electrically conductive foil 22 is formed larger than the open end of the recessed part 16a formed in the intermediate | middle layer 16, and is arrange | positioned so that the upper part of this recessed part 16a may be covered. A portion of the conductive foil 22 is in contact with and electrically connected to the wiring 18. In addition, the conductive foil 22 and the wiring 18 are preferably welded by applying heat and pressure. Electrical connection between the conductive foil 22 and the wiring 18 can also be performed by mechanical pressure welding with the adhesive agent 24 as described above, and Au, Sn on the wiring 18 and the conductive foil 22 can be obtained. , Solder and the like may be plated to solder both, or may be connected by diffusion bonding by ultrasonic heat or the like. Therefore, it is preferable that low-temperature lead is formed in at least one of the joining surfaces of both the conductive foil 22 and the wiring 18.

The board | substrate 20 is a film-form formed from flexible resin etc., and has the through-hole 20a in the position above the recessed part 16a. In addition, the conductive foil 22 is formed so as to cover the through hole 20a on the lower surface of the substrate 20. The external electrode 26 is formed in the conductive foil 22 through the through hole 20a. The external electrode 26 may be formed of, for example, solder only, or may be formed by soldering or gold plating the surface of copper (Cu) or nickel (Ni).

Moreover, as the board | substrate 20 with the conductive foil 22, the film carrier tape or FPC used by TAB technique of two layers (Cu foil + polyimide board | substrate or three layers (Cu foil + adhesive + polyimide board | substrate)) Flexible printed circuits) may be used.

This embodiment is comprised as mentioned above, and the effect | action is demonstrated below. In the semiconductor device 10, the conductive foil 22 in which the external electrode 26 was formed is supported by the intermediate | middle layer 16. As shown in FIG. have. However, the recessed part 16a is formed in the intermediate | middle layer 16 in the area | region just under the external electrode 26. As shown in FIG. By the recessed part 16a, the space is formed under the conductive foil 22. As shown in FIG. As a result, in the vicinity of the junction with the external electrode 26, the conductive foil 22 is excited and easily deformed. In this manner, when the stress is applied to the external electrode 26, the conductive foil 22 and the substrate 20 deform, whereby the stress can be absorbed. In this way, when the semiconductor device is mounted on a circuit board or when the mounted circuit board or electronic device is stressed due to a thermal expansion coefficient difference between the semiconductor device (or a semiconductor chip formed from silicon) and the circuit board due to temperature change, The mechanical stress generated when bent by the stress can be absorbed. Hereinafter, stress means this.

Next, in FIG. 2, the top view of the semiconductor device which concerns on this embodiment is shown. In the figure, the wiring 18 is formed in the center direction of the active surface 12a from the electrode 14 of the semiconductor chip 12, and each wiring 18 is connected to the conductive foil 22, and electrically conductive. The foil 22 is provided with an external electrode 26. The region excluding the external electrode 26 is covered and protected by the substrate 20.

Although the electrode 14 is an example of what is called a peripheral electrode type located in the peripheral part of the semiconductor chip 12, you may use the area array arrangement type semiconductor chip in which an electrode was formed in the inner area rather than the peripheral area of a semiconductor chip.

As shown in the drawing, the external electrode 26 is provided in the active region (region in which the active element is formed) of the semiconductor chip 12, not on the electrode 14 of the semiconductor chip 12. As shown in FIG. By forming the intermediate layer 16 in the active region and placing the wiring 18 in the active region, the external electrode 26 can be provided in the active region. That is, pitch conversion can be performed. Therefore, when the external electrode 26 is disposed, it is possible to provide an area within the active area, that is, a constant surface, and the degree of freedom of the setting position of the external electrode 26 is greatly increased.

The external electrodes 26 are arranged so as to be arranged side by side in a lattice form by bending the wiring 18 at a necessary position. In addition, since this is not an essential structure of the present invention, the external electrodes 26 do not necessarily have to be arranged so as to be arranged side by side in a lattice form.

2, at the junction of the electrode 14 and the wiring 18, the width of the electrode 14 and the width of the wiring 18,

Wiring 18 <electrode 14

In practice, the electrodes 14 and wiring 18

It is preferable to set it as. Especially,

Electrode 14 <wiring 18

In this case, not only the resistance value of the wiring 18 is reduced, but also the strength is increased so that disconnection is prevented.

In addition, in this embodiment, although the intermediate | middle layer 16 has a stress relaxation function, it is possible to absorb stress only by forming the recessed part 16a. Therefore, even if the intermediate layer 16 has a structure in which a layer (for example, a simple insulating layer or a protective layer) made of a material having no stress relaxation function is formed, the stress can be absorbed.

Next, FIGS. 3A to 3E are views for explaining a method for manufacturing a semiconductor device according to the present embodiment. First, as shown in FIG. 3A, the semiconductor chip 12 which has the electrode 14 which consists of aluminum (Al), for example is prepared. In addition, a passivation film (not shown) is formed on the semiconductor chip 12 to avoid the electrode 14. What is necessary is just to prepare a commercially available wafer, even when performing the process which concerns on this invention with respect to a wafer type semiconductor element. Then, a polyimide resin (not shown) is provided on the active surface 12a of the semiconductor chip 12 by a method such as spin coating. Or you may adhere | attach the polyimide resin etc. which became film form previously to the active surface 12a.

Then, through the photolithography process, as shown in FIG. 3B, the intermediate layer 16 having the concave portion 16a is formed. In addition, when forming the recessed part 16a by photolithography, it is preferable to select the material suitable for it as a material of the intermediate | middle layer 16. FIG.

Subsequently, as shown in FIG. 3C, the wiring 18 reaching the intermediate layer 16 from the electrode 14 is formed. For example, a 100 angstrom ( ^10-10 m) titanium tungsten (Ti-W) layer is formed by sputtering, and a 1 μm copper (Cu) layer is formed on the same by sputtering to form a metal film thus obtained. The wiring 18 is formed by etching in a predetermined pattern.

And as shown in FIG. 3D, the board | substrate 20 is adhere | attached through the adhesive agent 24. As shown in FIG. The through-hole 20a is previously formed in the board | substrate 20, and the conductive foil 22 is provided in the position which covers the through-hole 20a.

In addition, it is preferable to form, for example, tin (Sn), gold (Au), solder, or the like on at least one of the joint surfaces of both the conductive foil 22 and the wiring 18 to form low-temperature lead. .

The substrate 20 is placed so that the conductive foil 22 contacts the wiring 18, and heat and pressure are applied from above the substrate 20. In this way, low-temperature lead melts, and the electrically conductive foil 22 and the wiring 18 are electrically connected. This connection may be performed by applying an ultrasonic wave or the like.

Next, as shown in FIG. 3E, the external electrode 26 is formed in the conductive foil 22 through the through hole 20a of the substrate 20. For example, on the conductive foil 22, a solder ball is placed, a solder plating is laminated, a solder paste is printed, copper (Cu) or nickel (Ni) or both plating is performed and solder or The external electrode 26 is formed by plating gold (Au).

Through the above steps, the semiconductor device 10 can be obtained. Moreover, when the semiconductor chip 12 is a wafer type, the semiconductor device 10 is obtained by dicing and cutting | disconnecting into pieces. After that, the semiconductor device 10 is subjected to quality inspection and filled in the tray.

In addition, although the wiring 18 is formed in the inclined surface 16b in this embodiment, you may be formed in the inclined surface by the side of the recessed part 16a. This also applies to the following embodiments. In this way, since most of the wiring 18 passes through the intermediate layer 16 and is protected, device reliability is improved.

(2nd embodiment)

4 is a diagram illustrating a semiconductor device according to the second embodiment. The semiconductor device 30 shown in the drawing is characterized in that the resin 32 is filled in the concave portion 16a of the semiconductor device 10 shown in FIG. 1, and the other configuration is a semiconductor device ( Same as 10). Although the opening end of the recessed part 16a shown in FIG. 4 is considerably larger than the magnitude | size of the root part of the external electrode 26, it is not limited to this, and the magnitude | size of the root part of the external electrode 26 is not limited to this. It may be about the same or more. In addition, the opening of the recessed part 16a may be located in a part of the root of the external electrode 26, and in this case, this opening allows deformation | transformation of an intermediate | middle layer, and can exhibit a stress relaxation effect. In addition, although the recessed part 16a may penetrate the intermediate | middle layer 16, and may expose the passivation film (not shown) below, the intermediate | middle layer (at the bottom of the recessed part 16a) may not be penetrated. You may leave a part of 16).

As the resin 32, for example, a polyimide resin, a silicone gel, or a rubber used as a photosensitive resistor is preferably one having a lower Young's modulus and being softer than the intermediate layer 16. By doing in this way, the space formed by the recessed part 16a can be filled, and the crack by expansion of air or water vapor at the time of heating, such as a reflow process, can be prevented.

The resin 32 may be filled before the substrate 20 is bonded, or may be filled through the hole after the hole is formed in the substrate 20 and the substrate 20 is bonded.

In addition, filling resin in a recessed part like this embodiment is applicable also in all following embodiments.

(Third embodiment)

FIG. 5 is a diagram showing a semiconductor device according to the third embodiment. FIG. The semiconductor device 40 shown in the drawing has a semiconductor chip 12, an electrode 14, an intermediate layer 16, and a wiring 18, similarly to the semiconductor device 10 shown in FIG. 1. 16, the recessed part 16a is formed.

The board | substrate 42 is adhere | attached on the intermediate | middle layer 16 through the adhesive agent 24. The board | substrate 42 is a film | membrane formed from material with low Young's modulus, such as the polyimide resin mentioned as the material of the intermediate | middle layer 16, for example in 1st Embodiment. On the substrate 42, a patterned conductive foil 44 is formed on the wiring, and an external electrode 46 is formed on the conductive foil 44. In the board | substrate 42, the through-hole 42a is formed in the part located on the intermediate | middle layer 16 of the wiring 18. As shown in FIG. An electrical junction portion 48 is formed in the through hole 42a, and the conductive foil 44 and the wiring 18 are electrically connected to each other. In addition, a soldering resist layer 49 is provided on the conductive foil 44 to avoid the external electrode 46 to protect the conductive foil 44.

Next, the manufacturing method of the semiconductor device 40 is demonstrated. First, the intermediate | middle layer 16 and the wiring 18 are formed in the semiconductor chip 12 through the process shown to FIG. 3A-FIG. 3C, and the recessed part 16a is formed in the intermediate | middle layer 16. FIG.

Then, the substrate 42 is bonded to the intermediate layer 16 with the adhesive 24 interposed therebetween, so that the through hole 42a is formed in the substrate 42. Moreover, after forming the through-hole 42a in the board | substrate 42 previously, you may adhere | attach this.

Next, the conductive foil 44 is formed on the substrate 42. The conductive foil 44 can be formed by, for example, sputtering, electroplating, electroless plating, or the like. For the patterning of the conductive foil 44, a technique of photolithography may be used. Alternatively, the conductive foil 44 patterned in advance in the substrate 42 may be provided, and then the adhesive foil 44 may be bonded onto the intermediate layer 16.

For example, the electrical bonding portion 48 is provided in the region including the through-hole 42a of the substrate 42 by electroless plating or by applying electroplating thereto.

Next, the solder resist layer 49 is provided on the conductive foil 44 to avoid the region where the external electrode 46 is formed, and then the external electrode 46 is formed. The formation method of the external electrode 46 is the same as the formation method of the external electrode 26 of 1st Embodiment.

Since the recessed part 16a is formed in the intermediate | middle layer 16 also by the semiconductor device 40 manufactured as mentioned above, the stress applied to the external electrode 26 can be absorbed.

(4th Embodiment)

6 is a diagram illustrating a semiconductor device according to the fourth embodiment. In the semiconductor device 50 shown in the drawing, like the semiconductor device 10 shown in FIG. 1, an intermediate layer 56 is formed on a semiconductor chip 52 having an electrode 54, and an intermediate layer 56 is formed on the intermediate layer 56. The recessed part 56a is formed. In addition, the wiring 58 is formed from the electrode 54 on the intermediate layer 56, and the conductive foil 60 is formed on the intermediate layer 56 integrally with the wiring 58. At least one hole 60a is formed in the conductive foil 60. The external electrode 62 is formed in the region on the recess 56a in the conductive foil 60. In addition, the solder resist layer 64 is formed on the wiring 58 and the conductive foil 60 to avoid the external electrode 62, and these are protected.

This embodiment has the characteristics in the manufacturing method. 7A to 8C are diagrams for describing the method for manufacturing a semiconductor device according to the present embodiment.

In this embodiment, since the substrate is not used, it is preferable to form the intermediate layer 56, the external electrode 62, or the like on the wafer, and then cut it. On the other hand, in the form using a board | substrate (1st thru | or 3rd embodiment), a tape-shaped board | substrate can be adhere | attached on a separate semiconductor chip.

First, as shown in FIG. 7A, the intermediate layer 56 is formed on the active surface 52a of the semiconductor chip 52, avoiding the electrode 54. The intermediate layer 56 is formed of the same material as the intermediate layer 16 shown in FIG. 1. When the intermediate layer 56 is formed of a material having a low Young's modulus, the intermediate layer 56 also serves as a stress relaxation function. Alternatively, the intermediate layer 56 may be formed of a hard material (for example, an inorganic material such as magnesium oxide (MgO)) that does not perform a stress relaxation function.

Moreover, when the intermediate | middle layer 56 is etched at a later process, it is preferable that the intermediate | middle layer 56 differs from a semiconductor passivation film and a material so that the active surface 52a of the semiconductor chip 52 may not be etched. For that purpose, it is preferable that the intermediate | middle layer 56 is formed from the material which can be etched on condition that the substance exposed to the surface of the semiconductor chip 52 is not etched.

Next, as shown in FIG. 7B, a metal film 66 is formed over the intermediate layer 56 from the electrode 54. The manufacturing method is the same as the forming method of the metal film for forming the wiring 18 of 1st Embodiment. In this case, since the stress of the external terminal 62, which will be described later, is directly applied to the wiring 58, the thickness of the wiring 58 is preferably about 5 to 20 m. The metal film 66 is etched in the process described later to form the wiring 58 and the conductive foil 60.

Next, as shown in FIG. 7C, a hole 60a is formed in a portion of the metal film 66 that becomes the conductive foil 60, and the intermediate layer 56 is formed through the hole 60a. It is exposed to etching liquid or etching gas (corrosion agent). For example, when forming the intermediate layer 56 of a resin such as polyimide, as the etchant, a dry etching gas such as steel alkaline aqueous solution such as KOH or, 0 ₂ or CF ₄ preferred, and the oxidation of the intermediate layer 56 In the case of forming with magnesium (MgO) or the like, a hot phosphoric acid aqueous solution or the like is preferable. After that, the caustic agent is removed as necessary. In particular, in the case of a wet process, it is preferable to add a washing and a rinsing process. In this way, as shown in FIG. 7D, the intermediate layer 56 is etched to form the recess 56a.

Subsequently, as shown in FIG. 8A, the metal film 66 is patterned to form the wiring 58 and the conductive foil 60. Then, the solder resist layer 64 is formed as shown in Fig. 8B, and the external electrode 62 is formed as shown in Fig. 8C. As a soldering resist, the photosensitive polyimide resin, an epoxy resin dry film, etc. are used in many cases. The formation method of the external electrode 62 is the same as that of the first embodiment. In this way, the semiconductor device 50 is obtained. Also in this embodiment, the effect similar to 1st Embodiment can be achieved.

In the semiconductor device 50 manufactured by the present embodiment, since the holes 60a are formed in the conductive foil 60, the conductive foil 60 is easily deformed. Therefore, the absorption effect of the stress by the conductive foil 60 which became excited on the recessed part 56a is heightened further.

(5th Embodiment)

9A to 9C are diagrams showing a method for manufacturing a semiconductor device according to the fifth embodiment. In this embodiment, as shown in FIG. 9A, the intermediate layer 76 is formed on the semiconductor chip 72 having the electrode 74. The conductive foil 80 is formed on the intermediate layer 76, and the wiring 78 is formed to reach the electrode 74 from the conductive foil 80. The solder resist layer 84 is formed on the wiring 78 and the conductive foil 80. Further, holes 80a are formed in the conductive foil 80.

In addition, the formation method of the intermediate | middle layer 76 is the same as the method shown in FIG. 7A, and the formation method of the wiring 78, the hole 80a, and the conductive foil 80 is the same as the method shown in FIGS. 7B-8A. In addition, the soldering resist layer 84 is formed in the area | region which avoids the external electrode 82 (refer FIG. 9B).

Then, after forming the external electrode 82 on the conductive foil 80 and removing the residues accompanying it, the coating layer 86 is formed on the external electrode 82 and the solder resist layer 84. (See FIG. 9B). The coating layer 86 is formed of a material hard to be etched under the etching conditions of the intermediate layer 76.

Subsequently, through the hole 80a of the conductive foil 80, the recessed portion 76a is formed in the intermediate layer 76 in the same manner as in the process of FIG. 7D, and the coating layer 86 is removed, as shown in FIG. 9C. The semiconductor device 70 is obtained.

According to this embodiment, since the recessed part 76a is formed in the intermediate | middle layer 76 after removing the residue which arises at the time of forming the external electrode 82, no residue remains in the recessed part 76a. In addition, the characteristic of the semiconductor device 70 manufactured by this embodiment is the same as that of 4th embodiment.

(6th Embodiment)

10A to 10C are diagrams showing a method for manufacturing a semiconductor device according to the sixth embodiment.

In the present embodiment, as shown in FIG. 10A, the semiconductor chip 102 in which the passivation film 106 is formed on the active surface 102a, avoiding the electrode 104 is used. The passivation film 106 is formed of a material having a property in common with the intermediate layer 108 shown in FIG. 10C. That is, the passivation film 106 is formed of the material which is etched under the etching conditions of the intermediate layer 108. For example, the case where both the intermediate | middle layer 108 and the passivation film 106 are formed with polyimide resin is applicable.

In this case, as shown in FIG. 10B, the coating layer 118 is formed on the passivation film 106 at least below the recess 108a (see FIG. 10C). The coating layer 118 is formed of a material which is not etched under the etching conditions of the intermediate layer 108 and the passivation film 106. For example, when the intermediate layer 108 and the passivation film 106 are formed of polyimide resin, the coating layer 118 may be made of metal thin films such as Cr, Ti-W, and Ti.

Thereafter, as shown in FIG. 10C, the conductive foil having the intermediate layer 108 having the recess 108a, the wiring 110, and the holes 112a is formed by the steps shown in FIGS. 7A to 8C. 112, an external electrode 114, and a solder resist layer 116 are formed.

According to this embodiment, since the passivation film 106 is covered by the coating layer 118, even when the intermediate layer 108 is etched to form the recessed portion 108a, the passivation film 106 is prevented from being etched. can do. In this way, the active element can be prevented from being exposed in the recess 108a. The characteristic concerning the stress relaxation function is the same as that of embodiment mentioned above.

(7th Embodiment)

11A and 11B are diagrams showing a part of the semiconductor device according to the seventh embodiment. 11B is a cross-sectional view taken along the line B-B in FIG. 11A. In the semiconductor device 120 according to the present embodiment, holes 122 and 124 are formed in the substrate 20 and the conductive foil 22 in the semiconductor device 10 shown in FIG. 1.

According to this embodiment, by forming the holes 122 and 124, the board | substrate 20 and the conductive foil 22 are easy to deform | transform, and the stress relaxation function is improved.

(8th Embodiment)

12 is a diagram illustrating a semiconductor device according to the eighth embodiment. In the semiconductor device 130 shown in the figure, a wiring 136 is formed from an electrode 134 on the active surface 132a of the semiconductor chip 132. The intermediate layer 138 is formed on the wiring 136. And the recessed part 138a is formed in the intermediate | middle layer 138 so that the wiring 136 may be exposed in the position on the wiring 136. As shown in FIG. The substrate 146 is provided on the intermediate layer 138 with the adhesive 142 interposed therebetween. In this board | substrate 146, the conductive foil 144 is formed in the position above the recessed part 138a, and in the surface which opposes this recessed part 138a. In addition, the through hole 146a is formed in the substrate 146 above the recess 138a, and the conductive foil 144 is exposed from the surface on the opposite side. The external electrode 148 is formed through the through hole 146a.

In addition, the conductive paste 140 is filled in the recess 138a. The conductive paste 140 is made of soft resin, similar to the resin 32 filled in the recessed portion 16a shown in FIG. 4, such as silver (Ag), copper (Cu), silver-plated copper, or gold (Au). A conductive filler is added. The wiring paste 136 and the conductive foil 144 are electrically connected by the conductive paste 140.

Also in this embodiment, since the recessed part 138a is formed in the intermediate | middle layer 138, a stress relaxation function can be fulfilled.

(Ninth embodiment)

13A to 14B are diagrams showing a method for manufacturing a semiconductor device according to the ninth embodiment. In this embodiment, like the semiconductor chip 102 shown in FIG. 10A, a semiconductor chip 152 in which a passivation film (not shown) is formed on the active surface 152a is used. This passivation film is formed of a material which is etched under the etching conditions of the intermediate layer 158.

As shown in FIG. 13A, the coating layer 156 is formed on the passivation film in the active surface 152a. The coating layer 156 is formed of a material that is not etched under the etching conditions of the intermediate layer 158 (for example, chromium (Cr), titanium (Ti), titanium tungsten (Ti-W), copper (Cu), etc.). . The coating layer 156 is formed by sputtering, for example.

Next, as shown in FIG. 13B, the intermediate layer 158 is formed by avoiding the electrode 154 including the coating layer 156. The material of the intermediate | middle layer 158 is the same as that of 1st Embodiment.

As shown in FIG. 13C, the wiring 160 is formed from the electrode 154 to the intermediate layer 158, and the conductive foil 162 is formed so as to be electrically connected to the wiring 160. Specifically, by sputtering, a metal film in which chromium (CF), titanium (Ti), titanium tungsten (Ti-W) or copper (Cu) or a plurality of them are laminated is formed, and patterned by etching, The wiring 160 and the conductive foil 162 are integrally formed. In addition, holes 162a are formed in the conductive foil 162.

Subsequently, as illustrated in FIG. 13D, an external electrode 164 is formed on the conductive foil 162. Specifically, on the conductive foil 162, bumps in which copper (Cu), nickel (Ni) or gold (Au), or a plurality of them are stacked, are formed by electroplating or electroless plating. 164 is formed.

14A, the solder resist layer 166 is formed on the wiring 160, and the coating layer 168 is formed on the solder resist layer 166. The coating layer 168 also

It is formed of a material that is not etched under the etching conditions of the intermediate layer 158 (for example, chromium (Cr), titanium (Ti), titanium tungsten (Ti-W), copper (Cu, etc.)).

And as shown in FIG. 14B, the recessed part 158a is formed in the intermediate | middle layer 158. FIG. The process is the same as the process shown to FIG. 7D. In addition, the coating layer 168 is removed by etching. In this example, although the opening is in the center portion of the external electrode 164, the opening design may be the same as in the seventh embodiment.

Through the above steps, the semiconductor device 150 can be obtained. Also in this semiconductor device 150, the recessed part 158a is formed in the intermediate | middle layer 158, and fulfills a stress relaxation function.

In addition, instead of the bump type external electrode 164 of the semiconductor device 150 shown in FIG. 14B, as shown in FIG. 15, an end portion for forming the hole 162a in the conductive foil 162 is formed. You may form the external electrode 170 which consists of solder balls in it.

In addition, this invention is not limited to a CSP type semiconductor device. For example, when a strain part is directly laminated on the electrode of a semiconductor chip, the semiconductor device which is the size equivalent to a flip chip, but also has a stress relaxation function is obtained.

FIG. 16 shows a circuit board 1000 on which a semiconductor device 1100 manufactured by the method according to the above embodiment is mounted. As the circuit board 1000, for example, an organic substrate such as a glass epoxy substrate is generally used. The circuit board 1000 is formed so that a wiring pattern made of copper, for example, becomes a desired circuit, and solder balls are provided on the circuit board 1000. The electrical conduction is achieved by mechanically connecting the solder balls of the wiring pattern and the external electrodes of the semiconductor device 1100.

In this case, since the semiconductor device 1100 is formed with a structure that absorbs deformation caused by the difference in thermal expansion with the outside, even when the semiconductor device 1100 is mounted on the circuit board 1000, Reliability can be improved.

Moreover, the mounting area can also be reduced to the area mounted by bare chips. Therefore, when the circuit board 1000 is used for an electronic device, the electronic device itself can be miniaturized. In addition, the mounting space can be more secured within the same area, and high functionality can be achieved.

In addition, a notebook type personal computer 1200 is shown in FIG. 17 as an electronic device including the circuit board 1000.

In addition, the present invention can be applied to various surface mounting electronic components, whether active or passive components. Examples of the electronic components include resistors, capacitors, coils, oscillators, filters, temperature sensors, thermistors, varistors, volumes, or fuses.

Claims (10)

A semiconductor element having an electrode, A passivation film provided on the surface of said semiconductor element avoiding at least a part of each electrode, A conductive foil provided at a predetermined interval in the thickness direction above the surface on which the passivation film is formed; An external electrode formed on the conductive foil; An intermediate layer formed between the passivation film and the conductive foil and supporting the conductive foil; A wiring for electrically connecting the electrode and the conductive foil, An inclined surface is formed in the intermediate layer, and a concave portion formed of an opening region between the passivation film and the conductive foil is formed below the region including the junction portion with the external electrode in the conductive foil. And the wiring electrically connects the electrode and the conductive foil through the inclined surface. The method according to claim 1, A semiconductor device in which the resin having a Young's modulus lower than that of the intermediate layer is filled in the recess. The method according to claim 2, The wiring is formed on the surface on which the passivation film is formed and is located on the bottom surface of the recess of the intermediate layer. The resin is a semiconductor device to which the conductive filler is added, and electrically connects the wiring and the conductive foil. The method according to claim 1, The inclined surface is formed between the electrode and the conductive foil. The method according to claim 1, And the intermediate layer is formed of a flexible material. The method according to claim 1, And the conductive foil has a hole at a position that avoids a connection with the external electrode at a position inside the opening region of the recess. The method according to any one of claims 1 to 6, The board | substrate with which the said conductive foil was formed is provided facing the surface where the said conductive foil was formed toward the said intermediate | middle layer, The substrate has a through hole above the concave portion, And the external electrode is formed on the conductive foil through the through hole. The method according to any one of claims 1 to 6, A substrate formed of a flexible material is provided between the intermediate layer and the conductive foil, The substrate has a through hole in an area except the upper portion of the concave portion, And the wiring and the conductive foil are electrically connected to each other through the through hole. The method according to any one of claims 1 to 6, And the conductive foil and the wiring are integrally formed. The method according to any one of claims 1 to 6, The conductive foil and the wiring are separate semiconductor devices.

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