JP3534214B2 - Semiconductor package and substrate for mounting semiconductor chip used therein - Google Patents
Semiconductor package and substrate for mounting semiconductor chip used thereinInfo
- Publication number
- JP3534214B2 JP3534214B2 JP30900195A JP30900195A JP3534214B2 JP 3534214 B2 JP3534214 B2 JP 3534214B2 JP 30900195 A JP30900195 A JP 30900195A JP 30900195 A JP30900195 A JP 30900195A JP 3534214 B2 JP3534214 B2 JP 3534214B2
- Authority
- JP
- Japan
- Prior art keywords
- semiconductor chip
- base substrate
- insulating base
- semiconductor
- adhesive
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73265—Layer and wire connectors
Description
【０００１】[0001]
【発明の属する技術分野】本発明は、半導体パッケ−ジ
及びそれに用いる半導体チップ搭載用基板に関する。TECHNICAL FIELD The present invention relates to a semiconductor package.
And a semiconductor chip mounting substrate used therein .
【０００２】[0002]
【従来の技術】半導体の集積度が向上するに従い、入出
力端子数が増加している。従って、多くの入出力端子数
を有する半導体パッケージが必要になった。一般に、入
出力端子はパッケージの周辺に一列配置するタイプと、
周辺だけでなく内部まで多列に配置するタイプがある。
前者は、ＱＦＰ（Ｑｕａｄ Ｆｌａｔ Ｐａｃｋａｇｅ）
が代表的である。これを多端子化する場合は、端子ピッ
チを縮小することが必要であるが、０．５ｍｍピッチ以
下の領域では、半導体パッケージを搭載する配線板との
接続に高度な技術が必要になる。2. Description of the Related Art The number of input / output terminals has increased as the degree of integration of semiconductors has improved. Therefore, a semiconductor package having a large number of input / output terminals has been required. Generally, I / O terminals are arranged in a row around the package,
There is a type that arranges not only the periphery but also the interior in multiple rows.
The former is QFP (Quad Flat Package)
Is typical. When the number of terminals is increased, it is necessary to reduce the terminal pitch, but in the area of 0.5 mm pitch or less, a high level technique is required for connection with a wiring board on which a semiconductor package is mounted.
【０００３】後者のアレイタイプは比較的大きなピッチ
で端子配列が可能なため、多ピン化に適している。従
来、アレイタイプは接続ピンを有するＰＧＡ（Ｐｉｎ
Ｇｒｉｄ Ａｒｒａｙ）が一般的であるが、半導体パッ
ケージを搭載する配線板との接続は挿入型となり、表面
実装には適していない。The latter array type is suitable for increasing the number of pins because terminals can be arranged at a relatively large pitch. Conventionally, the array type has a PGA (Pin
Grid Array) is common, connection between the wiring board you mounting semiconductor package becomes insertion type, not suitable for surface mounting.
【０００４】このため、表面実装可能なＢＧＡ（Ｂａｌ
ｌ Ｇｒｉｄ Ａｒｒａｙ）と称するパッケージが開発さ
れている。ＢＧＡの分類としては、（１）セラミックタ
イプ、（２）プリント配線板タイプ及び（３）ＴＡＢを
使ったテープタイプなどがある。このうち、セラミック
タイプについては、従来のＰＧＡに比べるとマザーボー
ドとパッケージ間の距離が短くなるために、マザーボー
ドとパッケージ間の熱応力差に起因するパッケージ反り
が深刻な問題である。また、プリント配線板タイプにつ
いても、基板の反り、耐湿性、信頼性などに加えて基板
厚さが厚いなどの問題があり、ＴＡＢ技術を適用したテ
ープＢＧＡが提案されている。For this reason, surface mountable BGA (Bal
A package called the l Grid Array) has been developed. The BGA classification includes (1) ceramic type, (2) printed wiring board type, and (3) TAB tape type. Among them, the ceramic type has a shorter distance between the mother board and the package than the conventional PGA, so that the package warpage due to the difference in thermal stress between the mother board and the package is a serious problem. Further, the printed wiring board type also has problems such as warpage of the substrate, moisture resistance, reliability, and the like, and a thick substrate thickness. Therefore, a tape BGA to which the TAB technique is applied has been proposed.
【０００５】一方、パッケージサイズの更なる小型化に
対応するものとして、半導体チップとほぼ同等サイズ
の、いわゆるチップサイズパッケージ（ＣＳＰ；Ｃｈｉ
ｐ Ｓｉｚｅ Ｐａｃｋａｇｅ）が提案されている。これ
は、半導体チップの周辺部でなく、実装領域内に外部配
線基板との接続部を有するパッケージである。具体例と
しては、バンプ付きポリイミドフィルムを半導体チップ
の表面に接着し、チップと金リード線により電気的接続
を図った後、エポキシ樹脂などをポッティングして封止
したもの（ＮＩＫＫＥＩ ＭＡＴＥＲＩＡＬＳ ＆ ＴＥ
ＣＨＮＯＬＯＧＹ ９４．４，Ｎｏ．１４０，ｐ１８−
１９）などがあった。On the other hand, in order to cope with further miniaturization of the package size, a so-called chip size package (CSP; Chi) which is almost the same size as a semiconductor chip.
p Size Package) has been proposed. This is a package having a connection portion with an external wiring board in the mounting area, not in the peripheral portion of the semiconductor chip. As a specific example, a polyimide film with bumps is adhered to the surface of a semiconductor chip, electrical connection is made with the chip and a gold lead wire, and then epoxy resin or the like is potted and sealed (NIKKEI MATERIALS & TE
CHNOLOGY 94.4, No. 140, p18-
19) and so on.
【０００６】[0006]
【発明が解決しようとする課題】前述のように、ＢＧＡ
やＣＳＰ分野で樹脂フィルムをベース基板として利用し
たパッケージが検討されているが、ポリイミドなどの樹
脂フィルムはセラミックスなどと比較して吸湿しやす
く、ベース基板側からの水の浸入を防止することは困難
である。従って、外部接続端子としてはんだボールをＩ
Ｒリフローさせる工程や半導体パッケージをプリント配
線基板にはんだ実装する際に、ベース基板やチップ接着
材界面付近にトラップされた水に起因されるふくれや剥
がれ、あるいは、封止樹脂のクラックなどが発生しやす
く、半導体チップと配線パターンとの接続部が剥離して
電気的接続不良を引き起こすという問題があった。ま
た、同様な接続不良現象は、半導体チップ接着工程で接
着材に含まれる溶剤分が除去されないことや、半導体チ
ップ面と接着材面との追従性が悪いことなどにより、予
め半導体チップ／接着材界面にボイドが形成されてしま
うことによっても引き起こされる。本発明は、はんだリ
フロー工程のふくれや剥がれなどに起因する電気的接続
不良を低減可能な半導体パッケージを提供するものであ
る。As described above, the BGA
A package that uses a resin film as a base substrate has been studied in the field of CSP and CSP, but resin films such as polyimide are more likely to absorb moisture than ceramics and it is difficult to prevent water from entering from the base substrate side. Is. Therefore, solder balls are used as external connection terminals.
During the R reflow process or when mounting the semiconductor package on a printed wiring board by soldering, swelling or peeling due to water trapped near the interface of the base substrate or chip adhesive, or cracks in the sealing resin may occur. There is a problem that the connection portion between the semiconductor chip and the wiring pattern is easily peeled off to cause poor electrical connection. A similar poor connection phenomenon may occur in advance in the semiconductor chip / adhesive material due to the fact that the solvent component contained in the adhesive material is not removed in the semiconductor chip adhering process and the followability between the semiconductor chip surface and the adhesive material surface is poor. It is also caused by the formation of voids at the interface. The present invention provides a semiconductor package that can reduce electrical connection failure due to blistering or peeling in the solder reflow process.
【０００７】[0007]
【課題を解決するための手段】本願の発明は、（Ａ）可
とう性を有する絶縁ベース基板、絶縁ベース基板の片面
に形成され半導体チップ電極と電気的に接続される配線
パターン、絶縁ベース基板の他の面に形成された外部接
続端子により構成される半導体チップ搭載用基板、
（Ｂ）半導体チップ搭載用基板に接着材を介して接着さ
れた、配線パターンと電気的に接続された半導体チッ
プ、（Ｃ）半導体チップを封止する封止樹脂とにより成
る半導体パッケージであり、（Ｄ）半導体チップが搭載
される領域であって外部接続端子が設けられない領域
に、絶縁ベース基板及び接着材を貫通し半導体チップに
達する凹部を有し、その開口面積が５〜２５ｍｍ ２ であ
ることを特徴とする半導体パッケージである。また、本
発明は前記の半導体パッケージに用いる半導体チップ搭
載用基板である。The invention of the present application is (A) an insulating base substrate having flexibility, a wiring pattern formed on one surface of the insulating base substrate and electrically connected to a semiconductor chip electrode, and an insulating base substrate. A semiconductor chip mounting substrate composed of external connection terminals formed on the other surface of
(B) a semiconductor package that is bonded to a semiconductor chip mounting substrate via an adhesive and is electrically connected to a wiring pattern; and (C) a semiconductor resin that seals the semiconductor chip. (D) a region where the semiconductor chip is mounted in a region where the external connection terminal is not provided, penetrating the insulating base substrate and the adhesive material have a recess that reaches the semiconductor chip, the opening area of at 5 to 25 mm 2 Ah
A semiconductor package, characterized in that that. Further, the present invention is a semiconductor chip mounting substrate used for the above semiconductor package.
【０００８】[0008]
【発明の実施の形態】図１は本発明の半導体パッケージ
の一例を示すもので、１は絶縁ベース基板、２は配線パ
ターン、３はフィルム状接着材等の接着材、４は半導体
チップ、５は金ワイヤ、６は外部接続端子、７は封止樹
脂、８は凹部を示す。図１（ａ）及び（ｂ）は、それぞ
れ本発明の半導体パッケージの断面図及び裏面図（外部
接続端子６側から見た平面図）である。本発明において
は、外部端子６側から半導体チップ４に達する凹部８を
設ける、すなわち半導体パッケージ中央領域（半導体チ
ップ４が搭載される領域であって外部接続端子６が設け
られない領域）の絶縁ベース基板１及び接着材３を予め
除去しておくことにより、ベース基板１／配線パターン
２間の界面、配線パターン２／半導体チップ接着用接着
材３間の界面、ベース基板１／半導体チップ接着用接着
材３間及び半導体チップ３／半導体チップ接着用接着材
３間の界面などの界面にトラップされた水が気化する際
の蒸気を逃がすことができるようにしたものである。更
に、半導体チップ接着工程で接着材中に残存する溶剤分
や半導体チップ／接着材間の界面に形成された非追従部
などに起因するボイドはチップ圧着時に搭載領域の中央
部に集まりやすいため、中央領域の絶縁ベース基板１及
び接着材３を予め除去しておくことにより特に半導体チ
ップ／接着材界面でのボイドを効率良く逃がすことがで
きる。DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS FIG. 1 shows an example of a semiconductor package of the present invention. 1 is an insulating base substrate, 2 is a wiring pattern, 3 is an adhesive such as a film adhesive, 4 is a semiconductor chip, and 5 is a semiconductor chip. Is a gold wire, 6 is an external connection terminal, 7 is a sealing resin, and 8 is a recess. 1A and 1B are a cross-sectional view and a back view (a plan view seen from the external connection terminal 6 side) of a semiconductor package of the present invention, respectively. In the present invention, the concave portion 8 reaching the semiconductor chip 4 from the external terminal 6 side is provided, that is, the insulating base in the central region of the semiconductor package (the region where the semiconductor chip 4 is mounted and the external connection terminal 6 is not provided). By removing the substrate 1 and the adhesive material 3 in advance, the interface between the base substrate 1 / wiring pattern 2, the interface between the wiring pattern 2 / adhesive material 3 for semiconductor chip adhesion, and the adhesion for base substrate 1 / semiconductor chip adhesion The vapor when water trapped at the interface between the materials 3 and the interface between the semiconductor chip 3 and the adhesive material 3 for bonding the semiconductor chip is vaporized can be released. Further, voids caused by the solvent remaining in the adhesive in the semiconductor chip bonding process and the non-following portion formed at the interface between the semiconductor chip and the adhesive are likely to be gathered in the central portion of the mounting area during the pressure bonding of the chip. By removing the insulating base substrate 1 and the adhesive material 3 in the central region in advance, voids at the semiconductor chip / adhesive material interface can be efficiently released.
【０００９】この場合、凹部８の開口面積は５〜２５ｍ
ｍ ２ 程度確保し単一の凹部であることが好ましい。凹部
８を設ける位置は、半導体チップ４が搭載される領域で
あって外部接続端子６が設けられない領域であれば任意
に設定可能である。凹部８は外部接続端子が設けられな
い領域のほぼ全面に設けることができる。本願の発明に
おいては、パッケージ化した後、必要に応じて凹部８に
所定量の封止樹脂を充填することも可能である。封止樹
脂を充填することにより、凹部８の側壁外部からの水の
浸入を低減することができる。絶縁ベース基板にはポリ
イミドフィルムなどの高分子フィルムや０．１ｍｍ厚程
度のガラス布基材などが適用可能である。また、接着材
としてはペースト状のものも適用できるが、フィルム状
接着材が好ましい。In this case, the opening area of the recess 8 is 5 to 25 m.
It is preferable to secure about m 2 and to have a single recess. The position where the concave portion 8 is provided can be arbitrarily set in a region where the semiconductor chip 4 is mounted and where the external connection terminal 6 is not provided. The concave portion 8 can be provided on almost the entire surface of the area where the external connection terminal is not provided. In the invention of the present application, it is also possible to fill the recess 8 with a predetermined amount of sealing resin after packaging, if necessary. By filling the sealing resin, it is possible to reduce the intrusion of water from the outside of the sidewall of the recess 8. A polymer film such as a polyimide film or a glass cloth base material having a thickness of about 0.1 mm can be applied to the insulating base substrate. Further, as the adhesive, a paste-like adhesive can be applied, but a film-like adhesive is preferable.
【００１０】[0010]
【実施例】幅５０８ｍｍ、厚さ５０μｍのポリイミドフ
ィルム（宇部興産製、商品名ＵＰＩＬＥＸＳ−Ｔｙｐ
ｅ）の両面に熱硬化性ポリイミド接着材用ワニスを所定
量塗布し、１６０℃１０分、１８０℃５分の乾燥により
第１の接着材層（厚さ８μｍ）及び第２の接着材層（厚
さ５μｍ）をポリイミドフィルムの両面に形成した。次
に、２５０ｍｍ角にシートカット後、ＮＣドリル加工機
を用いて０．３ｍｍφの貫通穴を所定数設けた。加工条
件は、回転数８０，０００ｒｐｍ、ドリル送り速度１２
ｍ／分である。１８０℃で２０分間プリベーク後、厚さ
１２μｍの電解銅箔（日本電解（株）製、商品名ＳＬ
Ｐ）の粗化面を内側にして第１の接着材層と向かい合わ
せ、加熱・加圧により銅箔と接着材層とを接着させて非
貫通穴（外部接続端子６形成用）を形成した。加熱・加
圧条件は、圧力３０ｋｇｆ／ｃｍ2、温度２５０℃であ
る。なお、銅箔と反対側の第２の接着材層が鏡板に接着
しないように、厚さ５０μｍのテフロンフィルムを第２
の接着材層に面して構成した。次に、銅箔面にドライフ
ィルムレジスト（日立化成工業（株）製、商品名フォテ
ックＨＫ８２５）をラミネートし、露光・現像により所
望する複数組のレジストパターンを形成した。ラミネー
ト条件は、ロール圧力２．０ｋｇｆ／ｃｍ2、ロール温
度１００℃、送り速度１．０ｍ／分である。露光はオー
ク（株）製平行露光機（ＥＸＭ−１６００−Ａ）を使用
し、露光量８０ｍＪ／ｃｍ2で行なった。現像は、炭酸
ナトリウム溶液（液温２８℃、液濃度１．０ｗｔ％）を
使用し、スプレー圧力１．５ｋｇｆ／ｃｍ2で行なっ
た。Example A polyimide film having a width of 508 mm and a thickness of 50 μm (produced by Ube Industries, trade name UPILEXS-Type
A predetermined amount of varnish for thermosetting polyimide adhesive is applied to both surfaces of e) and dried at 160 ° C. for 10 minutes and 180 ° C. for 5 minutes to form a first adhesive layer (thickness 8 μm) and a second adhesive layer ( A thickness of 5 μm) was formed on both sides of the polyimide film. Then, after cutting the sheet into a 250 mm square, a predetermined number of 0.3 mmφ through holes were provided using an NC drilling machine. Processing conditions are rotation speed 80,000 rpm, drill feed rate 12
m / min. After prebaking at 180 ° C for 20 minutes, electrolytic copper foil with a thickness of 12 µm (Nippon Denki Co., Ltd., trade name SL
The roughened surface of P) faces the first adhesive material layer with the roughened surface facing inward, and the copper foil and the adhesive material layer are bonded by heating and pressurization to form a non-through hole (for forming the external connection terminal 6). . The heating / pressurizing conditions are a pressure of 30 kgf / cm 2 and a temperature of 250 ° C. In addition, in order to prevent the second adhesive layer on the side opposite to the copper foil from adhering to the mirror plate, a Teflon film with a thickness of 50 μm
Facing the adhesive layer. Next, a dry film resist (trade name: Fotec HK825, manufactured by Hitachi Chemical Co., Ltd.) was laminated on the copper foil surface, and a desired plurality of resist patterns were formed by exposure and development. The laminating conditions are a roll pressure of 2.0 kgf / cm 2 , a roll temperature of 100 ° C. and a feed rate of 1.0 m / min. The exposure was performed using a parallel exposure machine (EXM-1600-A) manufactured by Oak Co., Ltd. with an exposure amount of 80 mJ / cm 2 . The development was carried out using a sodium carbonate solution (liquid temperature 28 ° C., liquid concentration 1.0 wt%) and spray pressure 1.5 kgf / cm 2 .
【００１１】次に、塩化第二鉄溶液（液温３８℃、ボー
メ度４０）を用いて所望する領域の銅箔をエッチング除
去後、水酸化カリウム溶液（液温３８℃、液濃度３ｗｔ
％）を用いてレジストパターンを剥離して複数組の配線
パターンを得た。次に、２５０ｍｍ角シートを所定のフ
レーム形状に打ち抜き加工後、露出する配線パターン及
び層間接続部面に無電解ニッケル（厚さ７μｍ）、続い
て、金めっき（厚さ０．７μｍ）を施した。次に、絶縁
接着フィルムを温度１６０℃、圧力２０ｋｇｆ／ｃ
ｍ2、時間１０秒で仮圧着後、直径５ｍｍのパンチ穴
（凹部８形成用）を加工した。次に、半導体チップを温
度２４０℃、圧力２００ｇ、時間８秒で半導体チップを
本圧着した後、ワイヤボンダー（新川製、装置名 ＵＴ
Ｃ−２３０ＢＩ）を用いて金ワイヤによりチップ電極と
配線パターンの所望する箇所を電気的に接続させた。ボ
ンディング条件は、温度１８０℃、荷重１００ｇ、超音
波１００、時間２０ｍｓｅｃ等である。次に、半導体封
止用エポキシ樹脂（日立化成工業（株）製、商品名ＣＥ
Ｌ−９２００）を用いてトランスファーモールド法によ
りチップを封止した。封止条件は、温度１８０℃、圧力
８０ｋｇｆ／ｃｍ2、封止時間９０秒である。次に、外
部接続端子面にフラックス処理を施した後、はんだボー
ルを配置し、赤外線リフロー炉で２４０℃、１０秒間リ
フローさせて外部接続端子部を形成した。最後に、フレ
ームで連結されたパッケージを金型で打ち抜き、個々の
パッケージに分割し、半導体パッケージを得た。Next, after removing the copper foil in a desired region by etching with a ferric chloride solution (liquid temperature 38 ° C., Baume degree 40), potassium hydroxide solution (liquid temperature 38 ° C., liquid concentration 3 wt)
%) To remove the resist pattern to obtain a plurality of sets of wiring patterns. Next, after punching a 250 mm square sheet into a predetermined frame shape, electroless nickel (thickness 7 μm) and then gold plating (thickness 0.7 μm) were applied to the exposed wiring pattern and interlayer connection surface. . Next, the insulating adhesive film is heated at a temperature of 160 ° C and a pressure of 20 kgf / c
After temporary pressure bonding at m 2 for 10 seconds, a punch hole (for forming the recess 8) having a diameter of 5 mm was processed. Next, after the semiconductor chip was subjected to main pressure bonding at a temperature of 240 ° C., a pressure of 200 g, and a time of 8 seconds, a wire bonder (manufactured by Shinkawa, device name UT
C-230BI) was used to electrically connect the chip electrode and a desired portion of the wiring pattern with a gold wire. The bonding conditions are a temperature of 180 ° C., a load of 100 g, an ultrasonic wave of 100, and a time of 20 msec. Next, epoxy resin for semiconductor encapsulation (manufactured by Hitachi Chemical Co., Ltd., product name CE
L-9200) was used to seal the chip by a transfer molding method. The sealing conditions are a temperature of 180 ° C., a pressure of 80 kgf / cm 2 , and a sealing time of 90 seconds. Next, after performing a flux treatment on the surface of the external connection terminals, solder balls were arranged and reflowed at 240 ° C. for 10 seconds in an infrared reflow furnace to form external connection terminal portions. Finally, the packages connected by the frame were punched out by a die and divided into individual packages to obtain semiconductor packages.
【００１２】[0012]
【発明の効果】本発明により、はんだリフロー工程のふ
くれや剥がれなどに起因する電気的接続不良を低減可能
な半導体パッケージを安定して提供することが可能とな
った。As described above, according to the present invention, it is possible to stably provide a semiconductor package capable of reducing electrical connection failure due to blistering or peeling in the solder reflow process.
【図１】 本発明の半導体パッケージを示すもので、
（ａ）は（ｂ）のＩーＩ’線断面図、（ｂ）は裏面図。1 shows a semiconductor package of the present invention,
(A) is a sectional view taken along the line II 'of (b), and (b) is a rear view.
１．ベース基板 ２．配線パターン ３．接着材 ４．半導体チップ ５．金ワイヤ ６．外部接続端子 ７．封止樹脂 ８．凹部 1. Base substrate 2. Wiring pattern 3. Adhesive 4. Semiconductor chip 5. Gold wire 6. External connection terminal 7. Sealing resin 8. Recess
───────────────────────────────────────────────────── フロントページの続き (72)発明者 市村 茂樹 茨城県つくば市和台48 日立化成工業株 式会社 筑波開発研究所内 (72)発明者 田口 矩之 茨城県つくば市和台48 日立化成工業株 式会社 筑波開発研究所内 (56)参考文献 特開 平７−212013（ＪＰ，Ａ) 特開 平７−169794（ＪＰ，Ａ) 特開 平５−218107（ＪＰ，Ａ) 特開 平４−241444（ＪＰ，Ａ) 実開 昭62−145337（ＪＰ，Ｕ) 実開 平２−70447（ＪＰ，Ｕ) 実開 平１−115247（ＪＰ，Ｕ) 特表 平７−500947（ＪＰ，Ａ) (58)調査した分野(Int.Cl.7，ＤＢ名) H01L 23/12 ─────────────────────────────────────────────────── ─── Continuation of front page (72) Inventor Shigeki Ichimura 48 Wadai, Tsukuba, Ibaraki Prefecture Hitachi Chemical Co., Ltd. Tsukuba Development Laboratory (72) Inventor Noriyuki Taguchi 48 Wadai, Tsukuba, Ibaraki Hitachi Chemical Co., Ltd. Incorporated company Tsukuba Development Laboratory (56) Reference JP 7-212013 (JP, A) JP 7-169794 (JP, A) JP 5-218107 (JP, A) JP 4- 241444 (JP, A) Actually open 62-145337 (JP, U) Actually open 2-70447 (JP, U) Actually open 1-115247 (JP, U) Special table 7-500947 (JP, A) (58) Fields investigated (Int.Cl. 7 , DB name) H01L 23/12
Claims (4)
板、絶縁ベース基板の片面に形成され半導体チップ電極
と電気的に接続される配線パターン、絶縁ベース基板の
他の面に形成された外部接続端子により構成される半導
体チップ搭載用基板、（Ｂ）半導体チップ搭載用基板に
接着材を介して接着された、配線パターンと電気的に接
続された半導体チップ、（Ｃ）半導体チップを封止する
封止樹脂とにより成る半導体パッケージであり、（Ｄ）
半導体チップが搭載される領域であって外部接続端子が
設けられない領域に、絶縁ベース基板及び接着材を貫通
し半導体チップに達する凹部を有し、その開口面積が５
〜２５ｍｍ ２ であることを特徴とする半導体パッケー
ジ。1. An insulating base substrate having flexibility (A), a wiring pattern formed on one surface of the insulating base substrate and electrically connected to a semiconductor chip electrode, and an external surface formed on the other surface of the insulating base substrate. A semiconductor chip mounting substrate composed of connection terminals, (B) a semiconductor chip which is adhered to the semiconductor chip mounting substrate via an adhesive and is electrically connected to a wiring pattern, and (C) a semiconductor chip is sealed. (D)
In the region where the semiconductor chip is mounted and where the external connection terminal is not provided, there is a recess that penetrates the insulating base substrate and the adhesive and reaches the semiconductor chip, and the opening area is 5
Semiconductor package, which is a 25 mm 2.
１記載の半導体パッケージ。2. The semiconductor package according to claim 1, wherein the adhesive is a film adhesive.
封止樹脂を充填させた請求項１または２記載の半導体パ
ッケージ。To 3. A recess reaching the semiconductor chip, a semiconductor package according to claim 1 or 2, wherein was filled with a predetermined amount of the sealing resin.
に形成され半導体チップ電極と電気的に接続される配線
パターン、絶縁ベース基板の他の面に形成された外部接
続端子を有し、さらに、半導体チップが搭載される領域
であって外部接続端子が設けられない領域に、絶縁ベー
ス基板を貫通する貫通穴を有し、その開口面積が５〜２
５ｍｍ ２ である請求項１〜３のいずれかに記載の半導体
パッケージに用いる半導体チップ搭載用基板。4. A wiring pattern formed on one surface of a flexible insulating base substrate and electrically connected to a semiconductor chip electrode, and an external connection terminal formed on the other surface of the insulating base substrate. A through hole penetrating the insulating base substrate is provided in a region where the semiconductor chip is mounted and no external connection terminal is provided, and the opening area is 5 to 2
A semiconductor chip mounting board used for a semiconductor package according to any one of claims 1 to 3 which is 5 mm 2.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP30900195A JP3534214B2 (en) | 1995-11-28 | 1995-11-28 | Semiconductor package and substrate for mounting semiconductor chip used therein |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP30900195A JP3534214B2 (en) | 1995-11-28 | 1995-11-28 | Semiconductor package and substrate for mounting semiconductor chip used therein |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH09148475A JPH09148475A (en) | 1997-06-06 |
| JP3534214B2 true JP3534214B2 (en) | 2004-06-07 |
Family
ID=17987724
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP30900195A Expired - Lifetime JP3534214B2 (en) | 1995-11-28 | 1995-11-28 | Semiconductor package and substrate for mounting semiconductor chip used therein |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP3534214B2 (en) |
Families Citing this family (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| AU2854199A (en) * | 1998-03-23 | 1999-10-18 | Seiko Epson Corporation | Semiconductor device, manufacture of semiconductor device, circuit board and electronic device |
| US6333565B1 (en) | 1998-03-23 | 2001-12-25 | Seiko Epson Corporation | Semiconductor device and method of manufacturing the same, circuit board, and electronic instrument |
| KR100880814B1 (en) * | 2005-04-18 | 2009-01-30 | 가부시키가이샤 무라타 세이사쿠쇼 | Electronic component module |
-
1995
- 1995-11-28 JP JP30900195A patent/JP3534214B2/en not_active Expired - Lifetime
Also Published As
| Publication number | Publication date |
|---|---|
| JPH09148475A (en) | 1997-06-06 |
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