KR100607626B1 - Flat coating process with utilizing a resin coated copper for printed circuit board - Google Patents

Flat coating process with utilizing a resin coated copper for printed circuit board Download PDF

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KR100607626B1
KR100607626B1 KR1020040037419A KR20040037419A KR100607626B1 KR 100607626 B1 KR100607626 B1 KR 100607626B1 KR 1020040037419 A KR1020040037419 A KR 1020040037419A KR 20040037419 A KR20040037419 A KR 20040037419A KR 100607626 B1 KR100607626 B1 KR 100607626B1
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copper foil
printed circuit
circuit board
resin
resin coated
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KR1020040037419A
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KR20050112365A (en
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최홍천
윤상근
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대덕전자 주식회사
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    • A—HUMAN NECESSITIES
    • A01—AGRICULTURE; FORESTRY; ANIMAL HUSBANDRY; HUNTING; TRAPPING; FISHING
    • A01C—PLANTING; SOWING; FERTILISING
    • A01C15/00—Fertiliser distributors
    • A—HUMAN NECESSITIES
    • A01—AGRICULTURE; FORESTRY; ANIMAL HUSBANDRY; HUNTING; TRAPPING; FISHING
    • A01C—PLANTING; SOWING; FERTILISING
    • A01C3/00—Treating manure; Manuring
    • A01C3/06—Manure distributors, e.g. dung distributors
    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B62—LAND VEHICLES FOR TRAVELLING OTHERWISE THAN ON RAILS
    • B62D—MOTOR VEHICLES; TRAILERS
    • B62D59/00—Trailers with driven ground wheels or the like
    • A—HUMAN NECESSITIES
    • A01—AGRICULTURE; FORESTRY; ANIMAL HUSBANDRY; HUNTING; TRAPPING; FISHING
    • A01C—PLANTING; SOWING; FERTILISING
    • A01C19/00—Arrangements for driving working parts of fertilisers or seeders
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02P—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN THE PRODUCTION OR PROCESSING OF GOODS
    • Y02P60/00—Technologies relating to agriculture, livestock or agroalimentary industries

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  • Soil Sciences (AREA)
  • Environmental Sciences (AREA)
  • Engineering & Computer Science (AREA)
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  • Transportation (AREA)
  • Mechanical Engineering (AREA)
  • Production Of Multi-Layered Print Wiring Board (AREA)

Abstract

본 발명은 고중량 동박 인쇄 회로 기판 제작시 적층 공정에 관한 것으로, 레진 도포된 동박을 이용한 평탄 코팅 제조 방법에 관한 것이다. 본 발명은 글래스 섬유 층이 함유되지 않은 레진 도포된 동박을 빌드업 재료로 사용함으로써 내층 인쇄 회로 기판의 적층 평탄화 코팅 작업에서 패턴 된 동박 사이에 보이드가 발생하는 문제를 해결하게 된다. BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a lamination process in fabricating a heavy weight copper foil printed circuit board, and to a method of manufacturing a flat coating using a resin coated copper foil. The present invention solves the problem that voids are generated between patterned copper foils in a lamination planarizing coating operation of an inner layer printed circuit board by using a resin coated copper foil containing no glass fiber layer as a build-up material.

인쇄 회로 기판, 빌드업 적층, RCC, 프리프레그, 다층 배선.Printed circuit boards, buildup stacking, RCCs, prepregs, multilayer wiring.

Description

인쇄 회로 기판에 있어서 레진 도포된 동박을 이용한 평탄 코팅 공법{FLAT COATING PROCESS WITH UTILIZING A RESIN COATED COPPER FOR PRINTED CIRCUIT BOARD}Flat coating method using resin coated copper foil on a printed circuit board {FAT COATING PROCESS WITH UTILIZING A RESIN COATED COPPER FOR PRINTED CIRCUIT BOARD}

도1은 종래 기술에 따른 다층 배선 인쇄 회로 기판 제조 공법을 나타낸 도면.1 is a view showing a multilayer wiring printed circuit board manufacturing method according to the prior art.

도2a 및 도2b는 본 발명에 따라 인쇄 회로 기판을 제조하는 공정을 모식적으로 도시한 도면.2A and 2B are diagrams schematically showing a process of manufacturing a printed circuit board according to the present invention.

<도면의 주요 부분에 대한 부호의 설명><Explanation of symbols for the main parts of the drawings>

1 : 인쇄 회로 기판, 내층 코아 기판1: printed circuit board, inner layer core board

10 : 절연층10: insulation layer

11 : 코아 층의 동박, 내층 회로11: copper foil of core layer, inner layer circuit

20 : 프리프레그20: prepreg

21 : 글래스 섬유층21: glass fiber layer

38 : RCC의 절연부38: insulation of RCC

40 : RCC40: RCC

본 발명은 고중량 동박의 인쇄 회로 기판 제작을 적층 공정에 관한 것으로, 보다 상세하게는 레진 도포된 동박(Resin-coated Copper; 이하, "RCC"라 칭함)을 이용한 평탄 코팅 제조 방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a lamination process for fabricating printed circuit boards of heavy weight copper foil, and more particularly, to a method of manufacturing a flat coating using resin-coated copper (hereinafter, referred to as "RCC").

통상적으로 인쇄 회로 기판에서 사용되는 동박(copper)은 0.5 ∼ 2.0 온스(oz)의 규격이 사용되는데, 이 경우 동박의 두께는 보통 70㎛ 이하가 된다. 예를 들어, 고전류가 필요한 인쇄 회로 기판의 경우에 내층의 동박(copper)의 단면적을 크게 하는 것이 바람직하다. 동박의 단면적을 크게 하는 방법으로서 인쇄 회로 기판의 동박의 두께를 두껍게 하여야 하는데 보통 4온스(oz) 정도의 고중량 동박(heavy copper)이 인쇄 회로 기판에 적용된다.Typically, a copper foil used in a printed circuit board is used in a size of 0.5 to 2.0 ounces, in which case the thickness of the copper foil is usually 70 μm or less. For example, in the case of a printed circuit board requiring a high current, it is preferable to increase the cross-sectional area of the copper foil of the inner layer. As a method of increasing the cross-sectional area of the copper foil, the thickness of the copper foil of the printed circuit board must be thickened, and heavy copper copper of about 4 oz (oz) is usually applied to the printed circuit board.

그런데, 4 온스 정도의 동박이 사용되는 경우, 그 두께가 약 140㎛ 정도가 되는데, 이와 같이 두께가 두꺼운 동박을 구비한 인쇄 회로 기판에 다층 배선을 구성하는 경우에 적층 단계에서 레진이 패턴된 동박 사이의 공간에 충진 되지 않는 문제가 발생하게 된다.By the way, when the copper foil of about 4 ounces is used, the thickness becomes about 140 micrometers. When the multilayer wiring is comprised on the printed circuit board provided with such a thick copper foil, the copper foil by which resin was patterned by the lamination | stacking step is carried out. There is a problem of not filling the space between.

즉, 도1에 도시한 종래 기술에 따른 다층 배선 인쇄 회로 기판 제조 공법을 참조하면, 종래 기술의 경우에는 적층 공정에서 글래스 섬유층(glass wool)에 레진 (resin)을 함침시켜 제작한 프리프레그(Prepreg; 20)를 고온 고압에서 압착시킴으로써 패턴 사이를 채우는 공법에 의존하고 있다.That is, referring to the method for manufacturing a multilayer wiring printed circuit board according to the prior art shown in FIG. 1, in the case of the prior art, a prepreg manufactured by impregnating a resin in a glass wool layer in a lamination process is prepared. 20) is squeezed at high temperature and high pressure to rely on a method of filling between patterns.

그런데, 도1에 도시되어 있듯이 종래 기술에 사용되고 있는 프리프레그(20)는 동박(22)에 레진이 함침된 글래스 섬유층(21)을 고온 고압에서 압착하게 되므로, 코아 층의 동박(11)의 턱이 140㎛ 정도로 두꺼운 경우에 동박 패턴 사이에 보이드(void; 30a, 30b, 30c, 30d)가 형성될 수 있다.However, as shown in FIG. 1, the prepreg 20 used in the prior art compresses the glass fiber layer 21 in which the resin is impregnated with the copper foil 22 at high temperature and high pressure, and thus, the jaw of the copper foil 11 of the core layer. When the thickness is about 140 µm, voids 30a, 30b, 30c, and 30d may be formed between the copper foil patterns.

이와 같이, 보이드가 생성되는 경우 후 열처리 과정에서 딜래미네이션 (delamination)과 같은 불량 발생의 원인이 된다. 전술한 문제를 해결하기 위하여 에폭시 재질을 이용하여 동박 단차 부분을 인쇄하는 공법도 시도되고 있다. 그런데, 전술한 인쇄 공법을 채용하는 경우 양산 적용이 용이하지 않아 원가 상승의 원인이 된다. As such, when voids are generated, defects such as delamination may occur during the post-heat treatment. In order to solve the above-mentioned problem, a method of printing a copper foil step portion using an epoxy material has also been attempted. However, when the printing method described above is adopted, mass production is not easy, which causes a cost increase.

따라서, 본 발명의 목적은 고중량 동박을 인쇄 회로 기판 제작시 적층 공정에 있어서 충진이 완전히 이루어지지 않아 보이드가 발생하는 문제를 해결하는 평탄 코팅 공법을 제공하는데 있다. Accordingly, it is an object of the present invention to provide a flat coating method for solving a problem in which voids are generated due to filling of a heavy copper foil in a lamination process during fabrication of a printed circuit board.

상기 목적을 달성하기 위하여, 본 발명은 절연층(10)을 가운데 두고 절연층의 상부면과 하부면에 패턴 형성된 동박 회로(11)의 동박 두께가 100 ㎛ 이상인 고전류 동박 회로(11)를 구비한 내층 코아 기판(1)에, 절연층의 일면에 동박이 도포된 외층 회로를 적층하는 방법에 있어서, 글래스 섬유가 함침되지 않고 레진(resin)만으로 형성된 레진 도포된 동박(RCC)을, 레진이 형성된 면을 상기 내층 코아 기판(1)에 면하도록 하여 핫 프레스함으로써 표면을 평탄화하는 단계; 내층 코아 기판(1) 위에 평탄 코팅된 레진 도포된 동박의 동박을 제거하는 단계; 레진에 의해 평탄화된 기판 위에 절연층의 일면에 동박이 도포된 외층 회로를 적층하는 단계를 포함하는 인쇄 회로 기판 제조 방법을 제공한다.In order to achieve the above object, the present invention includes a high current copper foil circuit 11 having a copper foil thickness of 100 μm or more in a patterned copper foil circuit 11 formed on the upper and lower surfaces of the insulating layer with the insulating layer 10 in the center. In the method of laminating the outer layer circuit in which copper foil is applied to one surface of the insulating layer on the inner core substrate 1, the resin coated copper foil (RCC) formed of only resin without impregnated with glass fibers is formed with resin. Planarizing the surface by hot pressing the surface facing the inner core substrate (1); Removing the copper foil of the resin coated copper foil flat coated on the inner core substrate (1); It provides a printed circuit board manufacturing method comprising the step of laminating an outer layer circuit coated with copper foil on one surface of the insulating layer on a substrate planarized by a resin.

이하에서는, 첨부 도면 도2a 및 도2b를 참조하여 본 발명에 따른 다층 인쇄 회로 기판 제조 방법을 상세히 설명한다. Hereinafter, a method of manufacturing a multilayer printed circuit board according to the present invention will be described in detail with reference to FIGS. 2A and 2B.

본 발명은 종래에 사용되던 프리프레그에 비하여 레진(resin) 함유 비율이 높은 레진 도포된 동박(RCC; resin coated copper)을 이용하여 내층 코아의 패턴 사이를 채우는 공법을 이용하는 것을 특징으로 한다.The present invention is characterized by using a method of filling a pattern between inner core cores using a resin coated copper (RCC) having a higher resin content than a prepreg used in the related art.

도2a 및 도2b는 본 발명에 따라 인쇄 회로 기판을 제조하는 공정을 모식적으로 도시한 도면이다. 도2a를 참조하면, 내층 회로부를 구성하는 인쇄 회로 기판(1)은 절연층 (10)과 내층 회로(11)를 포함하며, 회로 디자인에 따라 이너(inner) 비아홀(도시하지 않음)을 포함하기도 한다. 내층 코아 기판(1)는 2층 이상으로 구성될 수 있고 절연층(10)은 FR-4, PI, BT 등으로 이루어질 수 있다. 2A and 2B are diagrams schematically showing a process of manufacturing a printed circuit board according to the present invention. Referring to FIG. 2A, the printed circuit board 1 constituting the inner layer circuit portion includes an insulating layer 10 and an inner layer circuit 11, and may include inner via holes (not shown) according to a circuit design. do. The inner core substrate 1 may be composed of two or more layers, and the insulating layer 10 may be made of FR-4, PI, BT, or the like.

여기서, 고전류용 인쇄 회로 기판의 경우 4온스 정도의 고중량 동박을 사용할 경우 내층 회로(11)의 동박 두께가 140㎛ 정도가 된다. 이어서, 도2b를 참조하면 진공 밀착기 또는 핫 프레스를 이용하여 빌드업 공법을 이용하여 평탄 코팅이 진행되는데, 본 발명에서는 레진 도포된 동박 절연 재료로써 RCC(40)를 이용하는 것을 특징으로 한다. 본 발명에 따라 RCC(40)를 사용해서 코팅을 진행하면, 레진의 경우 섬유층이 없으므로 표면이 쉽게 평탄화되는 경향이 있다.Here, in the case of the high current printed circuit board, when the heavy weight copper foil of about 4 ounces is used, the copper foil thickness of the inner layer circuit 11 will be about 140 micrometers. Subsequently, referring to FIG. 2B, a flat coating is performed by using a build-up method using a vacuum contactor or a hot press. In the present invention, an RCC 40 is used as a resin coated copper foil insulating material. When the coating is performed using the RCC 40 according to the present invention, the resin tends to be flattened because there is no fiber layer.

도2b에 도시한 대로 본 발명에 따른 평탄 코팅 단계에 RCC(40)를 사용하는 것은, RCC의 절연부 (38)가 레진 함유 성분 퍼센트가 매우 높으므로(거의 100%), 고온 고압 핫 프레스 공정에서 고단차의 동박(11) 패턴 사이에 보이드 생성 없이 충진할 수 있게 된다. 본 발명의 양호한 실시예로서, 전술한 방법으로 내층 코아 위에 RCC(40)로 표면 위를 충진함으로써 표면을 평탄화 한 후에는 동박을 벗겨 내어 제거하고 그 위에 절연체 위에 동박이 코팅된, 예를 들어 프리프레그를 이용하여 다시 외층 회로를 적층할 수 있다. 이후의 공정은 종래 기술에 따라 진행될 수 있다. 이 때에, 앞서 지적한 바와 같이, 일단 내층 표면이 에폭시 수지 계열의 레진에 의해 평탄화가 완료되었으므로, 프리프레그와 같이 글래스 섬유가 함침된 외층 회로를 적층할 때에 보이드가 발생하지 않게 된다.The use of the RCC 40 in the flat coating step according to the present invention as shown in FIG. 2B is a high temperature, high pressure hot press process since the insulating portion 38 of the RCC has a very high percentage of resin containing components (almost 100%). In the step can be filled without generating voids between the high-step copper foil (11) pattern. In a preferred embodiment of the present invention, after flattening the surface by filling the surface with the RCC 40 on the inner core in the manner described above, the copper foil is peeled off and removed, and the copper foil is coated on the insulator, for example, a prep. The outer layer circuit can be laminated again using the legs. Subsequent processes may proceed according to the prior art. At this time, as noted above, once the inner layer surface has been planarized by an epoxy resin-based resin, voids do not occur when laminating an outer layer circuit impregnated with glass fibers, such as a prepreg.

전술한 내용은 후술할 발명의 특허 청구 범위를 보다 잘 이해할 수 있도록 본 발명의 특징과 기술적 장점을 다소 폭넓게 개설하였다. 본 발명의 특허 청구 범위를 구성하는 부가적인 특징과 장점들은 이하에서 상술될 것이다. 개시된 본 발명의 개념과 특정 실시예는 본 발명과 유사 목적을 수행하기 위한 다른 구조의 설계 나 수정의 기본으로 즉시 사용될 수 있음이 당해 기술 분야의 숙련된 사람들에 의해 인식되어야 한다.The foregoing has outlined rather broadly the features and technical advantages of the present invention to better understand the claims of the invention which will be described later. Additional features and advantages that make up the claims of the present invention will be described below. It should be appreciated by those skilled in the art that the conception and specific embodiments of the invention disclosed may be readily used as a basis for designing or modifying other structures for carrying out similar purposes to the invention.

또한, 본 발명에서 개시된 발명 개념과 실시예가 본 발명의 동일 목적을 수행하기 위하여 다른 구조로 수정하거나 설계하기 위한 기초로서 당해 기술 분야의 숙련된 사람들에 의해 사용되어질 수 있을 것이다. 또한, 당해 기술 분야의 숙련된 사람에 의한 그와 같은 수정 또는 변경된 등가 구조는 특허 청구 범위에서 기술한 발명의 사상이나 범위를 벗어나지 않는 한도 내에서 다양한 변화, 치환 및 변경이 가능하다.In addition, the inventive concepts and embodiments disclosed herein may be used by those skilled in the art as a basis for modifying or designing other structures for carrying out the same purposes of the present invention. In addition, such modifications or altered equivalent structures by those skilled in the art may be variously changed, substituted, and changed without departing from the spirit or scope of the invention described in the claims.

이상과 같이, 본 발명은 글래스 섬유층이 함유되지 않은 레진 도포된 동박(RCC)을 빌드업 재료로 사용함으로써 내층 인쇄 회로 기판의 적층 평탄화 코팅 작업에서 패턴된 동박 사이에 보이드가 발생하는 문제를 해결하게 된다. As described above, the present invention solves a problem in which voids are generated between patterned copper foils in a lamination planarizing coating operation of an inner layer printed circuit board by using a resin coated copper foil (RCC) containing no glass fiber layer as a build-up material. do.

Claims (2)

절연층(10)을 가운데 두고 절연층의 상부면과 하부면에 패턴 형성된 동박 회로(11)의 동박 두께가 100 ㎛ 이상인 고전류 동박 회로(11)를 구비한 내층 코아 기판(1)에, 절연층의 일면에 동박이 도포된 외층 회로를 적층하는 방법에 있어서,Insulating layer on inner core core board 1 provided with high-current copper foil circuit 11 whose copper foil thickness of the copper foil circuit 11 patterned on the upper surface and lower surface of the insulating layer centering the insulating layer 10 is 100 micrometers or more. In a method of laminating an outer layer circuit coated with copper foil on one surface of (a) 글래스 섬유가 함침되지 않고 레진(resin)만으로 형성된 레진 도포된 동박(RCC)을, 레진이 형성된 면을 상기 내층 코아 기판(1)에 면하도록 하여 핫 프레스함으로써 표면을 평탄화하는 단계; (a) planarizing the surface by hot pressing a resin-coated copper foil (RCC) formed of resin only without impregnating glass fibers with the resin-formed surface facing the inner core core substrate (1); (b) 상기 단계 (a) 결과, 내층 코아 기판(1) 위에 평탄 코팅된 레진 도포된 동박의 동박을 제거하는 단계; 및(b) removing the copper foil of the resin-coated copper foil flat coated on the inner core substrate 1 as a result of step (a); And (c) 상기 단계 (b)에 후속하여, 상기 레진에 의해 평탄화된 기판 위에 절연층의 일면에 동박이 도포된 외층 회로를 적층하는 단계(c) subsequent to step (b), laminating an outer layer circuit coated with copper foil on one surface of the insulating layer on the substrate planarized by the resin; 를 포함하는 인쇄 회로 기판 제조 방법.Printed circuit board manufacturing method comprising a. 삭제delete
KR1020040037419A 2004-05-25 2004-05-25 Flat coating process with utilizing a resin coated copper for printed circuit board KR100607626B1 (en)

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Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2010030059A1 (en) * 2008-09-11 2010-03-18 Doosan Corporation Multi layer circuit board and manufacturing method of the same
KR101352819B1 (en) * 2010-04-23 2014-01-16 메이코 일렉트로닉스 컴파니 리미티드 Printed substrate manufacturing method and printed substrate employing same
KR101354372B1 (en) 2007-07-31 2014-01-23 삼성전자주식회사 Reinforce for printed circuit board and integrated circuit package using the same

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100814710B1 (en) * 2007-04-24 2008-03-18 조현귀 Heavy copper etching lamination pcb(printed circuit board) and method thereof

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH1027960A (en) 1996-07-09 1998-01-27 Mitsui Mining & Smelting Co Ltd Manufacture of multi-layer printed wiring board
JPH11266084A (en) * 1997-12-02 1999-09-28 Samsung Electro Mech Co Ltd Manufacture of multilayer printed circuit board
KR20010005137A (en) * 1999-06-30 2001-01-15 이형도 Method of manufacturing multi-layer printed circuit board
KR20020009794A (en) * 2000-07-27 2002-02-02 이형도 A method for manufacturing a multilayer printed circuit board having Blind via hole

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH1027960A (en) 1996-07-09 1998-01-27 Mitsui Mining & Smelting Co Ltd Manufacture of multi-layer printed wiring board
JPH11266084A (en) * 1997-12-02 1999-09-28 Samsung Electro Mech Co Ltd Manufacture of multilayer printed circuit board
KR20010005137A (en) * 1999-06-30 2001-01-15 이형도 Method of manufacturing multi-layer printed circuit board
KR20020009794A (en) * 2000-07-27 2002-02-02 이형도 A method for manufacturing a multilayer printed circuit board having Blind via hole

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR101354372B1 (en) 2007-07-31 2014-01-23 삼성전자주식회사 Reinforce for printed circuit board and integrated circuit package using the same
WO2010030059A1 (en) * 2008-09-11 2010-03-18 Doosan Corporation Multi layer circuit board and manufacturing method of the same
KR101352819B1 (en) * 2010-04-23 2014-01-16 메이코 일렉트로닉스 컴파니 리미티드 Printed substrate manufacturing method and printed substrate employing same

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