KR100606540B1 - Method for forming the copper interconnection of semiconductor device - Google Patents

Method for forming the copper interconnection of semiconductor device Download PDF

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KR100606540B1
KR100606540B1 KR1020040110161A KR20040110161A KR100606540B1 KR 100606540 B1 KR100606540 B1 KR 100606540B1 KR 1020040110161 A KR1020040110161 A KR 1020040110161A KR 20040110161 A KR20040110161 A KR 20040110161A KR 100606540 B1 KR100606540 B1 KR 100606540B1
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plasma
photoresist
forming
copper wiring
etching
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KR20060071544A (en
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이강현
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동부일렉트로닉스 주식회사
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
    • H01L21/76814—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics post-treatment or after-treatment, e.g. cleaning or removal of oxides on underlying conductors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3105—After-treatment
    • H01L21/311—Etching the insulating layers by chemical or physical means
    • H01L21/31105—Etching inorganic layers
    • H01L21/31111—Etching inorganic layers by chemical means
    • H01L21/31116—Etching inorganic layers by chemical means by dry-etching
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
    • H01L21/76807—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics for dual damascene structures

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  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
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  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)

Abstract

본 발명은 반도체 소자의 구리 배선 형성 방법에 관한 것으로, 보다 자세하게는 구리 배선 상에 형성된 소정 패턴의 1차 포토레지스트 하부에 존재하는 절연막을 RIE 방법으로 식각하는 단계; 상기 식각된 부위에 2차 포토레지스트를 채우는 단계; 상기 절연막 상부에 3차 포토레지스트를 도포하고 패터닝하는 단계; 상기 3차 패터닝된 포토레지스트를 식각 마스크로 하여 다단계 플라즈마 식각하여 듀얼 다마신 패턴을 형성하는 단계; 상기 듀얼 다마신 패턴의 표면을 세정하는 단계; 상기 듀얼 다마신 패턴에 배리어 금속막을 증착하는 단계; 및 상기 배리어 금속막이 증착된 패턴에 구리를 매립하는 단계로 이루어진 것을 특징으로 하는 반도체 소자의 구리 배선 형성 방법에 의해 달성된다. The present invention relates to a method for forming a copper wiring of a semiconductor device, and more particularly, etching the insulating film under the primary photoresist of a predetermined pattern formed on the copper wiring by an RIE method; Filling a secondary photoresist on the etched portion; Applying and patterning a tertiary photoresist on the insulating layer; Forming a dual damascene pattern by performing multi-step plasma etching using the third patterned photoresist as an etching mask; Cleaning the surface of the dual damascene pattern; Depositing a barrier metal film on the dual damascene pattern; And embedding copper in the pattern on which the barrier metal film is deposited.

따라서, 본 발명의 반도체 소자의 구리 배선 형성 방법은 전체 공정 수를 줄이고, 구리 표면을 깨끗하게 유지하므로써 반도체 소자의 수율을 향상시킬 수 있는 효과가 있다. Therefore, the copper wiring formation method of the semiconductor element of this invention has the effect which can improve the yield of a semiconductor element by reducing the whole process number and keeping a copper surface clean.

구리 배선, 듀얼 다마신, 다단계 플라즈마 식각Copper wiring, dual damascene, multilevel plasma etching

Description

반도체 소자의 구리 배선 형성 방법{Method for forming the copper interconnection of semiconductor device} Method for forming the copper interconnection of semiconductor device             

도 1a 내지 도 1c는 은 종래기술에 의한 반도체 소자의 구리 배선 형성 방법을 나타낸 도면.1A to 1C are views showing a method for forming a copper wiring of a semiconductor device according to the prior art.

도 2a 내지 도 2c는 본 발명에 의한 반도체 소자의 구리 배선 형성 방법을 나타낸 도면.2A to 2C are views showing a copper wiring formation method of a semiconductor device according to the present invention.

본 발명은 반도체 소자의 구리 배선 형성 방법에 관한 것으로, 보다 자세하게는 듀얼 다마신 공정에 의해 트렌치 식각을 할 경우 연속 다단계 플라즈마 식각으로 단일화하여 전체 공정 수를 줄이고, 구리 표면을 깨끗하게 유지하므로써 반도체 소자의 수율을 향상시킬 수 있는 반도체 소자의 구리 배선 형성 방법에 관한 것이다.The present invention relates to a method for forming a copper wiring of a semiconductor device, and more particularly, in the case of trench etching by a dual damascene process, by unifying a continuous multi-step plasma etching, the total number of processes is reduced, and the copper surface is kept clean. The present invention relates to a copper wiring formation method of a semiconductor device capable of improving yield.

최근 반도체 산업이 초대규모 직접회로(VLSI: Very Large-Scale Intergration), 극초대규모 집적회로(Ultra Large Scale Integration; ULSI)로 옮겨 가면서 소자의 집적도, 미세화, 동작속도 등을 향상시키는 방향으로 기술이 발전하고 있다. 소자의 디자인 룰(Design Rule)이 협소화되면서 0.3 마이크론 이하 공정에서는 RC 지연시간(Resistance Capacitance Delay Time) 문제를 해결하기 위한 일환으로 기존의 알루미늄 배선을 구리 배선으로 변경하고 있다. Recently, the semiconductor industry has moved to very large-scale integration (VLSI) and ultra large-scale integration (ULSI), and the technology has been developed in order to improve device integration, miniaturization and operation speed. Doing. As the design rule of the device is narrowed, the existing aluminum wiring is changed to copper wiring in order to solve the RC capacitance delay problem in the 0.3 micron or lower process.

일반적으로, 구리 배선 형성 공정은 알루미늄 배선과는 달리 산화막(Oxide Film)과(혹은) 질화막(Nitride Film)으로 패턴을 형성한 다음, 비아 홀과 트렌치를 식각하는데 이 때 생긴 자리를 구리로 증착하는 듀얼 다마신 기법을 이용한다. 다마신 공정을 통해 패턴이 형성되면 ECP(Electro Chemical Plating) 공정을 거쳐 구리 배선을 형성하게 된다. In general, unlike a copper wiring, a copper wiring forming process forms a pattern with an oxide film and / or a nitride film, and then etches via holes and trenches, and deposits a copper-deposited site. Use the dual damascene technique. When the pattern is formed through the damascene process, copper wiring is formed through an electrochemical plating (ECP) process.

도 1a 내지 도 1b는 종래 기술에 의한 반도체 소자의 구리 배선 형성 방법을 나타낸 도면이다. 1A to 1B are diagrams showing a method for forming a copper wiring of a semiconductor device according to the prior art.

먼저, 도 1a는 하부 금속 배선과 같은 소정의 소자가 형성된 기판상(101)에 절연막 증착, 사진식각, 포토레지스트 매립, 트렌치 식각하는 단계이다. 도에서 보는 바와같이 구리 배선 형성을 위한 트렌치를 만들기 위해 1차 포토레지스트(104) 하부에 존재하는 유전율이 낮은 FSG계 절연막(103)을 반응성 이온 식각(Reactive Ion Etching, 이하 RIE)한 뒤 형성되는 패턴에 2차 포토레지스트(105)를 매립하고, 상기 절연막 상부에 3차 포토레지스트(106)를 도포하고 패터닝한다. 이어서 상기 패터닝된 3차 포토레지스트를 식각 마스크로 하여 RIE 방법으로 식각하여 트렌치를 형성한다. First, FIG. 1A illustrates a step of depositing an insulating film, etching a photoresist, filling a photoresist, and trenching a trench on a substrate 101 on which a predetermined element such as a lower metal wiring is formed. As shown in FIG. 1, a reactive dielectric etch (RIE) of the low dielectric constant FSG-based insulating layer 103 under the primary photoresist 104 is formed to form a trench for forming a copper wiring. A secondary photoresist 105 is embedded in the pattern, and a tertiary photoresist 106 is applied and patterned on the insulating film. Subsequently, the trench is formed by etching the patterned tertiary photoresist using an RIE method using an etch mask.

다음, 도 1b 및 도 1c는 듀얼 다마신 패턴을 형성한 다음, 애싱, 질화막 RIE, 배리어 금속막 증착 및 구리 매립 단계이다. 도에서 보는 바와 같이 포토레지스트 제거를 위하여 애싱(Ashing) 처리하고, 구리 표면에 있는 질화막(102)을 CF4 가스로 플라즈마 식각한다. 이 때 상기 매립된 포토레지스트로 인해 부산물(107)이 생성되며, 트렌치 내에 잔류 CF4 가스와 질화막이 반응하여 폴리머성 부산물(108)이 생성되어 구리 표면과 절연막 측벽에 증착한다. 이어서, 듀얼 마디신 패턴 세정, 배리어 금속막(110) 증착 및 구리(112) 매립 순으로 진행된다. Next, FIGS. 1B and 1C illustrate a dual damascene pattern, followed by ashing, nitride RIE, barrier metal film deposition, and copper filling. As shown in the figure, ashing is performed to remove the photoresist, and the nitride film 102 on the copper surface is plasma-etched with CF 4 gas. At this time, the buried photoresist generates by-products 107, and a residual CF 4 gas and a nitride film react with each other to form a polymer by-product 108, which is deposited on a copper surface and an insulating film sidewall. Subsequently, the dual nodeine pattern cleaning, the barrier metal film 110 is deposited, and the copper 112 is embedded.

그러나, 상기와 같은 종래의 반도체 소자의 구리 배선 형성 방법은 여러 공정 단계를 거치게 되며, 포토레지스트 매립, 트렌치 RIE 및 질화막 RIE 공정에서 생성된 폴리머와 부산물은 후속 세정 공정에서 효과적으로 제거되지 않고 구리 표면에 잔류물(109)로 남아서 마스킹(Masking) 현상이 일으킴으로써, 식각되지 않는 영역이 존재할 뿐만 아니라, 후속 공정인 배리어 금속막 증착시 RC 저항이 증대되며, 구리막 내부에 미세 공간(Void)(111)이 발생하고, 전체 공정 시간(Total Around Time), 생산 비용 등이 증가하는 문제점이 있었다.However, the copper wiring formation method of the conventional semiconductor device as described above undergoes several process steps, and the polymers and by-products generated in the photoresist buried, trench RIE and nitride RIE processes are not effectively removed in the subsequent cleaning process. By remaining as a residue 109 and causing a masking phenomenon, not only the non-etched region exists, but also the RC resistance is increased during the deposition of the barrier metal film, which is a subsequent process, and a void (111) inside the copper film. ) Occurred, and the total process time (Total Around Time), production costs, etc. were increasing.

따라서, 본 발명은 상기와 같은 종래 기술의 문제점을 해결하기 위한 것으로, 트렌치 RIE, 포토레지트 스트립 및 질화막 RIE 공정을 단일 공정으로 간소화하여 전체 공정 수를 줄이고, 구리 표면을 깨끗하게 유지하므로써 반도체 소자의 수 율을 향상시킬 수 있는 반도체 소자의 구리 배선 형성 방법을 제공함에 본 발명의 목적이 있다.
Accordingly, the present invention is to solve the problems of the prior art as described above, by simplifying the trench RIE, photoresist strip and nitride film RIE process in a single process to reduce the overall number of processes, by keeping the copper surface clean It is an object of the present invention to provide a method for forming a copper wiring of a semiconductor device that can improve the yield.

본 발명의 상기 목적은 구리 배선 상에 형성된 소정 패턴의 1차 포토레지스트 하부에 존재하는 절연막을 RIE하는 단계, 상기 식각된 부위에 2차 포토레지스트를 채우는 단계, 상기 절연막 상부에 3차 포토레지스트를 도포하고 패터닝하는 단계, 상기 패터닝된 3차 포토레지스트를 식각 마스크로 하여 다단계 플라즈마 식각하여 듀얼 다마신 패턴을 형성하는 단계, 상기 듀얼 다마신 패턴의 표면을 세정하는 단계, 상기 듀얼 다마신 패턴에 배리어 금속막을 증착하는 단계 및 상기 배리어 금속막이 증착된 패턴에 구리를 매립하는 단계로 이루어진 것을 특징으로 하는 반도체 소자의 구리 배선 형성 방법에 의해 달성된다.The object of the present invention is to RIE the insulating film present in the lower portion of the primary photoresist of a predetermined pattern formed on the copper wiring, filling the secondary photoresist in the etched portion, tertiary photoresist on the insulating film Applying and patterning, forming a dual damascene pattern by performing multi-step plasma etching using the patterned tertiary photoresist as an etching mask, cleaning the surface of the dual damascene pattern, and barriering the dual damascene pattern A method of forming a copper wiring in a semiconductor device, comprising the steps of depositing a metal film and embedding copper in a pattern on which the barrier metal film is deposited.

본 발명의 상기 목적과 기술적 구성 및 그에 따른 작용효과에 관한 자세한 사항은 본 발명의 바람직한 실시예를 도시하고 있는 도면을 참조한 이하 상세한 설명에 의해 보다 명확하게 이해될 것이다.Details of the above object and technical configuration of the present invention and the effects thereof according to the present invention will be more clearly understood by the following detailed description with reference to the drawings showing preferred embodiments of the present invention.

도 2a 내지 도 2c는 본 발명에 의한 반도체 소자의 구리 배선 형성 방법을 나타낸 도면이다.2A to 2C are views showing a method for forming a copper wiring of a semiconductor device according to the present invention.

먼저, 도 2a 및 도 2b는 하부 금속 배선과 같은 소정의 소자가 형성된 기판(201)상에 절연막 증착, 사진식각, 포토레지스트 매립, 듀얼 다마신 형성 단계이다. 도에서 보는 바와같이 1차 포토레지스트(204) 하부에 존재하는 절연막(203)을 RIE방법으로 식각한 뒤 형성되는 패턴에 2차 포토레지스트(205)를 매립하고 상기 절연막 상부에 3차 포토레지스트(206)를 도포하고 패터닝한다. 이어서 상기 패터닝된 3차 포토레지스트를 식각 마스크로 하여 다단계 플라즈마 식각하여 듀얼 다마신 패턴을 형성한다. 이 때 상기 절연막은 유전율이 낮은 FSG계 절연막이 바람직하다.First, FIGS. 2A and 2B are steps of insulating film deposition, photolithography, photoresist embedding, and dual damascene formation on a substrate 201 on which a predetermined element such as a lower metal wiring is formed. As shown in the figure, a second photoresist 205 is buried in a pattern formed after etching the insulating film 203 under the primary photoresist 204 by the RIE method, and a third photoresist ( 206) is applied and patterned. Subsequently, multi-step plasma etching is performed using the patterned tertiary photoresist as an etch mask to form a dual damascene pattern. In this case, the insulating film is preferably an FSG insulating film having a low dielectric constant.

또한, 상기 다단계 플라즈마 식각은 다음과 같은 방식으로 진행하는 것이 바람직하다. 우선 트렌치 형성을 위하여 CF4 플라즈마를 이용하여 트렌치 식각하고, 식각시 발생하는 잔류 폴리머 및 포토레지스트를 CF4/O2 플라즈마로 제거한다. 이어서, 구리 표면 상의 질화막(202)을 CF4 플라즈마로 제거하고, 이 때 잔류하는 불소(Fluorine)는 H2/N2 플라즈마로 제거하면서 구리가 산화되는 것을 방지하기 위한 N 2 표면보호층(Passivation Layer)(207)을 형성시킨다. 각 단계 변경시 플라즈마 홀딩(Holding) 기능을 사용하여 식각 공정 중에 플라즈마 오프(Off)없이 다단계로 레서피(Recipe)가 구성되는 것이 바람직하다. In addition, the multi-step plasma etching is preferably performed in the following manner. First, the trench is etched using CF 4 plasma to form trenches, and residual polymer and photoresist generated during etching are removed by CF 4 / O 2 plasma. Subsequently, the nitride film 202 on the copper surface is removed by CF 4 plasma, and the remaining fluorine is removed by H 2 / N 2 plasma while the N 2 surface protection layer (Passivation) is prevented from oxidizing copper. Layer 207 is formed. It is preferable that a recipe is configured in multiple steps without plasma off during the etching process by using a plasma holding function at each step change.

다음, 도 2c는 다단계 플라즈마 식각 공정으로 듀얼 다마신 패턴을 형성한 후 이어지는 후속 단계이다. 도에서 보는 바와 같이 다단계 플라즈마 식각 공정 이후 듀얼 마디신 패턴 세정, 배리어 금속막 증착(210) 및 구리(212) 매립 순으로 진행된다. Next, FIG. 2C is a subsequent step following the formation of a dual damascene pattern by a multi-step plasma etching process. As shown in the figure, after the multi-step plasma etching process, the dual nodein pattern cleaning, the barrier metal film deposition 210, and the copper 212 are buried in the order.

본 발명은 이상에서 살펴본 바와 같이 바람직한 실시 예를 들어 도시하고 설명하였으나, 상기한 실시 예에 한정되지 아니하며 본 발명의 정신을 벗어나지 않는 범위 내에서 당해 발명이 속하는 기술분야에서 통상의 지식을 가진 자에 의해 다양 한 변경과 수정이 가능할 것이다.Although the present invention has been shown and described with reference to preferred embodiments as described above, it is not limited to the above-described embodiments and those skilled in the art without departing from the spirit of the present invention. Various changes and modifications will be possible.

따라서, 본 발명의 반도체 소자의 구리 배선 형성 방법은 전체 공정 수를 줄이고, 구리 표면을 깨끗하게 유지하므로써 반도체 소자의 수율을 향상시킬 수 있는 효과가 있다. Therefore, the copper wiring formation method of the semiconductor element of this invention has the effect which can improve the yield of a semiconductor element by reducing the whole process number and keeping a copper surface clean.

Claims (6)

구리 배선을 형성하기 위한 듀얼 다마신 공정에 있어서,In the dual damascene process for forming copper wiring, 구리 배선 상에 형성된 소정 패턴의 1차 포토레지스트 하부에 존재하는 절연막을 RIE 방법으로 식각하는 단계;Etching the insulating film under the primary photoresist of the predetermined pattern formed on the copper wiring by the RIE method; 상기 식각된 부위에 2차 포토레지스트를 채우는 단계;Filling a secondary photoresist on the etched portion; 상기 절연막 상부에 3차 포토레지스트를 도포하고 패터닝하는 단계;Applying and patterning a tertiary photoresist on the insulating layer; 상기 3차 패터닝된 포토레지스트를 식각 마스크로 하여 제1 플라즈마를 이용하여 상기 절연막 및 상기 2차 포토레지스트를 함께 트렌치 식각, 상기 트렌치 식각시 발생된 잔류 폴리머 및 포토레지스트를 제2 플라즈마로 제거, 상기 구리배선상에 형성된 질화막을 제3 플라즈마로 제거, 상기 질화막 후 잔류 불소를 제4 플라즈마로 제거하는 다단계 플라즈마 식각에 의하여 듀얼 다마신 패턴을 형성하는 단계;Using the third patterned photoresist as an etching mask, the insulating film and the second photoresist are trench-etched together using a first plasma, and residual polymer and photoresist generated during the trench etching are removed by a second plasma. Forming a dual damascene pattern by multi-step plasma etching to remove the nitride film formed on the copper wiring with a third plasma and to remove residual fluorine after the nitride film with a fourth plasma; 상기 듀얼 다마신 패턴의 표면을 세정하는 단계;Cleaning the surface of the dual damascene pattern; 상기 듀얼 다마신 패턴에 배리어 금속막을 증착하는 단계; 및Depositing a barrier metal film on the dual damascene pattern; And 상기 배리어 금속막이 증착된 패턴에 구리를 매립하는 단계Embedding copper in the pattern on which the barrier metal film is deposited; 로 이루어진 것을 특징으로 하는 반도체 소자의 구리 배선 형성 방법.Copper wiring forming method of a semiconductor device, characterized in that consisting of. 제 1 항에 있어서, The method of claim 1, 상기 절연막은 FSG막인 것을 특징으로 하는 반도체 소자의 구리 배선 형성 방법.And the insulating film is an FSG film. 제 1 항에 있어서,The method of claim 1, 상기 제1 플라즈마는 CF4 플라즈마이고, 상기 제2 플라즈마는 CF4/O2 플라즈마이고, 상기 제3 플라즈마는 CF4 플라즈마이고, 상기 제4 플라즈마는 H2/N2 플라즈마인 것을 특징으로 하는 반도체 소자의 구리 배선 형성 방법.The first plasma is a CF 4 plasma, the second plasma is a CF 4 / O 2 plasma, the third plasma is a CF 4 plasma, and the fourth plasma is an H 2 / N 2 plasma. Method for forming copper wiring of the device. 제 3 항에 있어서, The method of claim 3, wherein 상기 잔류 불소를 제거하는 동시에 구리가 산화되는 것을 방지하기 위한 N2 표면보호층(Passivation Layer)을 형성하는 것을 특징으로 하는 반도체 소자의 구리 배선 형성 방법. Forming a N 2 passivation layer for removing the residual fluorine and preventing copper from being oxidized. 제 1 항에 있어서,The method of claim 1, 상기 다단계 플라즈마 식각은 하나의 챔버에서 플라즈마 오프(Off)없이 다단계로 레서피(Recipe)가 구성되는 것을 특징으로 하는 반도체 소자의 구리 배선 형성 방법.The multi-step plasma etching method of forming a copper wiring of a semiconductor device, characterized in that the recipe (Recipe) is configured in a multi-step without plasma off (Off) in one chamber. 제 1 항에 있어서,The method of claim 1, 상기 다단계 플라즈마 식각은 각 단계 변경시 플라즈마 홀딩(Holding) 기능을 사용하여 식각 공정 중에 플라즈마 오프가 발생하지 않는 것을 특징으로 반도체 소자의 구리 배선 형성 방법.The multi-step plasma etching method of forming a copper wiring of a semiconductor device, characterized in that plasma off does not occur during the etching process by using a plasma holding (Holding) function at each step change.
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