KR100604796B1 - Dithering circuit for displaying gray level in passive display device - Google Patents

Abstract

Disclosed is a dithering circuit for implementing gray levels in a passive display device. The dithering circuit for implementing a gray level in a passive display device according to the present invention includes a frame counter including a plurality of modulo frame counters and incrementing each frame counting value in response to an externally applied frame control signal; A first counter comprising a plurality of modulo line counters, a line counter that loads a frame counting value in response to an externally applied line control signal to increase each line counting value, and a plurality of pattern position registers. A dither pattern generator having an M dither pattern register and generating dither pattern data corresponding to on / off duty ratios of different pixels in the dither pattern register; and dither pattern data in response to a line counting value output from a line counter. Pattern line to generate a pattern selection signal for selection And a video data generator for generating a predetermined bit of video data in response to the respective dithering pattern data and the pre-dithered data selected by the tack and the pattern selection signal, and dithering so that adjacent pixels are not turned on at the same time as much as possible. There is an effect that the flicker phenomenon can be prevented from occurring.

Description

Dithering circuit for displaying gray level in passive display device

1 is a block diagram illustrating a dithering circuit according to a preferred embodiment of the present invention.

FIG. 2 is a diagram schematically illustrating a dither pattern generator of the circuit illustrated in FIG. 1.

3A to 3G are waveform diagrams illustrating a process of generating a pattern selection signal of the circuit shown in FIG. 1.

4 is a diagram illustrating a process of selecting dithering pattern data from the pattern selection signal generated by the process of FIG. 3.

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to gray level implementation of a passive display device, and more particularly, to a dithering circuit for implementing gray level in a passive display device.

In general, an LCD controller driving a passive display device such as a super twisted nematic (STN) liquid crystal device (hereinafter, referred to as an LCD) may display only by turning on / off pixels. Therefore, a frame rate control (hereinafter referred to as FRC) is used to express gray levels in the passive display device. FRC refers to a method of controlling the number of times a pixel is turned on in a frame of a screen. That is, one pixel in one frame that can be represented on the LCD panel can be represented by a second plane of x and y. Here, x denotes the number of horizontal lines and y denotes the number of vertical lines. At this time, if the variable of the time axis indicating the number of frames is set to z, the coordinate value of the position of the pixel at one point may be expressed in three dimensions of x, y, and z. Also, the duty ratio DUTY RATE is defined as a value obtained by fixing x and y to a constant value, and dividing the number of times pixels are turned on by repeating a predetermined frame at that position by the predetermined frame number. For example, assuming that the duty ratio of any gray level is 1/2 at the position (1,1) of the LCD frame, it indicates that the pixel is turned on for one frame out of two frames at the position of (1,1). Therefore, in order to express gray levels in the passive display device, a duty ratio is set for each gray level, and pixels are turned on / off according to the set duty ratio. The method of turning on / off a pixel by such a method is called an FRC driving method. However, if the LCD is driven only by such an FRC method, adjacent pixels may be simultaneously turned on / off. As such, when adjacent pixels are turned on or off, visual flicker may occur. This is called a flicker. Therefore, a dithering method is used to eliminate such flicker. Dithering refers to a method of controlling a pixel to have an on / off value that is not the same depending on a position where a pixel is implemented, that is, a position of a frame, a vertical line, or a horizontal line, even when the same gray level is generated in adjacent pixels.

However, there is a problem in that flicker occurs in LCD driving that does not perform conventional dithering.

The technical problem to be achieved by the present invention is to implement a gray level in a passive display device that can completely eliminate the flicker phenomenon caused by adjacent pixels by performing three-dimensional dithering of the LCD frame, vertical line and horizontal line. It is to provide a dithering circuit for.

In order to achieve the above object, a dithering circuit for implementing a gray level in a passive display device according to the present invention includes a plurality of modulo frame counters, and each frame counting value in response to an externally applied frame control signal. A frame counter including an incrementing frame counter, a plurality of modulo line counters, a line counter that loads a frame counting value in response to an externally applied line control signal, and increases each line counting value with a plurality of pattern position registers. A dithering pattern generator including first to Mth dithering pattern registers to generate dithering pattern data corresponding to on / off duty ratios of different pixels in the dithering pattern register, and a line counting value output from a line counter. Pattern line for selecting dither pattern data in response Selected pattern to generate a signal of each unit and selected by the pattern selection signal dithering pattern data with pre-di-hindered response to the data is preferably composed of a generated video data to generate video data of a predetermined bit.

Hereinafter, a dithering circuit for implementing a gray level in a passive display device according to the present invention will be described with reference to the accompanying drawings.

1 is a block diagram of an embodiment for describing a dithering circuit for implementing a gray level according to the present invention. Referring to FIG. 1, the dither circuit includes a video data generator 100, a dither pattern generator 120, a frame counter 140, a line counter 160, and a pattern selector 180.

The frame counter 140 counts a frame of the LCD screen and outputs the counted result as a frame counting value MODF. In the embodiment of FIG. 1, frame counter 140 includes four Modulo-7, 5, 4, 3 frame counters 140a, 140b, 140c, 140d. Each modulo frame counter is represented by a MOD7F, MOD5F, MOD4F, or MOD3F counter. Here, each of the modulo frame counters MOD7F to MOD3F 140a to 140d receives the frame counting values MOD3F, MOD4F, MOD5F, and MOD7F in four modulo counting values in response to the frame control signal VFRAME. Increase. For example, each modulo frame counter may be implemented such that a counting value is increased at the rising edge of the frame control signal VFRAME. The MODF of FIG. 1 refers to four modulo counter values of MOD7F, MOD5F, MOD4F, and MOD3F.

The line counter 160 counts the number of lines in the vertical direction in response to the frame counting value MODF, and outputs the counted result as the line counting value MODL. Here, the vertical line counter 160 includes four MODULO line counters, i.e., modulo-7,5,4,3 line counters 160a, 160b, 160c, 160d. Modulo line counters are displayed as MOD7L, MOD5L, MOD4L, and MOD3L counters, respectively. Here, each of the modulo line counters MOD7L to MOD3L 160a to 160d increases the line counting value MODL in response to the line control signal VLINE. The line counting value MODL of FIG. 1 refers to four modulo counter values of MOD7L, MOD5L, MOD4L, and MOD3L. In addition, each of the modulo line counters 160a to 160d loads the value MODF counted from the modulo frame counters 140a to 140d at the rising edge of the previous line control signal and the falling edge of the current line control signal. Increase the line counting value. Accordingly, the line counting value MODL may be expressed in a form added with the frame counting value MODF, for example, xF + yL. Here, x represents a line value in the horizontal direction, and y represents a line value in the vertical direction. F denotes shift values of the modulo frame counters 140a to 140d, and L denotes shift values of the modulo line counters 160a to 160d.

The dither pattern generator 120 generates various dither pattern data to implement different duty ratios in which pixels are turned on and off. To this end, the dither pattern generator 120 includes A to D pattern position registers 120a to 120d. Here, the pattern A registers 120a to 120d are each implemented as four register blocks to process data in units of four bits. In addition, the dithering pattern generator 120 generates eight registers that may represent different duty using the pattern A to pattern D registers 120a to 120d. The dither pattern generator 120 will be described in detail with reference to FIG. 2.

The pattern selector 180 selects the pattern data of the duty ratio corresponding to the duty ratio from the dither pattern generator 120 in response to the line counting value MODL output from the line counter 160. Create The pattern selection signal MODPtr may be expressed in the form of xF + yL, and is loaded at the rising edge of the modulo line counting value MODL. The pattern selection signal MODPtr refers to four modulo counter values of MOD7Ptr, MOD5Ptr, MOD4Ptr, and MOD3Ptr, respectively.

The video data generation unit 100 includes first to fourth video data generation units 100a to 100d. Each video data generator 100a to 100d combines 8-bit data output from the pattern registers 120a to 120d of the dither pattern generator 120 to generate a predetermined bit, for example, 16-bit data. One bit of the 16 bits is output as video data (VD [0] to VD [3]) in response to externally applied pre-dithered (PRE_DITHERED) data (PRE_DIT). The first video data generator 100a includes an inverter 102a and a multiplexer 104a. Although not shown in detail, the second to fourth video data generation units 100b to 100d also include one inverter and one multiplexer.

The dithering circuit of the present invention having such a configuration generates dithering pattern data of different duty in order to perform dithering in three dimensions by using FRC driving.

FIG. 2 is a schematic diagram for describing the dither pattern generator 120 of FIG. 1, and 22 to 28 illustrate eight dither pattern registers having different duty ratios. That is, the dithering pattern register DP2_3 21 may be referred to as a register for indicating a duty ratio of 2/3, and is implemented with 12 bits. Here, 12 bits is a value obtained by multiplying 3, which is a duty of 2/3, with 4 bits of the pattern A to D registers 120a to 120d. That is, the pattern register DP2_3 21 outputs data of the corresponding bit in response to the pattern selection signal MOD3Ptr generated by the pattern selection unit 180.

In addition, the dithering pattern register DP3_4 22 may be referred to as a register representing a duty ratio of 3/4, and is implemented with 4 * 4 = 16 bits. Similarly, the pattern register (DP2_4) 23 is a register for indicating a duty ratio of 2/4, that is, 1/2, and is implemented with 16 bits. In addition, the dithering pattern register DP3_5 24 may be referred to as a register for indicating a duty ratio of 3/5, and is implemented with 5 * 4 = 20 bits. The dithering pattern registers DP4_5 25 are registers for indicating a duty ratio of 4/5, and are implemented with 20 bits. In addition, the dither pattern registers DP6_7 26 are registers for indicating a duty ratio of 6/7, and are implemented with 7 * 4 = 28 bits. The dithering pattern register DP5_7 27 represents a duty ratio of 5/7 and is implemented with 28 bits. In this manner, the dither pattern registers DP4_7 28 are registers for indicating a duty ratio of 4/7, and are implemented with 28 bits. Therefore, the eight dither pattern registers 21 to 28 implemented by the patterns A to D registers 120a to 120d respectively output 4 bits of data in response to the pattern selection signal MODPtr. In other words, referring to the pattern A register 120a, four bits of data are simultaneously output from each of the eight dithering pattern registers 21 to 28, and one of the four bits corresponds to the A register 120a. Becomes a value. As a result, the pattern A registers 120a to 120d respectively generate an output signal of 8 bits. At this time, the output 8-bit data is applied to the video data generation unit 100 and used to generate the first to fourth video data (VD [0] to VD [3]).

Subsequently, a pattern selection signal generation process performed by the frame counter 140, the line counter 160, and the pattern selector 180 will be described in detail with reference to FIG. 1.

3 (a) to 3 (g) are waveform diagrams illustrating a process for generating a pattern selection signal MODPtr of the apparatus in FIG. 1, and FIG. 3 (a) shows a frame control signal VFRAME applied from the outside. ), 3 (b) shows a line control signal VLINE, FIG. 3 (c) shows a frame modulo counting value MODF, and 3 (d) shows a line modulo counting value MODL. . 3 (e) shows an expanded state of the line control signal VLINE of FIG. 3 (b), FIG. 3 (f) shows a shift clock signal VCLK, and FIG. 3 (g) shows a pattern selection. Represents the signal MODPtr.

As described above, the modulo frame counter 140 increases the counting value of each of the internal MOD7F to MOD3F counters 140a to 140d in response to the frame control signal VFRAME of FIG. 3A. That is, each time the frame control signal VFRAME is applied, the counting value MODF of the modulo frame counters is increased. Referring to FIG. 3C, the frame counting value MODF is increased from 1F to 2F at the rising edge of the frame control signal VFRAME. In addition, the modulo line counters 160a to 160d have a line counting value MODL as shown in FIG. 3D whenever the vertical line control signal VLINE shown in FIG. 3B is applied from the outside. Is increased. At this time, when the vertical line control signal VLINE illustrated in FIG. 3E is enabled, the shift clock signal VCLK is generated to turn pixels on and off in the horizontal direction of the LCD panel. In addition, when the line counting value MODL changes from 1F + 1L to 1F + 2L, the pattern selection signal MODPtr of FIG. 3G becomes 1F + 1L. That is, the pattern selection signal MODPtr is also loaded at the rising edge of the line control signal VLINE.

Also, in the pattern selection signal MODPtr = xF + yL generated by the pattern selection unit 180, x is increased by 1 every 4 pixels shifted in the horizontal direction because the processing unit of video data is 4 bits. . Also, y is increased every time it is shifted in the vertical direction. The F and L values are set to appropriate values per modulo counter so that adjacent pixels in the frame, vertical line and horizontal line are not turned on at the same time. For example, the F value of the MOD7F counter 140a is set to three, and the F value of the MOD5F counter 140b is set to two. In addition, the F values of the MOD4F counter 140c and the MOD3F counter 140d are set to 1, and the L modifiers of the line modulo counters MOD7L to MOD3L 160a to 160d are all set to 1. Table 1 below shows the shift values of the respective modulo counters.

     Modulo counter   Shift value MOD7F 3 MOD7L One MOD5F 2 MOD5L One MOD4F One MOD4L One MOD3F One MOD3L One

Among the pattern selection signals, MOD7PTr is a pattern selection signal that can be generated by modulo 7F and 7L counters 140a and 160a, and a dithering pattern having a duty ratio of p / 7 (p = 6,5,4). It is used to generate pattern data of the registers 26, 27, 28 (see Fig. 2). Here, p represents the number of 1s among the seven register values. For example, when the pattern selection signal MOD7Ptr is 1F + 1L, F is 3 and L is 1, so this value is 4. In addition, MOD5Ptr becomes a pattern selection signal that can be generated by modulo 5F and 5L counters 140b and 160b, and is used to generate pattern data having a duty ratio q / 5 (q = 3,4). MOD4Ptr becomes a pattern selection signal that can be generated by modulo 4F and 4L counters 140c and 160c and is used to generate pattern data with a duty ratio of r / 4 (r = 3,2). MOD3Ptr becomes a pattern selection signal that can be generated by modulo 3F and 3L counters 140d and 160d and is used to generate pattern data with a duty ratio of 2/3.

Subsequently, the video data generation process performed by the dithering pattern generator 120 and the video data generator 100 will be described in detail. In the present invention, the duty cycle for gray level implementation is 1, 6/7, 4/5, 3/4, 5/7, 2/3, 3/5, 4/7, 1/2, 3/7, 2 16 of / 5, 1/3, 1/4, 1/5, 1/7 and 0. Next, Table 2 lists the duty ratios corresponding to each of the sixteen gray levels, and the corresponding percentages. The gray level here is each level of pre-dithered data PRE_DIT applied from the outside.

Pre-Dithered Data Duty ratio Duty ratio (%) 15 One 100 14 6/7 85.7 13 4/5 80 12 3/4 75 11 5/7 71.4 10 2/3 66.7 9 3/5 60 8 4/7 57.1 7 2/4 50 6 3/7 42.9 5 2/5 40 4 1/3 33.3 3 1/4 25 2 1/5 20 One 1/7 14.3 0 0 0

 In order to implement such a duty cycle, it can be seen that the dithering pattern registers 21 to 28 (see Fig. 2) have eight DP2_3, DP3_4, DP2_4, DP3_5, DP4_5, DP6_7, DP5_7, and DP4_7 used as described above. have.

First, the dither pattern data generated in each of the dither pattern registers 21 to 28 (see FIG. 2) of the dither pattern generator 120 of FIG. 1 will be described in detail. First, each pattern data generated in the dither pattern registers of FIG. 2 is shown in Table 3.

Duty ratio Number of bits Pattern data DP2_4 16 1010 0101 1010 0101 DP4_7 28 1011 1100 0111 1001 0100 1011 1100 0011 0110 DP3_5 20 0101 1010 1101 0111 1010 DP2_3 12 1011 0101 1110 DP5_7 28 1110 1111 0111 1101 1110 1011 1101 0111 1011 DP3_4 16 1101 0111 1110 1011 DP4_5 20 0111 1111 1011 1110 1101 DP6_7 29 1111 1101 1111 1110 1111 1111 1011 1111 0111

As described above, the pattern registers DP2_4 and 23 of the dither pattern generation unit 120 are 16-bit patterns obtained by multiplying 4 corresponding to the denominator of duty 2/4 by the respective A to D register values representing the data processing unit. Appears. Similarly, the pattern register DP4_7 of the data pattern generator 120 is implemented as 28 bits of pattern data multiplied by 7 corresponding to the denominator and 4 bits of the data processing unit. The same applies to other duty ratios. For example, a bit pattern with a denominator of duty ratio of 7 may indicate each bit position as DPk_7 [4n + m]. Here, n represents 0, 1, 2, 3, ... 6, m represents 0, 1, 2, 3, and k becomes 3, 4, 5, 6. For example, when m is 0, the value of the pattern A register 120a is represented. When m is 1, the value of the pattern B register 120b is represented. When m is 2, the value of the pattern C register 120c is represented. A value is shown, and when m is 3, the value of the pattern D register 120d is shown. In addition, four bits of DPk_7 [4n + 0], DPk_7 [4n + 1], DPk_7 [4n + 2], and DPk_7 [4n + 3] are simultaneously generated in units of one clock of VCLK.

4 shows each bit pattern for the pattern register DPk_7. Referring to FIG. 4, the pattern selection signal MOD7Ptr for selecting the dithering pattern data to be used for the second line of the second frame becomes four. Therefore, bits BT12 to BT15 corresponding to 4 in MOD7PTr of FIG. 4 are selected. Here, BT [12] represents DPk_7 [12]. In addition, the bits BT13 to BT15 represent bits of the pattern B register to the pattern D register respectively corresponding to the same line. As a result, it can be seen that BT12 to BT15 are selected by the pattern selection signal MOD7Ptr and simultaneously generated by the shift clock signal VCLK.

As such, in order to implement the duty ratio, the pattern A to pattern D register values may be represented as shown in Table 4 below. That is, Table 4 shows specific bit positions of the pattern positions A to D registers based on the data patterns shown in Table 3.

For example, in the case of the dithering pattern register (DP2_4) 23 whose duty ratio in Table 4 is 2/4, the number of bits of the pattern data is 16 bits, and each bit position DP2_4 [of the pattern A register 120a is used. 0]), the bit position DP2_4 [4] of the pattern B register 120b, the bit position DP2_4 [8] of the pattern C register 120c, and the bit position DP2_4 [12] of the pattern D register 120d. ) Occurs at the same time. In addition, in the case of the duty ratio p / 7 register DPp_7, the pattern data is 28 bits, as shown in Table 5, and in the case of the dithering pattern register DPq_5 having the duty ratio q / 5, the pattern data is 20 bits. For the r / 3 register, the pattern data is 12 bits. At this time, 8-bit data is simultaneously output from each of the pattern positions A through D registers 120a through 120d.

Duty ratio Pattern position Bit position DP2_4 A DP2_4 [0], DP2_4 [4], DP2_4 [8], DP2_4 [12] B DP2_4 [1], DP2_4 [5], DP2_4 [9], DP2_4 [13] C DP2_4 [2], DP2_4 [6], DP2_4 [10], DP2_4 [14] D DP2_4 [3], DP2_4 [7], DP2_4 [11], DP2_4 [15] DP4_7 A DP4_7 [0], DP4_7 [4], DP4_7 [8], .... DP4_7 [24] B DP4_7 [1], DP4_7 [5], DP4_7 [9], .... DP4_7 [25] C DP4_7 [2], DP4_7 [6], DP4_7 [10], .... DP4_7 [26] D DP4_7 [3], DP4_7 [7], DP4_7 [11], .... DP4_7 [27] DP3_5 A DP3_5 [0], DP3_5 [4], DP3_5 [8], DP3_5 [12], DP3_5 [16] B DP3_5 [1], DP3_5 [5], DP3_5 [9], DP3_5 [13], DP3_5 [17] C DP3_5 [2], DP3_5 [6], DP3_5 [10], DP3_5 [14], DP3_5 [18] D DP3_5 [3], DP3_5 [7], DP3_5 [11], DP3_5 [15], DP3_5 [19] DP2_3 A DP2_3 [0], DP2_3 [4], DP2_3 [8] B DP2_3 [1], DP2_3 [5], DP2_3 [9] C DP2_3 [2], DP2_3 [6], DP2_3 [10] D DP2_3 [3], DP2_3 [7], DP2_3 [11] DP5_7 A DP5_7 [0], DP5_7 [4], DP5_7 [8], .... DP5_7 [24] B DP5_7 [1], DP5_7 [5], DP5_7 [9], .... DP5_7 [25] C DP5_7 [2], DP5_7 [6], DP5_7 [10], .... DP5_7 [26] D DP5_7 [3], DP5_7 [7], DP5_7 [11], .... DP5_7 [27] DP3_4 A DP3_4 [0], DP3_4 [4], DP3_4 [8], DP3_4 [12] B DP3_4 [1], DP3_4 [5], DP3_4 [9], DP3_4 [13] C DP3_4 [2], DP3_4 [6], DP3_4 [10], DP3_4 [14] D DP3_4 [3], DP3_4 [7], DP3_4 [11], DP3_4 [15] DP4_5 A DP4_5 [0], DP4_5 [4], DP4_5 [8], DP4_5 [12], DP4_5 [16] B DP4_5 [1], DP4_5 [5], DP4_5 [9], DP4_5 [13], DP4_5 [17] C DP4_5 [2], DP4_5 [6], DP4_5 [10], DP4_5 [14], DP4_5 [18] D DP4_5 [3], DP4_5 [7], DP4_5 [11], DP4_5 [15], DP4_5 [19] DP6_7 A DP6_7 [0], DP6_7 [4], DP6_7 [8], .... DP6_7 [24] B DP6_7 [1], DP6_7 [5], DP6_7 [9], .... DP6_7 [25] C DP6_7 [2], DP6_7 [6], DP6_7 [10], .... DP6_7 [26] D DP6_7 [3], DP6_7 [7], DP6_7 [11], .... DP6_7 [27]

The dithering pattern data generated through the above process is generated as video data in the data generator 100. That is, the duty ratio other than the eight duty ratios implemented in the dithering pattern generator 120 may be implemented by inverting some bit values among the eight bits of the register. That is, when the first video data generation unit 100a of FIG. 1 is described in detail, the inverter 102a inverts 6 bits among the 8 bits of data output from the pattern A register 120a. Although not shown in detail, the same applies to the patterns B to D registers 120b to 120d. At this time, the 8-bit data generated in the pattern A register 120a becomes 7 to 14 bits among the 16 (0 to 15) bit data, and the inverted 6 bits are 1 to 6 bits. In addition, a fixed value is used for the 0 bits, i. That is, 16-bit data is applied as input data of the multiplexer 104a. Therefore, the multiplexer 104a selectively selects one of the input 16-bit data as the first video data VD [0] in response to the pre-dithered data PRE_DIT stored in an external memory (not shown). Output At this time, the multiplexer 104a is preferably implemented as a 16x1 multiplexer. Here, PRE_DIT is data for representing 16 gray levels, which is composed of all 16 bits, and each of the 16 gray levels is represented by 16 bits. At this time, 4 pixels can be represented by 16 bits of PRE_DIT. That is, the 4-bit data PRE_DIT applied to the multiplexer 104a as the selection signal SEL becomes 4 bits [3: 0] of the 16-bit data for one level, and 1 pixel can be represented by 4 bits. have. Specifically, PRE_DIT applied to the multiplexer 104a becomes PRE_DIT [3: 0] among 16 bits, and VD [0] is generated by PRE_DIT [3: 0]. Similarly, in the second video data generating unit 100b, VD [1] is generated by PRE_DIT [7: 4] as the selection signal. Also, the VD [2] is generated by PRE_DIT [11: 8] in the third video data generating unit 100c, and the VD [3] by PRE_DIT [16:12] in the fourth video data generating unit 100d. Is generated. At this time, when VD [3: 0] is represented by the coordinate values (x, y) of the LCD panel, VD [0] is used to represent the pixel at the position (4x + 0, y), and VD [1]. Is used to represent pixels of (4x + 1, y). Also, VD [2] is used to represent pixels of (4x + 2, y), and VD [3] is used to represent pixels of (4x + 3, y). The video data VD [3: 0] generated through the above process is applied to the LCD driver (not shown) and latched, and displayed on the LCD panel by the latched result.

According to the present invention, by performing dithering so that adjacent pixels are not turned on at the same time, the flicker phenomenon can be prevented from occurring and the gray level can be effectively expressed on the STN LCD which is a passive display device through dithering.

Claims (8)

A frame counter including a plurality of modulo frame counters, the frame counter incrementing each frame counting value in response to an externally applied frame control signal; A line counter including a plurality of modulo line counters and loading the frame counting value in response to an externally applied line control signal to increase each line counting value; A dithering pattern having a first to M-th (> 1) dithering pattern register implemented by a plurality of pattern position registers and generating dithering pattern data corresponding to on / off duty ratios of different pixels in the dithering pattern register Generator; A pattern selector configured to generate a pattern select signal for selecting the dither pattern data in response to a line counting value output from the line counter; And And a video data generator for generating a predetermined bit of video data in response to respective dithering pattern data and pre-dithered data selected by the pattern selection signal. The method of claim 1, wherein the frame counter and the line counter, A dithering circuit characterized by being modulo-7, modulo-5, modulo-4 and modulo-3 counters. The method of claim 1, wherein the dither pattern generator, Implement first through eighth dither pattern registers for representing eight duty ratios by the plurality of pattern position registers; And the eight dither pattern registers each represent a duty of 6/7, 4/5, 3/4, 5/7, 2/3, 3/5, 4/7, and 2/4. The method of claim 1, wherein the pattern selector, Representing the pattern selection signal by xF + yL value, Here, x represents a line value in the horizontal direction, F represents a shift value of the modulo frame counter, y represents a line value in the vertical direction, and L represents a shift value of the modulo line counter. Dithering circuit, characterized in that. The method of claim 4, wherein the pattern selector, The modulo-7 frame counter has F set to 3, and the modulo-5 frame counter has F set to 2, And the F of the modulo-4 and modulo-3 frame counters is set to one. The method of claim 4, wherein the pattern selector, And the modulo-7, modulo-5, modulo-4, and modulo three-line counters, wherein L is set to all ones. The video data generator of claim 1, wherein the video data generator comprises: Each of the first to fourth video data generating unit, The first to fourth video data generation units, 16-bit data is generated by a K (> 1) bit output respectively output from the plurality of pattern position registers and a bit output inverting L (here, 1 <L <K) bits among the K bit outputs. And selectively outputting one of the 16-bit data in response to the pre-dithered data. The method of claim 1, wherein the dither pattern generator, A dithering circuit comprising four pattern position registers to process data in units of four bits.

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