KR100602351B1 - Method and apparatus for controlling video memory and display device using the same - Google Patents

Abstract

The present invention provides a memory control apparatus and method capable of reducing the number of gates required for arithmetic logic and efficiently processing image data by storing and using a start address of each image data stored in a memory in a lookup table, and a display apparatus using the same. It is about. The display device according to the present invention includes a memory for storing a plurality of input image data, a data driver for supplying a data signal corresponding to the image data, a scan driver for supplying a scan signal, and an image corresponding to the data signal according to the scan signal. An image display unit to display, and a control unit for controlling the memory, data driver and scan driver. Here, the control unit controls the image data input and output to the memory by using the address storage unit in which the start addresses for the plurality of image data are stored in advance.

Display, memory, start address, arithmetic logic, lookup table

Description

Memory control apparatus and method and display device using same {Method and apparatus for controlling video memory and display device using the same}             

1 is a block diagram illustrating a display device according to an exemplary embodiment of the present invention.

2 is a diagram illustrating image data stored in a memory of a display device according to an exemplary embodiment of the present invention.

3 is a diagram illustrating a start address stored in a lookup table of a display device according to an exemplary embodiment of the present invention.

4 is a circuit diagram illustrating a pixel that may be employed in a display device according to an exemplary embodiment of the present invention.

Explanation of symbols on the main parts of the drawings

300: display device 310: memory

320: display module 322: scan driver

324: data driver 326: image display unit

328: pixel 330: control unit

332: timing controller 334: lookup table

The present invention relates to a memory control apparatus and method for reducing the number of gates required for arithmetic logic by storing and using start addresses for a plurality of image data stored in a memory in a lookup table, and a display device using the same.

In general, image data is made in units of pixels and displayed on a screen in units of pixels. Such image data is encoded in predetermined frame units for efficient transmission and storage of the data. At this time, the image compression technique is used for encoding each image data due to its huge amount of information. In general, compression of image data is performed in such a manner that redundant data between respective images is removed or encoded in a predetermined form in a space and time domain.

The most widely known image compression technique described above is the MPEG (moving picture expert group, MPEG) standard. The MPEG standard encodes macroblock units when creating image data of one frame, and decodes macroblock units for storage and display. For example, the macro block is composed of 16 scan lines. In addition, the MPEG standards described above include images such as digital television (DTV), high definition television (HDTV), satellite broadcasting service (DBS), and digital video disk (DVD). Adopted for high picture quality in systems.

For example, in the NTSC (national television system committee) system, one frame of image data is composed of 480 scan lines, and each scan line is composed of 720 pixels. In the NTSC system, a moving picture is realized using about 30 frames of data per second.

In the case of a PAL method (phase alteration by line system), image data of one frame is composed of 576 scan lines, and each scan line is composed of 720 pixels similarly to the NTSC method. In the PAL method, a moving image is implemented using about 25 frames of data per second.

Also, the image data is stored in a memory such as a video memory before being displayed on the screen of the display device. For example, in a conventional display device, an encoder (not shown) sequentially decodes image data encoded and input according to a control signal of a controller (not shown), and image data output from the decoder according to another control signal of the controller. It is stored in frame by frame in memory. At this time, the start address of each image data stored in the predetermined storage space in the memory is generated by the operation of the controller. For this purpose, the controller includes arithmetic logic.

Also, image data stored in the memory usually has a constant size. However, the image data stored in the memory is not stored in accordance with the capacity of the memory. For example, image data is not stored in memory manufactured in multiples of two, such as 1 mega, 2 mega, 4 mega, 8 mega bit, or the like to match the memory capacity, such as 1.8 mega, 2.6 mega, or the like.

Therefore, most conventional display apparatuses further integrate an expensive central processing unit (CPU) or such a central processing unit in order to obtain each start address of a large amount of image data sequentially stored in a memory through calculation. And a high speed computing device such as a micro processing unit (MPU).

In the display device equipped with the above-mentioned conventional high speed arithmetic device, a prototype is easily manufactured using a field programmable gate array (FPGA) that is easy to change design and is suitable for processing a large amount of image data in order to manufacture its driving circuit or control circuit. After designing the integrated circuit for the fabrication of the fabrication, the method is manufactured in the form of a chip such as an application specific intergrated circuit (ASIC) with the designed electronic circuit. FPGA is a form of programmable logic chip that supports thousands of many gates.

However, designing a drive circuit or control circuit of a conventional display device is difficult and complicated because an operation routine must be designed so that an FPGA having thousands of gates can calculate a start address of a plurality of image data. In other words, the FPGA for the integrated circuit design of the control unit of the conventional display device requires a large number of gates to form an operation routine for obtaining each start address of a large amount of image data. Therefore, in the conventional display device, it is difficult and complicated to design an integrated circuit for the controller using an FPGA. In addition, the control unit of the display device designed in this manner includes a large number of gates in order to form an operation routine for obtaining the start address of the image data stored in the memory similarly to its design method. Therefore, it is difficult to drive the memory efficiently.

SUMMARY OF THE INVENTION The present invention has been made in view of the above-described conventional problems, and an object of the present invention is to reduce the number of gates of arithmetic logic for controlling a memory of a display device, thereby facilitating an integrated circuit design for a controller. And a method.

Another object of the present invention is to provide a display device capable of efficiently controlling image data input and output to and from a memory using the above-described memory control device and method.

In order to achieve the above object, according to an aspect of the present invention, a memory for storing a plurality of input image data, a data driver for supplying a data signal corresponding to the image data, a scan driver for supplying a scan signal and And a control unit controlling a memory, a data driver, and a scan driver to display an image corresponding to a data signal according to a scan signal, wherein the controller stores an address in which start addresses for a plurality of image data are stored in advance. A display device for controlling image data input / output into a memory by using a unit is provided.

Preferably, the controller comprises a timing controller for providing a start address to the memory. The image display section also includes a plurality of scan lines for transmitting a scan signal, a plurality of data lines for transmitting a data signal, and a plurality of pixels connected to the plurality of scan lines and a plurality of data lines, respectively. In addition, the pixel includes a pixel circuit that supplies a current corresponding to the data signal, and a light emitting device that emits brightness corresponding to the input current. Moreover, it is preferable that a light emitting element is an organic light emitting element which makes an organic substance a light emitting layer.

According to another aspect of the invention, in the memory control device for controlling the memory of the display device, the storage unit for storing the start address for the plurality of image data stored in the memory in advance, and the start address stored in the storage unit A memory control device is provided that includes a timing controller that controls the memory to extract and output image data corresponding to a start address from the memory.

According to still another aspect of the present invention, there is provided a memory control method for controlling a memory of a display device, the method comprising: storing start addresses of a plurality of image data stored in a memory in a separate storage unit, and starting from the storage unit; There is provided a memory control method comprising the step of obtaining an address, and controlling the memory to form a control signal in accordance with the obtained start address to output image data corresponding to the start address in the memory.

Preferably, storing the start address in a separate storage unit includes generating a lookup table by previously storing start addresses of the plurality of image data in a separate memory.

Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. In the drawings, parts irrelevant to the present invention have been omitted for clarity, and like reference numerals denote like parts throughout the specification.

1 is a block diagram illustrating a display device according to an exemplary embodiment of the present invention.

Referring to FIG. 1, in the display device 300 according to an exemplary embodiment, start addresses of a plurality of image data stored in the memory 310 are stored in advance in the lookup table 334 in the controller 330. The start data stored in the lookup table 334 is used to efficiently control image data input and output to the memory 310. In other words, the display device 300 according to an exemplary embodiment does not need to form an operation routine for calculating the start address of the image data in the control unit 330, and obtains the start address from the lookup table 334. By outputting the image data stored in the memory 310, it is possible to efficiently process the image data input and output to the memory. To this end, the display device 300 includes a memory 310, a display module 320, and a controller 330. In addition, the display device 300 includes a power supply unit (not shown) that supplies the first power sources VDD and 340 and the second power sources VSS and 350 to the display module 320. The power supply unit may supply predetermined power to the memory 310 and the controller 330.

In more detail, the memory 310 stores image data input to the display device 300. The memory 310 is implemented with random access memory (RAM) consisting of one or more microchips. The memory 310 also has a capacity capable of processing image data in units of frames. Here, the memory capacity for processing image data in units of frames has a memory capacity larger than that for processing image data in units of frames of 1,866,240 bytes in the case of the PAL system, for example.

In addition, the memory 310 may be implemented with a larger capacity in order to process audio data and system data together with image data when processing image data in a frame unit.

The display module 320 displays an image corresponding to the image data transferred from the memory 310. To this end, the display module 320 includes a scan driver 322, a data driver 324, and an image display unit 326. In addition, the display module 320 may further include flexible printed circuits (FPC) (not shown) electrically connected to the controller 330. Of course, the scan driver 322 and / or the data driver 324 in the display module 320 may not be included in one module and may be appropriately formed in another form.

As illustrated in FIG. 1, the scan driver 322 is connected to a plurality of scan lines S1, S2,... Sn extending in the horizontal direction in the image display unit 326, and each scan line S1, S2,. Sn is supplied with a scan signal. In this case, the scanning signal may be at least one of a single scan method, a progressive scan method, a dual scan method, an interlaced scan method, or another scanning method. It is transmitted to the image display unit 326.

The data driver 324 is connected to a plurality of data lines D1, D2, ..., Dm extending in the vertical direction in the image display unit 326, and data signals are provided to the data lines D1, D2, ..., Dm. To supply. The data signal includes a data voltage and may be implemented as a data current according to the structure of the pixel circuit.

The image display unit 326 includes a plurality of pixels 328 respectively connected to a plurality of scan lines S1, S2, ..., Sn, a plurality of data lines D1, D2, ..., Dm, and a plurality of scan lines and a plurality of data lines. ). In addition, the image display unit 326 includes a first power line and a second power line for transmitting the first power sources VDD and 340 and the second power sources VSS and 350 to each pixel 328. The second power line may be implemented as a common power line or an electrode layer commonly connected to the plurality of pixels 328.

The pixel 328 is connected to at least one scan line and at least one data line, is activated by a scan signal transmitted through the scan line, and emits a predetermined color and light in correspondence to the data signal transmitted through the data line.

The control unit 330 does not obtain the start address of the image data stored in the memory 310 through arithmetic operation, but generates a lookup table by storing the start address in advance in a separate storage unit, and uses the memory 310 as a conventional method. Compared with the memory control device to control efficiently. Here, the memory control apparatus includes a timing controller 332 and a lookup table 334.

Specifically, the timing controller 332 in the memory control device controls the memory 310 so that image data sequentially input may be stored in a predetermined storage space in the memory 310. At this time, the image data stored in the memory 310 is stored at an address determined according to the memory control signal MCS of the timing controller 332 referring to the start address stored in the lookup table 334. In addition, the timing controller 332 obtains a start address from the lookup table 334, and then stores the memory 310 through another memory control signal MCS so that image data corresponding to the obtained start address is output from the memory 310. ).

The controller 330 controls the display module 320 that receives image data from the memory 310. Specifically, the timing controller 332 in the control unit 330 scans the display module 320 so that the image data transferred from the memory 310 to the display module 320 can be properly displayed on the display module 320. The display module 320 is controlled through the scan control signal SCS for controlling the driver 332 and the data control signal DCS for controlling the data driver 334 in the display module 320.

The lookup table 334 is implemented as a separate memory, an address storage unit, or other storage unit for storing the start address of each image data stored in the memory 310. For example, the lookup table 334 may be implemented in a small memory or storage unit. In this case, the lookup table 334 may be implemented with a size of several tens of bytes in order to reduce the size of a separate memory or storage.

As described above, in the display device according to the present invention, the start address of the plurality of image data stored in the memory needs to be generated through calculation by controlling the start address of the image data stored in the memory using a small lookup table. Therefore, it is possible to process image data more efficiently with a control unit (not shown) which is smaller in size than a conventional control unit having arithmetic logic.

2 is a diagram illustrating image data stored in a memory of a display device according to an exemplary embodiment of the present invention.

Referring to FIG. 2, the memory 310 selects each image data D0, D1, D2,..., D9, DA, DB, DC, DD, DE, and DF input according to a memory control signal of a timing controller. The data is stored in the storage spaces A0, B0, C0, ..., J0, K0, L0, M0, N0, O0, P0. Here, A0 to P0 represent starting addresses of the respective storage spaces. For example, the specific image data D0 is stored in the storage space A0 in the memory 310, the other specific image data D7 is stored in another storage space H0 in the memory 310, and another The specific image data DA is stored in another storage space K0 in the memory 310.

The image data may be stored in the memory 310 in various ways such as an interlace method in which odd-numbered image data and even-numbered image data are alternately stored in different storage spaces.

3 is a diagram illustrating a start address stored in a lookup table of a display device according to an exemplary embodiment of the present invention.

Referring to FIG. 3, the display device according to the present invention stores a start address of a plurality of image data stored in a memory in an address storage unit or a separate storage unit. Here, the address storage unit or the storage unit may be implemented by the lookup table 334. In the display device according to the present invention, the lookup table 334 stores the start address of each image data to be stored in the memory 310.

Therefore, the display device according to the present invention is the start address (A0, B0, C0) of each image data D0, D1, D2, ..., D9, DA, DB, DC, DD, DE, DF stored in the lookup table. , ..., J0, K0, L0, M0, N0, O0, P0) are used to control the memory 310 so that the image data stored in the memory 310 is easily transferred to the display module.

On the other hand, the timing controller of the memory control apparatus according to the present invention stores the image data of a predetermined size into the memory at an address determined according to the start address of the lookup table 334, and starts from the lookup table 334. After the address is obtained, the memory 310 is controlled so that image data corresponding to the obtained start address is output from the memory.

As described above, the present invention stores the start address of the image data stored in the memory in a small storage unit, generates the lookup table, and controls the memory according to the start address stored in the lookup table, thereby controlling the memory very efficiently. In addition, it is possible to efficiently process image data, and further contribute to miniaturization of a memory control device or control unit and a display device equipped with the same.

4 is a circuit diagram illustrating a pixel that may be employed in a display device according to an exemplary embodiment of the present invention.

Referring to FIG. 4, the pixel 328 is activated by a scan signal transmitted through the scan line Sn, and emits a predetermined color and luminance corresponding to the data signal transmitted through the data line Dm. To this end, the pixel 328 includes an electroluminescence device EL and a pixel circuit 329 for controlling the light emitting element EL.

The light emitting device EL includes an emission layer made of an organic material or an inorganic material. In addition, the light emitting device EL may be formed in a multi-layered structure including an electron injection layer, an electron transport layer, a hole injection layer, a hole transport layer, a hole blocking layer, and the like on both sides of the light emitting layer in order to improve injection and transfer characteristics of electrons or holes. Can be.

The pixel circuit 329 may include a switching transistor for selecting the pixel 328, a driving transistor for supplying a predetermined current to the light emitting element EL, and a capacitor connected to a gate and a source of the driving transistor. have.

For example, as illustrated in FIG. 4, the pixel circuit 329 includes a first transistor M1 having a source connected to the first power line VDD, a source connected to the data line Dm, and a drain. A second transistor connected to the gate of the first transistor M1, a gate connected to the scan line Sn, a first electrode connected to a gate of the first transistor M1, and a second electrode connected to the first transistor M1. It may be implemented as a capacitor (C) connected to the source of (M1).

On the other hand, in the above-described embodiment, the pixel circuit is referred to as a basic pixel circuit of the voltage write method including the driving transistor M1 and the switching transistor M2. However, the present invention can be easily applied to a display device having a pixel write type pixel circuit including a transistor for compensating for a threshold voltage of the driving transistor or a transistor for compensating a voltage drop in addition to the switching transistor and the driving transistor. have. Furthermore, the present invention can be easily applied to a display device including not only a voltage write type pixel circuit but also a current write type pixel circuit for supplying a data signal with a data current.

Further, in the above-described embodiment, while the transistor in the pixel circuit has been described as having a source, a drain, and a gate, each transistor has a first electrode representing a source or drain, a second electrode representing a drain or source, and a gate. It can be formed to. In other words, the MOS transistor in the pixel circuit described above is mentioned as an example. Therefore, the pixel circuit of the present invention can be formed of other kinds of transistors in addition to the MOS transistors. For example, a first electrode, a second electrode, and a third electrode are provided, and the amount of current flowing from the second electrode to the third electrode can be controlled by a voltage applied between the first electrode and the second electrode. It can be implemented as an active element.

In addition, in the above-described embodiment, the switching transistor M2 of the pixel circuit is an element for switching the electrodes on both sides in response to the scan signal, and may be implemented using several switching elements capable of performing the same function. have.

Further, in the above-described embodiment, the scan driver and the data driver of the display device can be directly mounted on the substrate on which the image display is formed, and are formed of the same layers as the scan line, the data line, and the transistor on the substrate on which the image display is formed. It can be replaced by a drive circuit. On the other hand, the scan driver and / or the data driver may be formed in a chip on flexible board, or chip on film (COF) structure. In other words, the scan driver and / or the data driver may be mounted in the form of a chip or the like on a flexible printed circuit (FPC) or a film that is adhered to and electrically connected to the substrate.

As mentioned above, although preferred embodiment of this invention was described in detail, this invention is not limited to the said embodiment, A various deformation | transformation by a person of ordinary skill in the art within the scope of the technical idea of this invention is carried out. This is possible.

According to the present invention, it is possible to reduce the number of gates of the operation logic for controlling the memory of the display device to facilitate the integrated circuit design for the memory controller. In addition, by using the small-capacity storage unit in which the start address is stored, not only can the memory of the display device be efficiently driven, but also the image data input and output to the memory of the display device can be processed very efficiently. In addition, by reducing the size of the integrated circuit for controlling the memory of the display device, it is possible to contribute to the miniaturization of the control unit or the display device.

Claims (8)

A memory for storing a plurality of input image data; A data driver supplying a data signal corresponding to the image data; A scan driver supplying a scan signal; An image display unit for displaying an image corresponding to the data signal in accordance with the scan signal; And A control unit for controlling the memory, the data driver, and the scan driver, the timing controller providing the start address to the memory ; And the control unit controls the image data input and output to the memory using an address storage unit in which start addresses for the plurality of image data are stored in advance. delete The method of claim 1, The image display unit, A plurality of scan lines for transmitting the scan signals; A plurality of data lines carrying the data signals; And And a plurality of pixels connected to the plurality of scan lines and the plurality of data lines, respectively. The method of claim 3, The pixel may include a light emitting device that emits light corresponding to the data signal, and a pixel circuit that controls the light emitting device. The method of claim 4, wherein The light emitting device is an organic light emitting device having an organic material as a light emitting layer. In the memory control device for controlling the memory of the display device, A storage unit which stores in advance start addresses for a plurality of image data stored in the memory; And And a timing controller which extracts the start address stored in the storage unit and controls the memory to output the image data corresponding to the start address from the memory. In the memory control method for controlling the memory of the display device, Storing start addresses of the plurality of image data stored in the memory in a separate storage unit; Obtaining the start address from the storage; And And forming a control signal according to the obtained start address to control the memory to output the image data corresponding to the start address from the memory. The method of claim 7, wherein The storing of the start address in a separate storage unit includes generating a lookup table by storing the start addresses of the plurality of image data in advance in a separate memory.

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