KR100600869B1 - thin film transistor having LDD region and GOLDD region - Google Patents

Abstract

A thin film transistor having an LDD region and a GOLDD region is provided. The thin film transistor may include a gate electrode; And a semiconductor layer including a channel region, a high concentration impurity region, and a low concentration impurity region partially overlapping the gate electrode, wherein the low concentration impurity region includes a GOLDD region overlapping with the gate electrode and an LDD region not overlapping with the gate electrode. And the length of the LDD region is equal to or larger than the length of the GOLDD region.

Thin Film Transistors, GOLDD, LDD, Reliability

Description

A thin film transistor having an LD region and a OLED region {thin film transistor having LDD region and GOLDD region}

1A to 1D are cross-sectional views illustrating a method of manufacturing a thin film transistor according to an exemplary embodiment of the present invention.

2 is a graph showing relative charge mobility with respect to the drain voltage of each of the thin film transistors according to Experimental Examples 1 and 2 and Comparative Examples 1 and 2. FIG.

(Explanation of symbols for main parts of drawing)

110 semiconductor layer 110a low concentration impurity region

110a-1: GOLDD area 110a-2: LDD area

110b: channel region 110c: high concentration impurity region

The present invention relates to a thin film transistor, and more particularly to a thin film transistor having an LDD region and a GOLDD region.

The thin film transistor generally includes a semiconductor layer, a gate electrode, and a source / drain electrode, wherein the semiconductor layer includes source / drain regions and a channel region interposed between the source / drain regions. On the other hand, the semiconductor layer may be formed of polysilicon or amorphous silicon, but the electron mobility of the polycrystalline silicon is higher than that of amorphous silicon, and currently, polycrystalline silicon is mainly applied.

However, the polycrystalline silicon thin film transistor has a disadvantage in that the off current is larger than that of the amorphous silicon thin film transistor. In order to compensate for the disadvantages of the polycrystalline silicon thin film transistor, a structure in which a lightly doped region is formed between a source / drain region, that is, a heavily doped region and a channel region of the polycrystalline silicon thin film transistor, Lightly doped drain (LDD) structures have been proposed. However, the thin film transistor having the LDD structure is weaker than the thin film transistor having the GOLDD structure, which has the effect of preventing degradation due to hot carrier injection near the drain region, that is, the reliability characteristic described later.

On the other hand, a so-called gate overlapped lightly doped drain (GOLDD) structure in which the gate electrode is disposed to overlap the low concentration impurity region is known to have a great effect of suppressing deterioration of the thin film transistor by preventing hot carrier injection near the drain region. However, the thin film transistor having the GOLDD structure has a large disadvantage in that the off current value is larger than the thin film transistor having the LDD structure.

In order to solve this problem, Korean Patent Application No. 10-2001-0025977 discloses a semiconductor device. The semiconductor device includes a semiconductor layer formed on an insulating surface, an insulating film formed on the semiconductor layer, and a gate electrode formed on the insulating film, wherein the gate electrode is formed as a first conductive layer having a first width and an upper layer as a lower layer. A pair having a laminated structure of a second conductive layer having a second width smaller than the first width, wherein the semiconductor layer is a pair of channel forming regions overlapping the second conductive layer and partially overlapping the first conductive layer And a source region and a drain region each composed of a low concentration impurity region and a high concentration impurity region.

However, in a pair of low concentration impurity regions partially overlapping with the first conductive layer, optimization of variables determining low concentration impurity regions overlapping the first conductive layer and low concentration impurity regions not overlapping the first conductive layer Thus, no attempt is made to optimize the reliability characteristics of thin film transistors.

The technical problem to be achieved by the present invention is to solve the problems of the prior art to provide a thin film transistor having an optimized reliability characteristics.

In order to achieve the above technical problem, the present invention provides a thin film transistor. The thin film transistor may include a gate electrode; And a semiconductor layer including a channel region, a high concentration impurity region, and a low concentration impurity region partially overlapping the gate electrode, wherein the low concentration impurity region includes a GOLDD region overlapping with the gate electrode and an LDD region not overlapping with the gate electrode. And the length of the LDD region is equal to or larger than the length of the GOLDD region.

The length of the LDD region is preferably 2 탆 or less. On the other hand, the length of the GOLDD region is preferably 0.5 to 2㎛.

When the length of the LDD region is equal to the length of the GOLDD region, the dose of impurities doped in the LDD region is preferably equal to or smaller than the dose of impurities doped in the GOLDD region.

It is preferable that the semiconductor layer is a polycrystalline silicon semiconductor layer. In this case, the semiconductor layer may be a semiconductor layer crystallized by ELA, SLS, MIC or MILC method.

It is preferable that the impurities doped in the high concentration impurity region and the low concentration impurity region are n-type impurities.

The gate electrode may be formed of one metal selected from the group consisting of aluminum (Al), aluminum alloy (Al alloy), molybdenum (Mo), and molybdenum alloy (Mo alloy). In addition, the gate electrode may be located on the semiconductor layer.

The thin film transistor may further include a gate insulating layer positioned between the gate electrode and the semiconductor layer, and the gate insulating layer may be formed of a silicon oxide layer, a silicon nitride layer, or a double layer thereof.

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings in order to describe the present invention in more detail. However, the present invention is not limited to the embodiments described herein but may be embodied in other forms. In the figures, where a layer is said to be "on" another layer or substrate, it may be formed directly on the other layer or substrate, or a third layer may be interposed therebetween. Like numbers refer to like elements throughout the specification.

1A to 1D are cross-sectional views illustrating a method of manufacturing a thin film transistor according to an exemplary embodiment of the present invention.

Referring to FIG. 1A, a substrate 100 is provided. The substrate 100 may be provided as a glass or plastic substrate. A buffer layer 105 may be formed on the substrate 100. The buffer layer 105 is a layer for protecting a thin film transistor formed in a subsequent process from impurities flowing out of the substrate 100, and may be formed of a silicon oxide film or a silicon nitride film.

The semiconductor layer 110 is formed on the buffer layer 105. The semiconductor layer 110 may be formed by forming an amorphous silicon film on the buffer layer 105, and then forming the amorphous silicon film on an Excimer Laser Annealing (ELA), Sequential Lateral Solidification (SLS), Metal Induced Crystallization (MIC) or MILC. It can be carried out by crystallization using the (Matal Induced Lateral Crystallization) method and patterning it. Thus, the semiconductor layer 110 is formed of a polycrystalline silicon layer having a higher charge mobility than the amorphous silicon layer.

A gate insulating layer 120 is formed on the semiconductor layer 110. The gate insulating layer 120 may be formed of a silicon oxide layer, a silicon nitride layer, or a double layer thereof. Subsequently, a first photoresist pattern 191 is formed on the gate insulating layer 120 to shield a predetermined portion of the semiconductor layer 110, and the semiconductor is formed using the first photoresist pattern 191 as a mask. The layer 110 is doped with lightly doped impurities. As a result, low concentration impurity regions 110a are formed in the semiconductor layer 110, and a channel region 110b positioned between the low concentration impurity regions 110a is defined.

Referring to FIG. 1B, the first photoresist pattern (191 of FIG. 1A) is removed, and a second photoresist pattern 193 is formed on the substrate on which the low concentration impurity region 110a is formed. The second photoresist pattern 193 is formed to overlap a predetermined portion of the low concentration impurity region 110a and to expose both ends of the semiconductor layer 110. The semiconductor layer 110 is heavily doped with impurities using the second photoresist pattern 193 as a mask. As a result, high concentration impurity regions 110c doped with the impurities at high concentration are formed at both ends of the semiconductor layer 110. Low concentration impurity regions 110a are disposed between the high concentration impurity regions 110c and adjacent to the high concentration impurity regions 110c. In addition, a channel region 110b is positioned between the low concentration impurity regions 110a.

The term “high concentration doping” does not mean an absolute high concentration, but means that the doping is performed at a higher dose than the “low concentration doping”. In addition, the highly doped impurities are impurities of the same type as the lightly doped impurities.

Referring to FIG. 1C, a gate conductive layer is formed on the gate insulating layer 120. The gate conductive layer is preferably formed of one metal selected from the group consisting of aluminum (Al), aluminum alloy (Al alloy), molybdenum (Mo), and molybdenum alloy (Mo alloy). More preferably, the gate conductive film is formed of molybdenum-tungsten alloy.

A third photoresist pattern 195 is formed on the gate conductive layer. The third photoresist pattern 195 is wider than the width of the first photoresist pattern (W1 of FIG. 1A) and has a narrow width W3 compared to the width of the second photoresist pattern (W2 of FIG. 1B). Have The gate conductive layer is etched using the third photoresist pattern 195 as an etch mask. As a result, the gate electrode 130 partially overlapping the low concentration impurity region 110a is formed.

The low concentration impurity region 110a overlapping the gate electrode 130 is a gate overlapped lightly doped drain (GOLDD) region 110a-1, and the low concentration impurity region 110a not overlapping the gate electrode is a general lightly LDD. doped drain) region 110a-2. The length L2 of the LDD region is equal to or longer than the length L1 of the GOLDD region. This effectively suppresses the off current and at the same time prevents deterioration due to hot carrier injection, and furthermore, it is possible to obtain optimized reliability characteristics of the thin film transistor. Adjusting the length L2 of the LDD region and the length L1 of the GOLDD region may be performed by adjusting the width W3 of the third photoresist pattern. In addition, the length L2 of the LDD region is preferably 2 μm or less in order to obtain proper on current characteristics of the thin film transistor. On the other hand, the length (L1) of the GOLDD region is preferably 0.5 to 2㎛. The reason is that when the length L1 of the GOLDD region is less than 0.5 μm, the resolution limit of the exposure apparatus may be exceeded, and when the length L1 of the GOLDD region exceeds 2 μm, the length of the gate electrode 130 may also be This is because the area occupied by the thin film transistors increases, resulting in a decrease in the aperture ratio in the flat panel display apparatus.

Referring to FIG. 1D, after the third photoresist pattern 195 of FIG. 1C is removed to expose the gate electrode 130, an interlayer insulating layer 140 is formed to cover the exposed gate electrode 130. The interlayer insulating layer 140 may be formed of a silicon oxide film, a silicon nitride film, or a double layer thereof.

A source / drain contact hole for exposing the high concentration impurity region 110c is formed in the interlayer insulating layer 140. A thin film transistor is manufactured by stacking a source / drain conductive layer on the entire surface of the substrate on which the source / drain contact hole is formed and patterning the source / drain electrode to form a source / drain electrode 150.

The thin film transistor may be an n-type or p-type thin film transistor. Preferably, the thin film transistor is an n-type thin film transistor. The reason is that n-type thin film transistors generally have a larger off-state current than p-type thin film transistors and are easily deteriorated due to hot carrier injection, thereby forming the LDD region 110a-2 and the GOLDD region 110a-1. This is because the off current reduction effect and the deterioration prevention effect can be largely obtained. To this end, the impurities doped in the semiconductor layer 110 to form the low concentration impurity region 110a and the high concentration impurity region 110c are n-type impurities. The n-type impurity may be P (phosphorus) or As (arsenic).

Hereinafter, preferred examples are provided to aid the understanding of the present invention. However, the following experimental examples are only for helping understanding of the present invention, and the present invention is not limited to the following experimental examples.

Experimental Example 1

A GOLDD region having a doping amount of 1e13ions / cm2 with P (phosphorus) as an impurity and a doped amount having a length of 1e13ions / cm2 with an impurity A thin film transistor was formed.

Experimental Example 2

A thin film transistor was formed in the same manner as the thin film transistor according to Experimental Example 1 except that the length of the LDD region was 1 μm.

Comparative Example 1

A thin film transistor was formed in the same manner as the thin film transistor according to Experimental Example 1 except that the length of the LDD region was 0.5 μm.

Comparative Example 2

Except that the LDD region was not formed, the same thin film transistor as in the thin film transistor according to Experimental Example 1 was formed.

After applying a threshold voltage to the gate electrode of each of the thin film transistors according to Experimental Examples 1 and 2 and Comparative Examples 1 and 2 and applying a predetermined voltage to the drain electrode for 60 seconds (that is, to the thin film transistor After stress), the charge mobility was measured in the same state. The charge mobility of each voltage was measured while increasing the voltage applied to the drain electrode, that is, the drain voltage in 1V units within a range of 8 to 17V. The measured charge mobility is shown in FIG. 2 in terms of the relative charge mobility with respect to the charge mobility before stressing the thin film transistors.

2 is a graph showing relative charge mobility with respect to the drain voltage of each of the thin film transistors according to Experimental Examples 1 and 2 and Comparative Examples 1 and 2;

Referring to FIG. 2, it can be seen that the thin film transistors (c and d) according to Comparative Examples 1 and 2 rapidly deteriorate relative charge mobility characteristics as the drain voltage to which stress is applied increases. That is, the thin film transistor (c) according to Comparative Example 1 having a short LDD region compared to the length of the GOLDD region has a DC reliability characteristic that is not significantly different from that of the thin film transistor (d) according to Comparative Example 2 having no LDD region. Seems. However, the thin film transistor (b) according to Experimental Example 2, in which the length of the LDD region is the same as that of the GOLDD region, exhibits moderate degradation of relative charge mobility characteristics, and the length of the LDD region is longer than that of the GOLDD region. In the thin film transistor (a) according to Experimental Example 1, the relative charge mobility characteristics did not change even when the drain voltage under stress was increased to 17V.

As a result, it can be seen that the DC reliability characteristics are improved in the case of the thin film transistor in which the length of the LDD region is equal to or larger than the length of the GOLDD region. On the other hand, when the length of the LDD region is formed to have the length of the GOLDD region, and the dose amount of the LDD region is formed equal to or smaller than the dose amount of the GOLDD region, the above DC reliability characteristics are improved. Can be.

As described above, according to the present invention, a thin film transistor having a GOLDD region and an LDD region and exhibiting optimized reliability characteristics can be obtained.

Claims (10)

A gate electrode; A semiconductor layer comprising a channel region, a high concentration impurity region and a low concentration impurity region partially overlapped with the gate electrode, The low concentration impurity region includes a GOLDD region overlapping the gate electrode and an LDD region not overlapping the gate electrode, and the length of the LDD region is equal to or greater than the length of the GOLDD region. The method of claim 1, The LDD region has a length of less than 2㎛ thin film transistor. The method of claim 1, The length of the GOLDD region is a thin film transistor, characterized in that 0.5 to 2㎛. The method of claim 1, If the length of the LDD region is the same as the length of the GOLDD region, And a dose amount of impurities doped in the LDD region is equal to or smaller than a dose amount of impurities doped in the GOLDD region. The method of claim 1, The semiconductor layer is a thin film transistor, characterized in that the polycrystalline silicon semiconductor layer. The method of claim 5, wherein The semiconductor layer is a thin film transistor, characterized in that the semiconductor layer crystallized by ELA, SLS, MIC or MILC method. The method of claim 1, And the impurities doped in the high concentration impurity region and the low concentration impurity region are n-type impurities. The method of claim 1, The gate electrode is a thin film transistor, characterized in that formed of one metal selected from the group consisting of aluminum (Al), aluminum alloy (Al alloy), molybdenum (Mo) and molybdenum alloy (Mo alloy). The method of claim 1, And the gate electrode is on the semiconductor layer. The method of claim 1, And a gate insulating film positioned between the gate electrode and the semiconductor layer, wherein the gate insulating film is formed of a silicon oxide film, a silicon nitride film, or a double layer thereof.

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