KR100600851B1 - Flat Panel Display with improved white balance - Google Patents

Abstract

The present invention discloses a flat panel display that can improve white balance by varying a resistance value by doping a drain offset region of a driving transistor at different concentrations in R, G, and B unit pixels of each pixel.

The flat panel display device of the present invention includes R, G, and B unit pixels for implementing red (R), green (G), and blue (B), respectively, and the unit pixels each include a transistor having a source / drain region. And a plurality of pixels, wherein the transistors of at least two unit pixels among the R, G, and B unit pixels have different drain values.

Each of the unit pixels having different resistance values includes a light emitting device, and all transistors for controlling the supply of current to each light emitting device of the unit pixels have channel layers having the same size. The drain regions of the R, G and B unit pixels have offset regions having different doping concentrations, and the drains of the transistors for driving the light emitting devices having the highest luminous efficiency among the transistors of the R, G and B unit pixels. The offset region has a lower doping concentration of impurities than the drain offset region of the transistor for driving the light emitting device having a lower luminous efficiency than the light emitting device.

Description

Flat Panel Display with improved white balance

1 is a diagram showing an arrangement of R, G, and B unit pixels of a conventional flat panel display.

2 to 4 illustrate planar structures of driving transistors of R, G and B unit pixels in a flat panel display device according to an exemplary embodiment of the present invention.

* Description of the symbols for the main parts of the drawings *

210: semiconductor layers 221, 225: source / drain regions

223, 227: offset region 230: gate

241, 245: source / drain contacts 251, 255: source / drain electrodes

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a full color flat panel display, and more particularly, to a flat panel display capable of realizing white balance by varying the resistance value of the drain region by varying the doping concentration of the drain side offset region.

In general, an organic light emitting display device, which is a flat panel display device, includes a plurality of pixels 100 arranged in a matrix form, as shown in FIG. 1, and each pixel 100 is a unit for implementing red (R). It consists of three unit pixels: a pixel 110R, a unit pixel 120G for implementing green (G), and a unit pixel 130B for implementing blue (B).

The R unit pixel 110R includes a red EL element 115 having a red (R) light emitting layer, a driving transistor 113 for supplying current to the red EL element 115, and the driving transistor 113. To the red EL element 113 from the switching transistor 111 for switching. The G unit pixel 120G includes a green EL element 125 having a green (G) light emitting layer, a driving transistor 123 for supplying current to the green EL element 125, and the driving transistor 123. And a switching transistor 121 for switching the supply of current to the green EL element 123. The B unit pixel 130B includes a blue EL element 135 having a blue (B) light emitting layer, a driving transistor 133 for supplying current to the blue EL element 135, and the driving transistor 133. Switching transistor 131 for switching the current supply to the blue EL element 135.

Typically, the driving transistors 113, 123, and 133 of the R, G, and B unit pixels 110R, 120G, and 130B of the OELD have a size, that is, a ratio W of the width W to the length L of the channel layer. / L) are all constant, and the EL element has high luminous efficiency in order of B, R, and G unit pixels. Therefore, while the sizes of the driving transistors 113, 123, and 133 of the R, G, and B unit pixels 110R, 120G, and 130B are all constant, light emission of each of the R, G, and B EL layers 115, 125, and 135 is constant. Since the efficiencies differed, it was difficult to achieve white balance.

In order to realize the white balance, a relatively small amount of current must be supplied to an EL device having a high luminous efficiency, for example, a green EL device, and a relatively large amount of current is supplied to a red and blue EL device having a low luminous efficiency. You should.

At this time, the current Id flowing through the driving transistor to the EL element is expressed as in Equation (1) since the driving transistor is operated in a saturated state.

Id = Cox mu W {(Vg-Vth)} ^ {2} / 2L ..... (1)

Therefore, one of the methods for controlling the current flowing to the EL element to realize the white balance is the size of the driving transistors of the R, G, and B unit pixels, that is, the width W of the channel length L of the transistor. There is a method of controlling the amount of current flowing through the EL elements of R, G, and B unit pixels by varying the ratio (W / L). As such, a method of controlling the amount of current flowing to the EL element according to the size of the transistor is disclosed in Japanese Patent Laid-Open No. 2001-109399. The Japanese patent forms the size of the driving transistors of the R, G, and B unit pixels differently according to the luminous efficiency of the EL element for each of the R, G, and B unit pixels. That is, the size of the driving transistor of the unit pixel for implementing green (G) having high luminous efficiency is made smaller than that of the unit transistor for implementing red (R) or blue (B) having low luminous efficiency. The amount of current flowing to the EL elements of the R, G, and B unit pixels was controlled by zooming.

Another method for implementing the white balance is a method of differently forming the area of the light emitting layer of the R, G, B unit pixels, which is disclosed in Japanese Patent Laid-Open No. 2001-290441. The Japanese patent forms light emitting areas differently according to the luminous efficiency of EL elements of R, G and B unit pixels, thereby generating the same luminance of R, G and B unit pixels. That is, the light emitting area of the R unit pixel or B unit pixel having low luminous efficiency than the G unit pixel having high luminous efficiency is formed to be relatively large so that the same luminance is generated through the R, G, and B unit pixels.

However, the conventional method for implementing the white balance as described above is to form a large light emitting area of the unit pixel of low luminous efficiency among the R, G, B unit pixels, or the luminous efficiency of the R, G, B unit pixels By increasing the size of the transistor of a low unit pixel, the area occupied by each pixel increases, and thus there is a problem that it is difficult to apply to high resolution.

Accordingly, an object of the present invention is to provide a flat panel display device and a method of manufacturing the same, which can implement white balance without increasing the pixel area.

Another object of the present invention is to provide a flat panel display device capable of realizing white balance by varying resistance values of drain regions of driving transistors for R, G, and B unit pixels.

Another object of the present invention is to provide a flat panel display which can realize white balance by varying the doping concentration of the drain offset region of the driving transistor for each R, G, B unit pixel.

In order to achieve the object as described above, the present invention comprises R, G, B unit pixels for implementing red (R), green (G), blue (B), respectively, the unit pixels are source / drain And a plurality of pixels each having a transistor having a region, wherein the transistors of at least two unit pixels among the R, G, and B unit pixels provide a flat panel display device having a drain value having a different resistance value. do.

Each of the unit pixels having different resistance values includes a light emitting device, and all of the transistors for controlling the supply of current to the light emitting devices of the unit pixels have channel layers having the same size. The resistance value of the drain region of the transistor for driving the light emitting device having the highest luminous efficiency among the transistors of the R, G, and B unit pixels is the resistance of the drain region of the transistor for driving the light emitting device having the low luminous efficiency. It is characterized by being larger than the value.

The drain regions of the R, G and B unit pixels have offset regions having different doping concentrations, and the drains of the transistors for driving the light emitting devices having the highest luminous efficiency among the transistors of the R, G and B unit pixels. The offset region is characterized in that the doping concentration of the impurity is lower than the drain offset region of the transistor for driving the light emitting device having a lower luminous efficiency than the light emitting device.

Each of the R, G, and B unit pixels includes a light emitting device driven by the transistor, wherein the source / drain regions have respective offset regions, and the transistors of the R, G, and B unit pixels The source offset regions are all doped with impurities, and the drain offset region is characterized in that the doping concentration of the impurities is different according to the luminous efficiency of the light emitting device.

Each of the R, G, and B unit pixels includes a light emitting device driven by the transistor, wherein the source / drain regions have respective offset regions, and the transistors of the R, G, and B unit pixels The source offset regions are all doped with impurities at the same concentration, and the drain offset region is characterized in that the doping concentration of the impurities is different according to the luminous efficiency of the light emitting device.

Each of the R, G, and B unit pixels includes a light emitting device driven by the transistor, wherein the source / drain regions have respective offset regions, and the transistors of the R, G, and B unit pixels The source / drain offset region is characterized in that the doping concentration of the impurity varies depending on the luminous efficiency of the light emitting device.

Each unit pixel includes a light emitting device driven by the transistor, wherein the drain offset regions of at least two transistors of the transistors are doped with different doping concentrations, and the luminous efficiency of the transistors of the R, G, and B unit pixels is increased. The channel region of the transistor for driving a high light emitting device is doped with a lower impurity concentration than the channel region of another transistor.

Hereinafter, embodiments of the present invention will be described with reference to the accompanying drawings.

2 to 4 illustrate a planar structure of an organic light emitting display device according to an exemplary embodiment of the present invention, which is limited to driving transistors of R, G, and B pixel units.

Referring to FIG. 2, the driving transistor 113 of the R unit pixel includes a semiconductor layer 210, a gate 230, and source / drain electrodes 251 and 255. The semiconductor layer 210 includes a channel layer 224 formed at a portion corresponding to the gate 230, and high concentration source / drain regions 221 and 225 formed at both sides of the channel layer 224. In this case, the high concentration source / drain regions 221 and 225 are electrically connected to the source / drain electrodes 251 and 255 through the contacts 241 and 245, respectively.

In addition, the semiconductor layer 210 further includes offset regions 223 and 227 formed between the channel layer 224 and the high concentration source / drain regions 221 and 225. The source offset region 223 of the offset regions 223 and 227 is a region that is not doped with impurities, and the drain offset region 227 has the same conductivity type as the source / drain regions 221 and 225. It is a region doped with a relatively low concentration of impurities.

Referring to FIG. 3, the driving transistor 123 of the G unit pixel includes a semiconductor layer 310, a gate 330, and source / drain electrodes 351 and 355. The semiconductor layer 310 includes a channel layer 324 formed at a portion corresponding to the gate 330, and high concentration source / drain regions 321 and 325 formed at both sides of the channel layer 324. The high concentration source / drain regions 321 and 325 are electrically connected to the source / drain electrodes 351 and 355 through the contacts 341 and 345, respectively.

In addition, the semiconductor layer 310 further includes offset regions 323 and 327 formed between the channel layer 324 and the high concentration source / drain regions 321 and 325. The offset regions 323 and 327 are all intrinsic regions which are not doped with impurities.

Referring to FIG. 4, the driving transistor 133 of the B unit pixel includes a semiconductor layer 410, a gate 430, and source / drain electrodes 451 and 455. The semiconductor layer 410 includes a channel layer 424 formed at a portion corresponding to the gate 430, and high concentration source / drain regions 421 and 425 formed at both sides of the channel layer 424. The high concentration source / drain regions 421 and 425 are electrically connected to the source / drain electrodes 451 and 455 through the contacts 441 and 445, respectively.

In addition, the semiconductor layer 410 further includes offset regions 423 and 427 formed between the channel layer 424 and the high concentration source / drain regions 421 and 425. The source offset region 423 of the offset regions 423 and 427 of the B unit pixel is an intrinsic region which is not doped with impurities, and the drain offset region 427 has the same conductivity type as the source / drain regions 421 and 425. The dopant is doped with a relatively higher concentration than the drain offset region 227 of the R unit pixel.

In an embodiment of the present invention, the driving transistors of R, G, and B unit pixels having different luminous efficiencies are formed to have the same size, and the lengths of the drain offset regions Lroff, Lgoff, and Lboff are formed the same, and the doping concentration is White balance was realized by forming different resistance values according to the.

That is, since the R and B unit pixels have lower luminous efficiency than the G unit pixels, the drain offset region 327 of the G unit pixel having high luminous efficiency is formed to have a large resistance value without being doped. On the other hand, the drain offset region 427 of the B unit pixel having the lowest luminous efficiency is formed to have a small resistance by doping at a high concentration, and the drain offset region of the R unit pixel having the luminous efficiency between the G unit pixel and the B unit pixel. A reference numeral 237 is formed to have a low doping concentration, so as to have a resistance value between the G unit pixels and the B unit pixels.

In the exemplary embodiment of the present invention, an offset region is also formed on the source side without being doped with impurities, but the source offset region of the R unit pixel may be lightly doped and the source offset region of the B unit pixel may be doped at a high concentration, similarly to the drain offset region. have. Further, the offset region may be formed only on the drain side without forming the offset region on the source side.

In addition, in the G unit pixel, the drain offset region is not doped, and only the drain offset regions of the R and B unit pixels are doped at low and high concentrations, respectively, but the difference in the resistance value of the drain region for implementing the white balance occurs. It is also possible to do all of the drain offset regions of the G, B unit pixels with different doping concentrations.

According to the embodiment of the present invention as described above, the white balance can be realized without increasing the pixel area by changing the resistance value by changing the doping concentration of the drain offset region of the R, G, B unit pixels.

Although described above with reference to a preferred embodiment of the present invention, those skilled in the art will be variously modified and changed within the scope of the invention without departing from the spirit and scope of the invention described in the claims below I can understand that you can.

Claims (10)

R, G, and B unit pixels for implementing red (R), green (G), and blue (B), respectively, and the unit pixels each include a plurality of pixels each including a transistor having a source / drain region. , And the transistors of at least two unit pixels among the R, G, and B unit pixels have sheet resistances different from each other in the drain offset region. The method of claim 1, wherein the unit pixels having different resistance values are each provided with a light emitting element, and the channel layers of the transistors for controlling the current supply to the light emitting element of each unit pixel are all the same size. Flat panel display device. 3. The surface resistance of the drain offset region of the transistor for driving the light emitting device having the highest luminous efficiency among the transistors is higher than the resistance value of the drain region of the transistor for driving the light emitting device having the low luminous efficiency. Flat panel display device characterized in that large. The flat panel display of claim 1, wherein the drain regions of the R, G, and B unit pixels have offset regions having different doping concentrations. The light emitting device of claim 4, wherein each unit pixel includes a light emitting device driven by the transistor, and a drain offset region of the transistor for driving the light emitting device having the highest luminous efficiency among the transistors has a light emitting efficiency that is higher than that of the light emitting device. And a doping concentration of an impurity lower than a drain offset region of a transistor for driving a low light emitting device. The R, G and B unit pixels each include a light emitting device driven by the transistor, wherein the source / drain regions each include an offset region, and the R, G, The source offset regions of the transistors of the B unit pixels are all doped with impurities, and the doping concentration of the impurities is different depending on the luminous efficiency of the light emitting device. The R, G and B unit pixels each include a light emitting device driven by the transistor, wherein the source / drain regions each include an offset region, and the R, G, The source offset regions of the transistors of the B unit pixels are all doped with the same impurity concentration, and the drain offset region is characterized in that the doping concentration of the impurities is different according to the luminous efficiency of the light emitting device. The R, G and B unit pixels each include a light emitting device driven by the transistor, wherein the source / drain regions each include an offset region, and the R, G, A source / drain offset region of a transistor of a B unit pixel has a doping concentration of an impurity according to the luminous efficiency of the light emitting device. The flat panel display of claim 1, wherein each of the unit pixels has doped impurities at different doping concentrations in at least two of the transistors of the R, G, and B unit pixels. 10. The transistor of claim 9, wherein each of the R, G, and B unit pixels includes a light emitting device driven by the transistor, and a drain offset region of a transistor for driving a light emitting device having high luminous efficiency among the transistors is different from each other. And a dopant concentration lower than the drain offset region of the flat panel display device.

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