KR100542985B1 - Flat Panel Display with improved white balance - Google Patents

Abstract

According to the present invention, a flat plate capable of improving white balance by changing the geometric structure of the offset region by changing the offset length of the offset region between the multi gates of the driving transistors in R, G, and B unit pixels of each pixel. A display device is started.

The flat panel display device of the present invention includes R, G, and B unit pixels for implementing red (R), green (G), and blue (B), and each unit pixel includes a transistor having a multi-gate. A transistor of at least two unit pixels among the R, G, and B unit pixels includes a plurality of pixels and includes offset regions having different geometric structures between the multi gates.

The total lengths of the offset regions between the multi-gates of the transistors of the R, G, and B unit pixels are all the same, and the offset lengths of the portions in which the impurities are not doped in the offset regions are different from each other. The R, G, and B unit pixels have offset regions of transistors for driving light emitting devices having the highest luminous efficiency among the transistors than offset regions of transistors for driving light emitting devices having lower luminous efficiency than the light emitting devices. It is characterized by a long length.

Description

Flat Panel Display with improved white balance

1 is a diagram showing an arrangement of R, G, and B unit pixels of a conventional flat panel display.

2A and 2B illustrate a planar structure and a cross-sectional structure of a driving transistor of an R unit pixel in a flat panel display device according to an exemplary embodiment of the present invention.

3A and 3B illustrate a planar structure and a cross-sectional structure of a driving transistor of a G unit pixel in a flat panel display device according to an exemplary embodiment of the present invention.

4A and 4B illustrate a planar structure and a cross-sectional structure of a driving transistor of a B unit pixel in a flat panel display device according to an exemplary embodiment of the present invention.

* Description of the symbols for the main parts of the drawings *

220, 320, 420: semiconductor layers 230, 330, 430: offset region

240, 241, 245, 340, 341, 345, 440, 441, 445: gate

221, 225, 321, 325, 421, 425: source / drain regions

251, 255, 351, 355, 451, 455 for source / drain contacts

261, 265, 361, 365, 461, 465: source / drain electrodes

270, 370 mask 235, 335, 435 doping area

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a full color flat panel display. More particularly, the present invention relates to a flat display apparatus capable of realizing white balance by changing a geometrical structure of an offset region by changing an offset length of an offset region between multiple gates. will be.

In general, an organic light emitting display device, which is a flat panel display device, includes a plurality of pixels 100 arranged in a matrix form as shown in FIG. 1, and each pixel 100 is a unit for implementing red (R). It consists of three unit pixels: a pixel 110R, a unit pixel 120G for implementing green (G), and a unit pixel 130B for implementing blue (B).

The R unit pixel 110R includes a red EL element 115 having a red (R) light emitting layer, a driving transistor 113 for supplying current to the red EL element 115, and the driving transistor 113. To the red EL element 115 from the switching transistor 111. The G unit pixel 120G includes a green EL element 125 having a green (G) light emitting layer, a driving transistor 123 for supplying current to the green EL element 125, and the driving transistor 123. Switching transistor 121 for switching the supply of current to the green EL element 125. The B unit pixel 130B includes a blue EL element 135 having a blue (B) light emitting layer, a driving transistor 133 for supplying current to the blue EL element 135, and the driving transistor 133. And a switching transistor 131 for switching the current supply to the blue EL element 135 from the above.

Typically, the R, G, and B unit pixels 110R, 120G, and 130B of the OELD have a size W of the driving transistors 113, 123, and 133, that is, a ratio W of the width W to the length L of the channel layer. / L) are all constant, and the EL element has high luminous efficiency in the order of B, R, and G unit pixels. Therefore, while the size (W / L) of the channel layers of the driving transistors 113, 123, and 133 of the R, G, and B unit pixels 110R, 120G, and 130B are all the same, the respective R, G, and B EL layers ( Since the luminous efficiencies of the 115, 125, and 135 are different from each other, it is difficult to realize a white balance.

In order to realize the white balance, a relatively small amount of current must be supplied to an EL device having a high luminous efficiency, for example, a green EL device, and a relatively large amount of current is supplied to a red and blue EL device having a low luminous efficiency. You should.

At this time, the current Id flowing through the driving transistor to the EL element is expressed by Equation (1) since the driving transistor is operated in a saturated state.

Id = Cox mu W {(Vg-Vth)} ^ {2} / 2L ..... (1)

Therefore, one of the methods for controlling the current flowing to the EL element to realize the white balance is the size of the driving transistors of the R, G, and B unit pixels, that is, the width W of the channel length L of the transistor. There is a method of controlling the amount of current flowing through the EL elements of R, G, and B unit pixels by varying the ratio (W / L). Thus, a method of controlling the amount of current flowing to the EL element according to the size of the transistor is disclosed in Japanese Patent Laid-Open No. 2001-109399. The Japanese patent forms the size of the driving transistors of the R, G, and B unit pixels differently according to the luminous efficiency of the EL element for each of the R, G, and B unit pixels. That is, the size of the driving transistor of the unit pixel for implementing green (G) having high luminous efficiency is made smaller than that of the unit transistor for implementing red (R) or blue (B) having low luminous efficiency. The amount of current flowing to the EL elements of the R, G, and B unit pixels was controlled by zooming.

Another method for implementing the white balance is a method of differently forming the area of the light emitting layer of the R, G, B unit pixels, which is disclosed in Japanese Patent Laid-Open No. 2001-290441. The Japanese patent forms light emitting areas differently according to the luminous efficiency of EL elements of R, G and B unit pixels, thereby generating the same luminance of R, G and B unit pixels. That is, the light emitting area of the R unit pixel or B unit pixel having low luminous efficiency than the G unit pixel having high luminous efficiency is formed to be relatively large so that the same luminance is generated through the R, G, and B unit pixels.

However, the conventional method for implementing the white balance as described above is to form a large light emitting area of the unit pixel of low luminous efficiency among the R, G, B unit pixels, or the luminous efficiency of the R, G, B unit pixels By increasing the size of the transistor of a low unit pixel, the area occupied by each pixel increases, and thus there is a problem that it is difficult to apply to high resolution.

Accordingly, an object of the present invention is to provide a flat panel display device and a method of manufacturing the same, which can implement white balance without increasing the pixel area.

Another object of the present invention is to provide a flat panel display device which can realize white balance by changing the resistance value by changing the geometry of the offset region between the multi-gates of the driving transistors for each R, G, and B unit pixels. There is a purpose.

Another object of the present invention is to provide a flat panel display which can realize white balance by varying the offset length of the offset region between the multi-gates of the driving transistors for each R, G, and B unit pixels.

In order to achieve the object as described above, the present invention is each provided with R, G, B unit pixels for implementing red (R), green (G), blue (B), each unit pixel is a multi-gate Provides a flat panel display including a plurality of pixels having a transistor having a transistor, wherein at least two unit pixels of the R, G, B unit pixels have offset regions having different geometries between the multi-gates. Characterized in that.

The R, G, and B unit pixels include a light emitting device driven by the transistor, and resistance of an offset region of the transistor for driving the light emitting device having the highest luminous efficiency among the transistors of the R, G and B unit pixels. The value is larger than the resistance value of the offset region of the transistor for driving the light emitting device having a relatively low luminous efficiency.

The total lengths of the offset regions between the multi-gates of the transistors of the R, G, and B unit pixels are all the same, and the offset lengths of the portions in which the impurities are not doped in the offset regions are different from each other. The R, G, and B unit pixels have offset regions of transistors for driving light emitting devices having the highest luminous efficiency among the transistors than offset regions of transistors for driving light emitting devices having lower luminous efficiency than the light emitting devices. It is characterized by a long length.

The total lengths of the offset regions between the multi-gates of the transistors of the R, G, and B unit pixels are all the same, and the widths of the offset regions are different from each other, or the offsets between the multi-gates of the transistors of the R, G, and B unit pixels are different. The widths of the regions are all the same, and the lengths of the offset regions are different.

Hereinafter, embodiments of the present invention will be described with reference to the accompanying drawings.

2A illustrates a planar structure of a driving transistor of an R unit pixel in an organic light emitting display device according to an exemplary embodiment of the present invention, and FIG. 2B illustrates a cross-sectional structure of a driving transistor of an R unit pixel. It is a cross-sectional structure along the line 2A-2A 'of 2a.

2A and 2B, a driving transistor R_DTR 113 of an R unit pixel includes a semiconductor layer 220, a gate electrode 240, and source / drain electrodes 261 and 265. The gate electrode 240 includes multi gates 241 and 245 corresponding to the semiconductor layer 220. The semiconductor layer 220 may include the multi channel layers 223 and 227 formed at portions corresponding to the multi gates 241 and 245, and the source / side formed at one side of the channel layers 223 and 227. Drain regions 221 and 225 are provided. The source / drain regions 221 and 225 are electrically connected to the source / drain electrodes 261 and 265 through contacts 251 and 255, respectively.

In addition, the semiconductor layer 220 further includes an offset region 230 between the multi-gates 241 and 245, that is, between the multi-channel layers 223 and 227. The offset region 230 includes a portion 235 doped with a high concentration of impurities of the same conductivity type as the source / drain regions 221 and 225, and an offset portion 231 not doped with impurities. The length occupied by the offset portion of the length Lr of 230 is Lroff.

In FIG. 2A, reference numeral 270 denotes a mask used to define the offset length Lroff among the offset regions 230 between the multi-gates 241 and 245. That is, the mask 270 is used as an ion implantation mask when doping an impurity into a portion 231 of the offset region 230, and the offset length Lroff according to the overlapping degree between the mask 270 and the offset region 230. Is determined.

3A illustrates a planar structure of a driving transistor of a G unit pixel in an organic light emitting display device according to an exemplary embodiment of the present invention, and FIG. 3B illustrates a cross-sectional structure of a driving transistor of a G unit pixel. It is a cross-sectional structure along the line 3A-3A 'of 3a.

3A and 3B, the driving transistors G_DTR and 123 of the G unit pixel include a semiconductor layer 320, a gate electrode 340, and source / drain electrodes 361 and 365. The gate electrode 340 includes multi gates 341 and 345 corresponding to the semiconductor layer 320. The semiconductor layer 320 may include a multi channel layer 323 and 327 corresponding to the multi gates 341 and 345, and a source / drain region formed at one side of the multi channel layers 323 and 327. 321 and 325 are provided. The source / drain regions 321 and 325 are electrically connected to the source / drain electrodes 361 and 365 through the contacts 351 and 355, respectively.

In addition, the semiconductor layer 320 further includes an offset region 330 between the multi-gates 341 and 345, that is, between the multi-channel layers 323 and 327. The offset region 330 includes a portion 335 doped with a high concentration of impurities of the same conductivity type as the source / drain regions 321 and 325 and an offset portion 331 not doped with impurities. The length occupied by the offset portion of the length Lg of 330 is Lgoff.

In FIG. 3A, reference numeral 370 denotes a mask used to define the offset length Lgoff among the offset regions 330 between the multi gates 341 and 345. That is, the mask 370 is used as an ion implantation mask when doping impurities into a portion 331 of the offset region 330, and the offset length Lgoff according to the overlapping degree between the mask 370 and the offset region 330. Is determined.

The driving transistor of the G unit pixel having the highest luminous efficiency among the R, G, and B unit pixels has a relatively low luminous efficiency of the offset length Lgoff among the offset regions 330 between the multi-gates 341 and 345. The driving transistor is formed to be longer than the offset length Lroff of the offset regions 230 between the multi-gates 241 and 245 of the driving transistor of the unit pixel.

4A illustrates a planar structure of a driving transistor of B unit pixels in an organic light emitting display device according to an exemplary embodiment of the present invention, and FIG. 4B illustrates a cross-sectional structure of a driving transistor of B unit pixels. It is a cross-sectional structure along the line 4A-4A 'of 4a.

4A and 4B, the driving transistors B_DTR and 133 of the B unit pixel are the driving transistors G_DTR and 123 of the G unit pixel, and the semiconductor layer 420, the gate electrode 440, and the source / drain electrode. (461) and (465). The gate electrode 440 includes multi gates 441 and 445 corresponding to the semiconductor layer 420. The semiconductor layer 420 may include source / drain regions formed on one side of the multi channel layers 423 and 427 corresponding to the multi gates 441 and 445, and the multi channel layers 423 and 427. 421 and 425 are provided. The source / drain regions 421 and 425 are electrically connected to the source / drain electrodes 461 and 465 through the contacts 451 and 455, respectively.

In addition, the semiconductor layer 420 further includes an offset region 430 between the multi-gates 441 and 445, that is, between the multi-channel layers 423 and 427. Unlike the R or G unit pixels, the offset region 430 is entirely doped with high concentration impurities of the same conductivity type as the source / drain regions 321 and 325. Therefore, the length occupied by the offset portion of the length Lb of the offset area 430 is Lboff = 0.

As described above, the driving transistor of the G unit pixel having the highest luminous efficiency among the R, G, and B unit pixels has a relative offset length Lgoff among the offset regions 330 between the multi gates 341 and 345. The driving transistor of the B unit pixel having the lowest luminous efficiency is formed longer than the offset length Lroff of the offset regions 230 between the multi-gates 241 and 245 of the driving transistor of the R unit pixel having low luminous efficiency. By doping all of the offset regions 430 between the multi-gates to make Lboff = 0f, white balance can be realized by differently setting resistance values of the offset regions between the multi-gates of R, G, and B pixel units.

In an embodiment of the present invention, the offset region between the multi-gates of each of the driving transistors of the R, G, and B unit pixels is formed to have a different geometric structure, thereby changing the resistance value of the offset region to implement white balance. will be.

That is, the lengths (Lr, Lg, Lb) of the offset regions between the multi-gates of R, G, and B unit pixels having different luminous efficiencies are made the same, and impurities are not doped in the offset regions 230, 330, and 430. By making the offset lengths (Lroff, Lgoff, and Lboff) different from each other, the white balance is realized by forming offset regions between the multi-gates of each unit pixel to have different resistance values.

In other words, the G unit pixel having the highest luminous efficiency is formed to have the largest resistance value by making the offset length the longest among the offset regions 330. On the other hand, the B unit pixel having the lowest luminous efficiency is formed to have the smallest resistance value by doping the offset region 430 as a whole so that the offset length is 0, and R having the luminous efficiency between the G unit pixel and the B unit pixel. The offset region 230 of the unit pixel is formed to have an offset length Lroff smaller than the offset length Lgoff of the offset region 330 of the G unit pixel, thereby forming a resistance value between the G unit pixel and the B unit pixel. It is formed to have.

In the embodiment of the present invention, although the multi-gate is composed of two gates, the offset region between the multi-gates of the driving transistors of the R, G, and B unit pixels is different from each other regardless of the structure and the number of gates of the multi-gate. By having a structure, all structures formed to have different resistance values are possible.

As another embodiment of the present invention, the white balance may be implemented by changing the resistance value in the offset region by changing the size (W / L) of the offset region between the multi-gates of the R, G, and B unit pixels. For example, by setting the total length of the offset regions between the multi-gates of the R, G, and B unit pixels to be the same, and forming the offset regions to have different widths, the offset regions of the R, G, and B unit pixels are mutually different. It may be formed to have different resistance values. In addition, the widths of the offset regions between the multi-gates of the R, G, and B unit pixels are set to be the same, and the total length of the offset regions is formed differently so that the offset regions of the R, G, and B unit pixels have different resistance values. It may be formed to have.

Further, as another embodiment of the present invention, the size of the offset region between the multi-gates of the R, G, and B unit pixels is changed, and at the same time, the impurities in the offset region of the R, G, and B unit pixels are similar to those of the above embodiment. By changing the length of the undoped offset portion, the white balance may be realized by changing the resistance value of the offset region between the multigates.

According to the embodiment of the present invention as described above, the geometric structure of the offset region between the multi-gate of the R, G, B unit pixel is formed differently to change the resistance value of each offset region without increasing the pixel area. White balance can be implemented.

Although described above with reference to a preferred embodiment of the present invention, those skilled in the art will be variously modified and changed within the scope of the invention without departing from the spirit and scope of the invention described in the claims below I can understand that you can.

Claims (8)

Each of which has R, G, and B unit pixels for implementing red (R), green (G), and blue (B), each unit pixel including a plurality of pixels including a transistor having a multi-gate; And the transistors of at least two unit pixels of the R, G, and B unit pixels have offset regions having different geometries between the multi-gates. The method of claim 1, wherein the R, G, B unit pixels include a light emitting element driven by the transistor, and to drive the light emitting element having the highest luminous efficiency among the transistors of the R, G, B unit pixels. The resistance value of the offset region of the transistor is larger than the resistance value of the offset region of the transistor for driving a light emitting device having a relatively low luminous efficiency. The method of claim 1, wherein the total lengths of the offset regions between the multi-gates of the transistors of the R, G, and B unit pixels are all the same, and offset lengths of portions of the offset region that are not doped with impurities are different from each other. Flat Panel Display. The light emitting device of claim 3, wherein each of the R, G, and B unit pixels includes a light emitting device driven by the transistor, and an offset region of the transistor for driving the light emitting device having the highest light emitting efficiency among the light emitting devices is the light emitting device. A flat panel display device having an offset length longer than that of an offset region of a transistor for driving a light emitting device having a lower luminous efficiency than the device. The flat panel display of claim 1, wherein the total lengths of the offset regions between the multi-gates of the transistors of the R, G, and B unit pixels are all the same, and the widths of the offset regions are different from each other. The light emitting device of claim 5, wherein the R, G, and B unit pixels include a light emitting device driven by the transistor, and an offset region of the transistor for driving the light emitting device having the highest light emitting efficiency among the light emitting devices is the light emitting device. A flat panel display device having an offset length longer than that of an offset region of a transistor for driving a light emitting device having a lower luminous efficiency than the device. The flat panel display of claim 1, wherein the widths of the offset regions between the multi-gates of the transistors of the R, G, and B unit pixels are the same, and the offset regions have different lengths. 10. The light emitting device of claim 7, wherein the R, G, and B unit pixels have light emitting devices driven by the transistor, and an offset region of the transistor for driving the light emitting device having the highest light emitting efficiency among the light emitting devices is the light emission. A flat panel display device having an offset length longer than that of an offset region of a transistor for driving a light emitting device having a lower luminous efficiency than the device.

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