KR100599449B1 - Cmos variable gain amplifier - Google Patents

Abstract

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a CMOS variable gain amplifier, comprising: an input gain adjuster for amplifying an input signal and a differential input signal of a variable voltage to a fixed gain value and outputting the voltage at a voltage level; An output resistance adjuster for adjusting gain by changing a resistance; a current separator for separating a part of the current flowing from the output resistance adjuster to an input gain adjuster; and an input gain adjuster for adjusting an input gain of the input gain adjuster. Comprising a bias current adjuster, it is possible to input a wide range of voltage to generate a constant size output signal, it is possible to realize a low-power high-speed variable amplifier using the current split method.

Gain, amplification

Description

CMOS VARIABLE GAIN AMPLIFIER             

1 is a control circuit block diagram according to an embodiment of the present invention;

2 is a circuit diagram of an input gain adjustment unit of the present invention;

3 is a circuit diagram of an output resistance adjusting unit and a current separating unit of the present invention;

4 is a circuit diagram of a bias current adjusting unit of the present invention;

5 is a circuit diagram of the maximum variable gain of the present invention;

6 is a circuit diagram of the low voltage bias of the present invention.

<Explanation of symbols for the main parts of the drawings>

1: input gain adjustment unit

2: output resistance adjusting section

3: current separator

4: bias current adjuster

Q: transistor

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a CMOS variable gain amplifier. More particularly, the present invention relates to a CMOS variable gain amplifier, which reduces power consumption by using a current division method and expands an input and output voltage range by adjusting an output resistance value. It relates to a gain amplifier.

When designing a CMOS variable gain amplifier, considerations include the size of the frequency bandwidth, the low power design, the size of the input signal to ensure linearity, the regulation voltage and the gain control range. In addition, the dependence of temperature and power supply voltage on the circuit is also one of the very important considerations.

However, due to current device technology characteristics, CMOS circuits are unlikely to have an operating frequency range of 100 MHz or more. In addition, due to the limitation in size reduction of the threshold voltage of the MOS device, it is difficult to expect smooth operation for a low power supply because the size of the input / output signal is limited.

Accordingly, there are many problems in implementing a CMOS variable gain amplifier having low power consumption and operating at high speed at low voltage in an integrated circuit.

Accordingly, an object of the present invention is to solve the above-described problems of the prior art, and provides a stable current bias by providing a variable gain amplification function for an input signal having a wide range by a regulated voltage at low supply voltage and small power consumption. And to provide a CMOS variable gain amplifier having a wide band operation characteristics by a variable output resistor.

According to one aspect of the present invention, there is provided a CMOS variable gain amplifier including: an input gain adjuster configured to amplify an input signal and a differential input signal having a variable voltage to a fixed gain value, and output the voltage at a voltage level; An output resistance adjuster connected to the input gain adjuster to adjust a gain by receiving a variable voltage to change an output resistance; A current separator for separating a part of the current flowing from the output resistance adjuster to the input gain adjuster; And a bias current adjuster connected to the input gain adjuster to adjust the input gain of the input gain adjuster.

In addition, the CMOS variable gain amplifier of the present invention comprises: an input gain adjuster for amplifying an input signal and a differential input signal of a variable voltage to a fixed gain value and outputting the voltage at a voltage level; An output resistance adjuster connected to the input gain adjuster to adjust a gain by receiving a variable voltage to change an output resistance; A current separator for separating a part of the current flowing from the output resistance adjuster to the input gain adjuster; And a bias current adjuster connected to the input gain adjuster to adjust the input gain of the input gain adjuster.

Hereinafter, a CMOS variable gain amplifier of the present invention will be described in detail with reference to the accompanying drawings.

1 is a control circuit block diagram according to an embodiment of the present invention. As shown in FIG. 1, the CMOS variable gain amplifier of the present invention has a large input gain controller 1, an output impedance controller 2, and a current bliding 3; It consists of a bias current controller (Current Controller) (4).

)에 의해 결정되어 진다. 이

은 소스전극과 드레인전극 사이의 거리와 소스전극에 흐르는 전류의 양에 의해 결정된다. The input gain adjusting unit 1 adjusts the gain of an input signal, and is a transconductance of a CMOS transistor (

Is determined by). this

Is determined by the distance between the source electrode and the drain electrode and the amount of current flowing through the source electrode.

The output resistance adjusting unit 2 adjusts the overall gain by changing the output resistance as a method of adjusting the gain.

The current separating unit 3 is a circuit for flowing a part of the current flowing to the input gain adjusting unit 1 out of the current flowing from the output resistance adjusting unit 2 to the ground, and is used to obtain a large gain with small current consumption. Lose.

을 변경시킨다. The bias current adjuster 4 is one of methods of adjusting the gain of the input gain.

To change.

The overall gain of the variable gain amplifier of the present invention is given by the following equation.

은 입력 이득 조정부(1)의 트랜지스터 트랜스컨덕턴스(transconductance)이며,

는 출력 저항을 각각 의미한다. here,

Is the transistor transconductance of the input gain adjustment section 1,

Denotes the output resistance respectively.

값과

를 조정하여 이득을 조정할 수 있다. In other words,

Value and

You can adjust the gain by adjusting.

은 두 가지 방법으로 조정이 가능하다. remind

Can be adjusted in two ways.

의 첫 번째 조정 방법은 소스전극과 드레인전극사이 길이를 조정하는 것이다. 하지만, 상기 길이를 조정하는 것은 실제적으로 불가능하므로 가변 이득 동작에 이용하지 못한다. among them

The first adjustment method is to adjust the length between the source and drain electrodes. However, adjusting the length is practically impossible and therefore not available for variable gain operation.

의 두 번째 조정 방법은, 드레인전극에서 소스전극에 흐르는 전류의 양을 조정하는 방법으로서, 크게 두 가지로 조정이 가능하다. 전류량 조정 방법의 하나는, 바이어스 전류를 조정하는 방법으로서, 바이어스 전류 조정부(4)에서 담당하게 된다. 한편, 바이어스 전류를 조정하는 다른 하나는, 입력 이득 조정부(1)의 게이트 전압을 조정함으로써 구현이 가능하게 된다. Meanwhile,

The second adjustment method of is to adjust the amount of current flowing from the drain electrode to the source electrode, which can be largely adjusted in two ways. One of the current amount adjustment methods is a method for adjusting the bias current, which is in charge of the bias current adjustment unit 4. On the other hand, the other to adjust the bias current can be implemented by adjusting the gate voltage of the input gain adjustment unit (1).

를 능동 소자를 이용하여 구현한 후, 게이트 전압을 조정함으로써

를 증감할 수 있다.

Is implemented using an active element, and then the gate voltage is adjusted.

Can increase or decrease.

That is, by adjusting the values of the three methods, the input gain adjusting unit 1, the output resistance adjusting unit 2 and the bias current adjusting unit 4, the entire variable gain range can be increased.

과 큰

를 구현하면 가능하다. 이 때,

을 증가시키기 위해서는 큰 바이어스 전류가 필요하지만

는 바이어스 전류의 크기에 반비례므로, 큰 이득을 얻기 힘들게 된다. 이 때, 전류 분리부(3)를 이용하여 To increase the variable gain range of a variable gain amplifier, especially when a large gain is required

And big

This is possible by implementing At this time,

In order to increase the

Since is inversely proportional to the magnitude of the bias current, it is difficult to obtain a large gain. At this time, by using the current separator 3

Current flowing to the input gain adjuster 1

= Current flowing through the output resistance adjusting section (2) + current flowing through the current separating section (3)

Implementing this allows a large gain with a small supply current.

2 is a circuit diagram of an input gain adjustment unit of the present invention. As shown in FIG. 2, the input gain adjuster includes a first transistor Q1 and a second transistor Q2 that receive an input signal, a source electrode connected to a drain electrode of the first transistor Q1, and variable to a gate electrode. The source electrode is connected to the drain electrode of the third transistor Q3 and the second transistor Q2 that receive the voltage, and is composed of the fourth transistor Q4 that receives the variable voltage to the gate electrode.

를 조정한다. 상기

의 조정에 따라 이득이 조정되어 진다. By adjusting the gate voltages of the third and fourth transistors Q3 and Q4 located above the input port, the first and second transistors Q1 and Q2 of the first and second transistors Q3 and Q4 are adjusted. By adjusting the amount of current flowing to the source electrode

Adjust it. remind

The gain is adjusted according to the adjustment of.

3 is a circuit diagram of a current separator and an output resistance adjuster of the present invention. As illustrated in FIG. 3, the output resistance adjusting unit includes a fifth transistor Q5 and a fourth transistor Q4 connected to a source electrode of the third transistor Q3 and receiving a variable voltage from the gate electrode. A source electrode is connected to the drain electrode, and the sixth transistor Q6 receives a variable voltage from the gate electrode. In addition, the current separation unit includes a seventh transistor Q7 connected to a source electrode in common with the drain electrodes of the third transistor Q3 and the fourth transistor Q4 and receiving a set voltage V1 from the gate electrode. have.

The source-drain resistances of the fifth transistor Q5 and the sixth transistor Q6 may be varied by adjusting the gate voltages of the fifth transistor Q5 and the sixth transistor Q6 constituting the output resistance. This makes it possible to vary the overall gain. In addition, the current obtained by adding the current flowing through the current separator 3 and the output resistance adjuster 2 can flow through the input gain adjuster 1 to increase the gain. The amount of current flowing through the output resistance adjuster 2 is adjusted by an external voltage.

4 is a circuit diagram of a bias current adjuster of the present invention. As shown in FIG. 4, the bias current adjusting unit has a drain electrode connected to the source electrodes of the first transistor Q1 and the second transistor Q2, the source electrode being grounded, and a variable voltage applied to the gate electrode and the drain electrode. The contacts of the eighth transistor Q8, the first transistor Q1 drain electrode and the third transistor Q3 source electrode, and the second transistor Q2 drain electrode and the fourth transistor Q4 source electrode, respectively. The drain electrode is connected, the source electrode is grounded, and the ninth transistor Q9 is provided with a variable voltage applied to the gate electrode and the drain electrode.

The gain is adjusted by adjusting the amount of current in the input gain adjusting unit 1 through the variable voltage.

5 is a circuit diagram of the maximum variable gain of the present invention. As illustrated in FIG. 5, a first transistor and a second transistor receiving an input signal, a third transistor Q3 connected to a source electrode of the drain electrode of the first transistor Q1 and receiving a variable voltage from the gate electrode thereof. And an input gain adjuster including a source transistor connected to the drain electrode of the second transistor Q2 and receiving a variable voltage at the gate electrode, and a source electrode connected to the drain electrode of the third transistor Q3. An output comprising a sixth transistor Q6 connected to the source electrode connected to the drain electrode of the fifth transistor Q5 and the fourth transistor Q4 and receiving the variable voltage at the gate electrode. A seventh source electrode connected to the resistance adjusting unit and the drain electrodes of the third and fourth transistors Q3 and Q4 and receiving the set voltage V1 from the gate electrode; A current separator comprising a transistor Q7, a drain electrode connected to the source electrodes of the first transistor Q1 and the second transistor Q2, the source electrode grounded, and a variable voltage applied to the gate electrode and the drain electrode. The drains of the eighth transistor Q8, the contacts of the first transistor Q1 drain electrode and the third transistor Q3 source electrode, and the contacts of the second transistor Q2 drain electrode and the fourth transistor Q4 source electrode, respectively. An electrode is connected, the source electrode is grounded, and a bias current adjuster composed of a ninth transistor Q9 to which a variable voltage is applied to the gate electrode and the drain electrode.

In this way, if the input gain adjustment, the bias current adjustment, and the output resistance adjustment are all used, the change in gain can be made very large. In this embodiment, NMOS is used as the transistor.

The more advanced the CMOS process, the lower the voltage used as the bias. In general, 1.8V is used for 0.18 μm, and 1.2V is used for 0.13 μm. In this case, the stack of CMOS transistors that can be used is limited to three or less. Therefore, the structure as shown in Figure 5 can not be used because the stack is four layers. In addition, when only the input gain adjusting section 1 is adopted to obtain the variable gain, the magnitude of the inputtable signal is also limited.

However, when configured as shown in the low voltage bias configuration example of FIG. 6, a three-layer stack and a larger input power can be input.

That is, as shown in FIG. 6, the first transistor and the second transistor receiving the input signal, the source transistor is connected to the drain electrode of the first transistor Q1 and the third transistor receiving the variable voltage at the gate electrode ( A source gain is connected to the drain electrode of Q3) and the second transistor Q2 and includes an input gain adjusting unit including a fourth transistor Q4 that receives a variable voltage at the gate electrode, and a drain electrode of the third transistor Q3. The source electrode is connected to the drain electrode of the fifth transistor Q5 and the fourth transistor Q4 that receive the variable voltage, and the source electrode is connected to the sixth transistor Q6 that receives the variable voltage. A source electrode is commonly connected to the configured output resistance adjusting unit and the drain electrodes of the third and fourth transistors Q3 and Q4, and receives a set voltage V1 from the gate electrode. It consists of a current separator composed of the seventh transistor Q7.

Although the present invention has been described in more detail with reference to some embodiments, the present invention is not necessarily limited to these embodiments, and various modifications can be made without departing from the spirit of the present invention.

As described above, the CMOS variable gain amplifier according to the present invention can implement a large variable gain by adopting three current gain adjusting units. In particular, the large current gain can be realized by reducing the power consumption by adopting a current separator, and a large variable gain and a large input signal can be received even at a low power supply bias.

Claims (9)

An input gain adjuster configured to amplify the input signal and the differential input signal having a variable voltage to a fixed gain value and output the voltage at a voltage level; An output resistance adjuster connected to the input gain adjuster to adjust a gain by receiving a variable voltage to change an output resistance; And Current separation unit for separating a portion of the current flowing from the output resistance adjustment unit to the input gain adjustment unit CMOS variable gain amplifier comprising a. The method of claim 1, wherein the input gain adjustment unit, A first transistor and a second transistor configured to receive an input signal through the gate electrode; A third transistor having a source electrode connected to the drain electrode of the first transistor and receiving a variable voltage at the gate electrode; And A fourth transistor connected to the drain electrode of the second transistor and receiving a variable voltage from the gate electrode CMOS variable gain amplifier, characterized in that consisting of. The method of claim 1, wherein the output resistance adjusting unit, A fifth transistor connected to the input gain adjuster and receiving a variable voltage at a gate electrode; And A sixth transistor connected to a source electrode of the input gain adjusting unit and receiving a variable voltage from a gate electrode; CMOS variable gain amplifier, characterized in that consisting of. The method of claim 1, wherein the current separation unit, A seventh transistor connected to the input gain adjusting unit with a source electrode receiving the set voltage V1 from the gate electrode; CMOS variable gain amplifier, characterized in that consisting of. 5. The CMOS variable gain amplifier according to any one of claims 1 to 4, further comprising a bias current adjuster connected to the input gain adjuster for adjusting an input gain of the input gain adjuster. The method of claim 5, wherein the bias current adjustment unit, An eighth transistor having a drain electrode connected to the input gain adjusting unit, a source electrode grounded, and a variable voltage applied to the gate electrode and the drain electrode; A ninth transistor having a drain electrode connected to the input gain adjusting unit, a source electrode grounded, and a variable voltage applied to the gate electrode and the drain electrode; CMOS variable gain amplifier, characterized in that consisting of. A first electrode and a second transistor receiving an input signal, a source electrode connected to the drain electrode of the first transistor, and a source electrode connected to the drain electrode of the third transistor and the second transistor receiving the variable voltage. An input gain adjuster configured of a fourth transistor configured to receive a variable voltage at an electrode; A fifth transistor having a source electrode connected to the drain electrode of the third transistor and receiving a variable voltage at the gate electrode, and a sixth transistor connected to the drain electrode of the fourth transistor and receiving a variable voltage at the gate electrode; An output resistance adjuster; And A current separator comprising a seventh transistor connected to a source electrode in common with the drain electrodes of the third and fourth transistors and receiving a set voltage V1 from the gate electrode; CMOS variable gain amplifier comprising a. 8. The transistor of claim 7, wherein a drain electrode is connected to the source electrodes of the first and second transistors, the source electrode is grounded, and a variable voltage is applied to the gate electrode and the drain electrode; A drain electrode is connected to each of the contacts of the third transistor source electrode and the contacts of the second transistor drain electrode and the fourth transistor source electrode. The ninth transistor includes a ground voltage and a variable voltage applied to the gate electrode and the drain electrode. And a bias current adjuster. 10. The CMOS variable gain amplifier of claim 7 or 8 wherein the transistor is an NMOS.

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