JP2004064213A - Differential amplifier circuit - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a differential amplifier circuit ofh a high voltage gain without the need for a large layout area and without waveform distortion and deterioration in the frequency characteristics. <P>SOLUTION: A regulated current supplied to input NMOS 1, 2 receiving differential input signals INP, INN in addition to a current supplied from load NMOS 3, 4 of diode connection. Thereby, the differential amplifier circuit can have a high voltage gain without the need for increasing the size (channel width) of the input NMOS 1, 2. Thus, the drain-source voltage Vds of the NMOS 1, 2 is increased to prevent waveform distortion due to reduction in the dynamic range. Further, the input capacitance is reduced to prevent deterioration in the frequency characteristics. <P>COPYRIGHT: (C)2004,JPO

Description

【００１４】
（１）式に示すように、Ｖｇｓ１１−Ｖｔ＝√（Ｉ１１／Ｋ１１），Ｖｇｓ１３−Ｖｔ＝√（Ｉ１３／Ｋ１３）であるから、電圧利得ＧＡＰは次の（６）式のように表される。

【００１５】
同様に、入力用のＮＭＯＳ１２と負荷用のＮＭＯＳ１４からなる増幅回路の電圧利得ＧＡＮは、次の（７）式で表される。
ＧＡＮ＝√｛（Ｋ１２×Ｉ１２）／（Ｋ１４×Ｉ１４）｝　・・・（７）
【００１６】
従って、図２の差動増幅回路全体の電圧利得ＧＡ２は、次の（８）式のようになる。

【００１７】
ここで、一般的に、Ｉ１１＝Ｉ１３＝Ｉ１２＝Ｉ１４，Ｋ１１＝Ｋ１２，Ｋ１３＝Ｋ１４であるから、（８）式の電圧利得ＧＡ２は、次の（９）式のようになる。
ＧＡ２＝２√（Ｋ１１／Ｋ１３）　・・・（９）
【００１８】
製造プロセスによる定数Ｐが一定であるとすると、電圧利得ＧＡ２は、（２）式で示されるように、入力用のＮＭＯＳ１１，１２と負荷用のＮＭＯＳ１３，１４のゲート幅／ゲート長（＝Ｗ／Ｌ）の比で決定されることになる。
【００１９】
【発明が解決しようとする課題】
【００２０】
しかしながら、従来の差動増幅回路では、次のような課題があった。
【００２１】
電圧利得ＧＡ２が、入力用のＮＭＯＳ１１，１２と負荷用のＮＭＯＳ１３，１４のサイズ（ゲート幅）比に依存するため、電圧利得の高い差動増幅回路を実現するには、負荷用のＮＭＯＳ１３，１４に比べて、入力用のＮＭＯＳ１１，１２のサイズを大きくする必要がある。このため、半導体集積回路におけるレイアウト面積が増大し、集積度が低下するという問題があった。
【００２２】
また、入力用のＮＭＯＳ１１，１２のサイズを大きくすると、ドレイン・ソース電圧Ｖｄｓが減少するが、ゲート・ソース電圧Ｖｇｓが大きい場合には、入力信号ＩＮＰ，ＩＮＮに対するダイナミックレンジが小さくなる。このため、ＮＭＯＳ１１，１２が非飽和領域で動作し、出力信号ＯＵＴＰ，ＯＵＴＮに波形歪みが発生するという問題があった。
【００２３】
更に、入力用のＮＭＯＳ１１，１２のサイズが大きいと、入力キャパシタンスが増大し、周波数特性が劣化するという問題があった。
【００２４】
本発明は、前記従来技術が持っていた課題を解決し、大きなレイアウト面積を必要とせずに高い電圧利得が得られ、波形歪みや周波数特性の劣化がない差動増幅回路を提供するものである。
【００２５】
【課題を解決するための手段】
【００２６】
前記課題を解決するために、本発明の内の第１の発明は、差動増幅回路において、差動入力信号によってそれぞれ導通状態が制御される第１及び第２の入力トランジスタと、前記第１及び第２の入力トランジスタと同一の導電型で、該第１及び第２の入力トランジスタにそれぞれ直列にダイオード接続された第１及び第２の負荷トランジスタと、前記第１及び第２の入力トランジスタにそれぞれ一定の電流を供給する第１及び第２の定電流源と、前記第１及び第２の入力トランジスタに流れる電流の和を一定値に制御する第３の定電流源とを備えている。
【００２７】
第２の発明は、第１の発明における第１の負荷トランジスタを、ドレインとゲートを電源電位に接続し、ソースを第１の出力ノードに接続した第１導電型のＭＯＳで構成し、第２の負荷トランジスタを、ドレインとゲートを前記電源電位に接続し、ソースを第２の出力ノードに接続した第１導電型のＭＯＳで構成している。
【００２８】
また、第１の定電流源を、ソース及びドレインをそれぞれ前記電源電位及び第１の出力ノードに接続し、ゲートに第１のバイアス電圧が与えられる第２導電型のＭＯＳで構成し、記第２の定電流源を、ソース及びドレインをそれぞれ前記電源電位及び第２の出力ノードに接続し、ゲートに第２のバイアス電圧が与えられる第２導電型のＭＯＳで構成している。
【００２９】
更に、第１の入力トランジスタを、ドレイン及びソースをそれぞれ前記第１の出力ノード及び第３の定電流源に接続し、ゲートに前記差動入力信号の一方が与えられる第１導電型のＭＯＳで構成し、第２の入力トランジスタを、ドレイン及びソースをそれぞれ前記第２の出力ノード及び第３の定電流源に接続し、ゲートに前記差動入力信号の他方が与えられる第１導電型のＭＯＳで構成している。
【００３０】
本発明によれば、以上のように差動増幅回路を構成したので、次のような作用が行われる。
【００３１】
第１の入力トランジスタには、第１の負荷トランジスタの電流に加えて、第１の定電流源からの電流が流れる。また、第２の入力トランジスタには、第２の負荷トランジスタの電流に加えて、第２の定電流源からの電流が流れる。そして、これらの第１及び第２の入力トランジスタに流れる電流の和は、第３の定電流源によって一定値に制御される。これにより、差動入力信号は、第１及び第２の入力トランジスタで増幅され、第１及び第２の負荷トランジスタから出力される。
一方、第１及び第２の入力トランジスタに流れる電流は、第１及び第２の負荷トランジスタに流れる電流よりも大きくなるので、これらの入力トランジスタのサイズを大きくしなくても高い電圧利得を得ることができる。
【００３２】
【発明の実施の形態】
【００３３】
図１は、本発明の実施形態を示す差動増幅回路の回路図である。
【００３４】
この差動増幅回路は、入力用のＮＭＯＳ１，２、負荷用のＮＭＯＳ３，４、定電流供給用のＰチャネルＭＯＳ（以下、「ＰＭＯＳ」という）５，６、及び定電流源７を備えている。
【００３５】
ＮＭＯＳ１，２のゲートには、差動的な入力信号ＩＮＰ，ＩＮＮがそれぞれ入力されるようになっており、これらのＮＭＯＳ１，２のドレインは、それぞれノードＮＮ，ＮＰに接続され、ソースは共通の定電流源７を介して接地電圧ＧＮＤに接続されている。
【００３６】
ノードＮＮにはダイオード接続されたＮＭＯＳ３のソースが接続され、このＮＭＯＳ３のドレインとゲートが電源電圧ＶＤＤに接続されている。また、ノードＮＰにはダイオード接続されたＮＭＯＳ４のソースが接続され、このＮＭＯＳ４のドレインとゲートが電源電圧ＶＤＤに接続されている。
【００３７】
更に、ノードＮＮには、ＰＭＯＳ５のドレインが接続され、このＰＭＯＳ５のソースが電源電圧ＶＤＤに接続されている。ノードＮＰには、ＰＭＯＳ６のドレインが接続され、このＰＭＯＳ６のソースが電源電圧ＶＤＤに接続されている。ＰＭＯＳ５，６のゲートには、それぞれ所定のバイアス電圧ＶＢ５，ＶＢ６が与えられ、これらのＰＭＯＳ５，６を通してノードＮＮ，ＮＰに、一定電流Ｉ５，Ｉ６が供給されるようになっている。
【００３８】
そして、ノードＮＮ，ＮＰから、増幅された差動的な出力信号ＯＵＴＮ，ＯＵＴＰがそれぞれ出力されるようになっている。
【００３９】
次に、動作を説明する。
【００４０】
図１において、ＮＭＯＳ１〜４に流れるドレイン電流をそれぞれＩ１〜Ｉ４とすると、ＰＭＯＳ５，６からノードＮＮ，ＮＰに、それぞれ一定電流Ｉ５，Ｉ６が供給されるので、次の（１０）式の関係が成り立つ。
Ｉ１＝Ｉ３＋Ｉ５，　Ｉ２＝Ｉ４＋Ｉ６　　・・・（１０）
【００４１】
また、この差動増幅回路全体の電圧利得ＧＡ１は、ＮＭＯＳ１〜４のトランスコンダクタンス係数をそれぞれＫ１〜Ｋ４とすると、（８）式に準じて次の（１１）式のようになる。

【００４２】
これに、（１０）式の関係を代入すると、次の（１２）式が得られる。

【００４３】
ここで、Ｉ１＝Ｉ２＝Ｉ３＝Ｉ４，Ｉ５＝Ｉ６，Ｋ１＝Ｋ２，Ｋ３＝Ｋ４とすると、（１２）式の電圧利得ＧＡ１は、次の（１３）式のようになる。
ＧＡ１＝２√｛Ｋ１（Ｉ３＋Ｉ５）／（Ｋ３×Ｉ３）｝　・・・（１３）
【００４４】
次に、図１中のＮＭＯＳ３，４と図２中のＮＭＯＳ１３，１４を同一サイズに設定した場合に、図１と図２の差動増幅回路の電圧利得ＧＡ１，ＧＡ２を等しくする条件として、（９）式と（１３）式から、次の（１４）式が導かれる。
Ｋ１＝Ｋ１１×Ｉ３／（Ｉ３＋Ｉ５）　・・・（１４）
【００４５】
（１４）式に示すように、図１中のＮＭＯＳ１，２のトランスコンダクタンス係数Ｋ１は、図２中のＮＭＯＳ１１，１２のトランスコンダクタンス係数Ｋ１１よりも小さくなる。これによるＮＭＯＳ１，２の面積の縮小は、次の（１５）式のようになる。
Ｋ１１−Ｋ１＝Ｋ１１×Ｉ５／（Ｉ３＋Ｉ５）　・・・（１５）
【００４６】
一方、図１における一定電流Ｉ５，Ｉ６は、それぞれＰＭＯＳ５，６によって供給され、このＰＭＯＳ５では（１）式に準じて次の（１６）式が成り立っている。なお、ＰＭＯＳ６も同様である。
Ｋ５＝Ｉ５／（Ｖｇｓ−Ｖｔ）^２　・・・（１６）
【００４７】
従って、ＮＭＯＳ１の面積の縮小量（Ｋ１１−Ｋ１）が、一定電流Ｉ５の電流源であるＰＭＯＳ５の面積（Ｋ５）よりも大きければ、全体としてレイアウト面積を縮小することができるといえる。その条件は、（１５），（１６）式に基づいて、次の（１７）式のように求められる。
Ｋ１１×Ｉ５／（Ｉ３＋Ｉ５）＞Ｉ５／（Ｖｇｓ−Ｖｔ）^２
（Ｖｇｓ−Ｖｔ）^２＞（Ｉ３＋Ｉ５）／Ｋ１１　・・・（１７）
【００４８】
即ち、（１７）式を満足するように、ＰＭＯＳ５，６のゲート・ソース電圧Ｖｇｓ（即ち、バイアス電圧ＶＢ５，ＶＢ６）を印加すれば良い。
【００４９】
このように、本実施形態の差動増幅回路では、入力用のＮＭＯＳ１，２に、それぞれ一定電流Ｉ５，Ｉ６を供給するＰＭＯＳ５，６を有している。これにより、ＮＭＯＳ１，２の面積を大きくせずに電圧利得ＧＡ１を増加させることができるという利点がある。
【００５０】
また、ＮＭＯＳ１，２の面積が大きくならないので、これらのＮＭＯＳ１，２のドレイン・ソース電圧Ｖｄｓが減少せず、入力信号ＩＮＰ，ＩＮＮに対するダイナミックレンジが小さくならない。このため、ＮＭＯＳ１１，１２が非飽和領域で動作して出力信号ＯＵＴＰ，ＯＵＴＮに波形歪みが生ずる、という問題が発生しない。
【００５１】
更に、ＮＭＯＳ１１，１２の入力キャパシタンスは増大せず、周波数特性の劣化のおそれがないという利点がある。
【００５２】
なお、本発明は、上記実施形態に限定されず、種々の変形が可能である。この変形例としては、例えば、次のようなものがある。
【００５３】
（ａ）　定電流供給用のＰＭＯＳ５，６には、固定のバイアス電圧ＶＢ５，６を印加しているが、このバイアス電圧ＶＢ５，６を可変にして、差動増幅回路の電圧利得ＧＡ１を任意に制御できるように構成しても良い。
【００５４】
（ｂ）　定電流供給用のＰＭＯＳ５，６に代えて、他の回路構成の定電流源を用いても良い。
【００５５】
（ｃ）　入力用と負荷用のトランジスタ１〜４をすべてＮＭＯＳで構成しているが、すべてＰＭＯＳで構成しても良い。その場合、定電流供給用のトランジスタ５，６はＮＭＯＳで構成すると共に、電源の極性を逆にする必要がある。
【００５６】
（ｄ）　接地電圧ＧＮＤ側に定電流源７を設けているが、電源電圧ＶＤＤ側に定電流源７を設けても良い。
【００５７】
【発明の効果】
【００５８】
以上詳細に説明したように、第１の発明によれば、第１及び第２の入力トランジスタにそれぞれ一定電流を供給するための、第１及び第２の定電流源を有している。従って、入力トランジスタに流れる電流は負荷トランジスタに流れる電流よりも大きくなり、入力トランジスタのサイズを大きくしなくても高い電圧利得を得ることが可能になる。これにより、レイアウト面積の増加、波形歪み、及び周波数特性の劣化のない差動増幅回路が得られる。
【００５９】
第２の発明によれば、第１及び第２の負荷トランジスタをダイオード接続した第１導電型のＭＯＳ（例えば、ＮＭＯＳ）で構成し、第１及び第２の入力トランジスタをこれらの負荷トランジスタと同じＮＭＯＳで構成し、第１及び第２の定電流源をＰＭＯＳで構成している。これにより、簡単な回路構成で第１と同様の効果を有する差動増幅回路が得られる。
【図面の簡単な説明】
【図１】本発明の実施形態を示す差動増幅回路の回路図である。
【図２】従来の差動増幅回路の一例を示す回路図である。
【符号の説明】
１〜４　　ＮＭＯＳ
５，６　　ＰＭＯＳ
７　　定電流源[0001]
TECHNICAL FIELD OF THE INVENTION
[0002]
The present invention relates to a differential amplifier circuit.
[0003]
[Prior art]
[0004]
FIG. 2 is a circuit diagram showing an example of a conventional differential amplifier circuit.
[0005]
This differential amplifier circuit includes N-channel MOS transistors (hereinafter, simply referred to as “MOS” and N-channel MOS transistors as “NMOS”) 11 and 12 to which differential input signals INP and INN are input, respectively. Have. The drains of the NMOSs 11 and 12 are connected to nodes NN and NP, respectively, and the sources are connected to the ground voltage GND via a common constant current source 15.
[0006]
The source of the diode-connected NMOS 13 is connected to the node NN, and the drain and gate of the NMOS 13 are connected to the power supply voltage VDD. The source of the diode-connected NMOS 14 is connected to the node NP, and the drain and gate of the NMOS 14 are connected to the power supply voltage VDD. Then, amplified differential output signals OUTN and OUTP are output from the nodes NN and NP, respectively.
[0007]
Next, the voltage gain of the differential amplifier circuit will be described.
[0008]
Generally, a drain current Id in a MOS saturation region (a region where the drain current Id does not change even when the drain-source voltage Vds is increased) is determined by a gate-source voltage Vgs, a threshold voltage Vt, and a transconductance coefficient K. It is expressed by the following equation (1).
Id = K (Vgs−Vt) ² (1)
[0009]
Here, the transconductance coefficient K is a value represented by the following equation (2) based on a constant P, a channel width W, and a channel length L determined by a manufacturing process.
K = P × W / L (2)
[0010]
The MOS transconductance gm is obtained by differentiating the drain current Id in the expression (1) with the gate-source voltage Vgs, as shown in the following expression (3).
gm = δId / δVgs = 2K (Vgs−Vt) (3)
[0011]
Now, paying attention to the amplifier circuit composed of the input NMOS 11 and the load NMOS 13 shown in FIG. , Vgs13 and the drain current are I11 and I13, respectively.
[0012]
The mutual conductances gm11 and gm13 of the NMOSs 11 and 13 are expressed by the following equation (4) using the equation (3).
gm11 = δI11 / δVgs11 = 2K11 (Vgs11−Vt)
gm13 = δI13 / δVgs13 = 2K13 (Vgs13−Vt) (4)
[0013]
Here, the voltage gain GAP by the NMOSs 11 and 13 is the ratio of the change (δVgs13) of the output signal OUTN to the change (δVgs11) of the input signal INP, and is expressed by the following equation (5).

[0014]
As shown in the equation (1), since Vgs11−Vt = √ (I11 / K11) and Vgs13−Vt = √ (I13 / K13), the voltage gain GAP is expressed by the following equation (6). .

[0015]
Similarly, the voltage gain GAN of the amplifier circuit including the input NMOS 12 and the load NMOS 14 is expressed by the following equation (7).
GAN = {(K12 × I12) / (K14 × I14)} (7)
[0016]
Accordingly, the voltage gain GA2 of the entire differential amplifier circuit of FIG. 2 is expressed by the following equation (8).

[0017]
Here, since I11 = I13 = I12 = I14, K11 = K12, and K13 = K14, generally, the voltage gain GA2 in the equation (8) is as shown in the following equation (9).
GA2 = 2√ (K11 / K13) (9)
[0018]
Assuming that the constant P due to the manufacturing process is constant, the voltage gain GA2 is, as shown by the equation (2), the gate width / gate length (= W / W) of the input NMOSs 11 and 12 and the load NMOSs 13 and 14. L).
[0019]
[Problems to be solved by the invention]
[0020]
However, the conventional differential amplifier circuit has the following problems.
[0021]
Since the voltage gain GA2 depends on the size (gate width) ratio between the input NMOSs 11 and 12 and the load NMOSs 13 and 14, in order to realize a differential amplifier circuit having a high voltage gain, the load NMOSs 13 and 14 are required. It is necessary to increase the size of the input NMOSs 11 and 12 as compared with the above. For this reason, there has been a problem that the layout area in the semiconductor integrated circuit increases and the degree of integration decreases.
[0022]
Also, when the size of the input NMOSs 11 and 12 is increased, the drain-source voltage Vds decreases, but when the gate-source voltage Vgs is large, the dynamic range for the input signals INP and INN decreases. For this reason, there is a problem that the NMOSs 11 and 12 operate in the non-saturation region and waveform distortion occurs in the output signals OUTP and OUTN.
[0023]
Further, when the size of the input NMOSs 11 and 12 is large, there is a problem that the input capacitance increases and the frequency characteristics deteriorate.
[0024]
An object of the present invention is to provide a differential amplifier circuit which solves the problems of the prior art and provides a high voltage gain without requiring a large layout area, and has no waveform distortion or deterioration of frequency characteristics. .
[0025]
[Means for Solving the Problems]
[0026]
According to a first aspect of the present invention, there is provided a differential amplifier circuit comprising: first and second input transistors, each of which has a conduction state controlled by a differential input signal; And first and second load transistors of the same conductivity type as the first and second input transistors and diode-connected in series with the first and second input transistors, respectively. There are first and second constant current sources that supply a constant current, respectively, and a third constant current source that controls the sum of the currents flowing through the first and second input transistors to a constant value.
[0027]
According to a second invention, the first load transistor in the first invention is constituted by a first conductivity type MOS having a drain and a gate connected to a power supply potential and a source connected to a first output node. Is constituted by a first conductivity type MOS having a drain and a gate connected to the power supply potential and a source connected to the second output node.
[0028]
Further, the first constant current source is constituted by a second conductivity type MOS having a source and a drain connected to the power supply potential and the first output node, respectively, and a gate to which a first bias voltage is applied, and The second constant current source comprises a second conductivity type MOS having a source and a drain connected to the power supply potential and the second output node, respectively, and a gate to which a second bias voltage is applied.
[0029]
Further, the first input transistor is a first conductivity type MOS having a drain and a source connected to the first output node and a third constant current source, respectively, and a gate supplied with one of the differential input signals. A first conductivity type MOS having a second input transistor, a drain and a source connected to the second output node and a third constant current source, respectively, and a gate supplied with the other of the differential input signals. It consists of.
[0030]
According to the present invention, since the differential amplifier circuit is configured as described above, the following operation is performed.
[0031]
The current from the first constant current source flows through the first input transistor in addition to the current of the first load transistor. Further, a current from the second constant current source flows through the second input transistor in addition to the current of the second load transistor. Then, the sum of the currents flowing through the first and second input transistors is controlled to a constant value by the third constant current source. As a result, the differential input signal is amplified by the first and second input transistors and output from the first and second load transistors.
On the other hand, since the current flowing through the first and second input transistors is larger than the current flowing through the first and second load transistors, a high voltage gain can be obtained without increasing the size of these input transistors. Can be.
[0032]
BEST MODE FOR CARRYING OUT THE INVENTION
[0033]
FIG. 1 is a circuit diagram of a differential amplifier circuit according to an embodiment of the present invention.
[0034]
This differential amplifier circuit includes input NMOSs 1 and 2, load NMOSs 3 and 4, P-channel MOSs (hereinafter referred to as “PMOS”) 5 and 6 for supplying a constant current, and a constant current source 7. .
[0035]
Differential input signals INP and INN are input to the gates of the NMOSs 1 and 2, respectively. The drains of the NMOSs 1 and 2 are connected to the nodes NN and NP, respectively, and the sources are common. It is connected to the ground voltage GND via the constant current source 7.
[0036]
The source of the diode-connected NMOS 3 is connected to the node NN, and the drain and gate of the NMOS 3 are connected to the power supply voltage VDD. The source of the diode-connected NMOS 4 is connected to the node NP, and the drain and gate of the NMOS 4 are connected to the power supply voltage VDD.
[0037]
Further, the drain of the PMOS 5 is connected to the node NN, and the source of the PMOS 5 is connected to the power supply voltage VDD. The drain of the PMOS 6 is connected to the node NP, and the source of the PMOS 6 is connected to the power supply voltage VDD. Predetermined bias voltages VB5 and VB6 are applied to the gates of the PMOSs 5 and 6, respectively, and constant currents I5 and I6 are supplied to the nodes NN and NP through the PMOSs 5 and 6, respectively.
[0038]
Then, amplified differential output signals OUTN and OUTP are output from the nodes NN and NP, respectively.
[0039]
Next, the operation will be described.
[0040]
In FIG. 1, assuming that drain currents flowing through NMOSs 1 to 4 are I1 to I4, respectively, constant currents I5 and I6 are supplied from PMOSs 5 and 6 to nodes NN and NP, respectively. Holds.
I1 = I3 + I5, I2 = I4 + I6 (10)
[0041]
Further, when the transconductance coefficients of the NMOSs 1 to 4 are respectively K1 to K4, the voltage gain GA1 of the entire differential amplifier circuit is expressed by the following equation (11) according to the equation (8).

[0042]
By substituting the relationship of equation (10) into this, the following equation (12) is obtained.

[0043]
Here, assuming that I1 = I2 = I3 = I4, I5 = I6, K1 = K2, and K3 = K4, the voltage gain GA1 of the equation (12) becomes the following equation (13).
GA1 = 2 {K1 (I3 + I5) / (K3 × I3)} (13)
[0044]
Next, when the NMOSs 3 and 4 in FIG. 1 and the NMOSs 13 and 14 in FIG. 2 are set to the same size, the conditions for equalizing the voltage gains GA1 and GA2 of the differential amplifier circuits in FIGS. The following expression (14) is derived from the expressions 9) and (13).
K1 = K11 × I3 / (I3 + I5) (14)
[0045]
As shown in the equation (14), the transconductance coefficient K1 of the NMOSs 1 and 2 in FIG. 1 is smaller than the transconductance coefficient K11 of the NMOSs 11 and 12 in FIG. The reduction in the area of the NMOSs 1 and 2 due to this is as shown in the following equation (15).
K11−K1 = K11 × I5 / (I3 + I5) (15)
[0046]
On the other hand, the constant currents I5 and I6 in FIG. 1 are supplied by PMOSs 5 and 6, respectively, and the PMOS 5 satisfies the following equation (16) according to the equation (1). The same applies to the PMOS 6.
K5 = I5 / (Vgs-Vt) ² (16)
[0047]
Therefore, if the reduction amount (K11−K1) of the area of the NMOS 1 is larger than the area (K5) of the PMOS 5, which is the current source of the constant current I5, it can be said that the layout area can be reduced as a whole. The condition is obtained as in the following expression (17) based on the expressions (15) and (16).
K11 × I5 / (I3 + I5)> I5 / (Vgs−Vt) ²
(Vgs−Vt) ² > (I3 + I5) / K11 (17)
[0048]
That is, the gate-source voltages Vgs of the PMOSs 5 and 6 (that is, the bias voltages VB5 and VB6) may be applied so as to satisfy the expression (17).
[0049]
As described above, the differential amplifier circuit of the present embodiment has the PMOSs 5 and 6 that supply the constant currents I5 and I6 to the input NMOSs 1 and 2, respectively. Thus, there is an advantage that the voltage gain GA1 can be increased without increasing the area of the NMOSs 1 and 2.
[0050]
Further, since the areas of the NMOSs 1 and 2 do not increase, the drain-source voltages Vds of the NMOSs 1 and 2 do not decrease, and the dynamic range for the input signals INP and INN does not decrease. Therefore, there is no problem that the NMOSs 11 and 12 operate in the non-saturation region and the output signals OUTP and OUTN have waveform distortion.
[0051]
Further, there is an advantage that the input capacitance of the NMOSs 11 and 12 does not increase and there is no fear of deterioration of frequency characteristics.
[0052]
Note that the present invention is not limited to the above embodiment, and various modifications are possible. For example, there are the following modifications.
[0053]
(A) The fixed bias voltages VB5, 6 are applied to the PMOSs 5, 6 for supplying the constant current. You may comprise so that control is possible.
[0054]
(B) A constant current source having another circuit configuration may be used instead of the PMOSs 5 and 6 for supplying a constant current.
[0055]
(C) Although the input and load transistors 1 to 4 are all configured by NMOS, they may be all configured by PMOS. In this case, the transistors 5 and 6 for supplying the constant current need to be formed of NMOS and the polarity of the power supply needs to be reversed.
[0056]
(D) Although the constant current source 7 is provided on the ground voltage GND side, the constant current source 7 may be provided on the power supply voltage VDD side.
[0057]
【The invention's effect】
[0058]
As described in detail above, according to the first invention, the first and second constant current sources for supplying a constant current to the first and second input transistors, respectively, are provided. Therefore, the current flowing through the input transistor becomes larger than the current flowing through the load transistor, and a high voltage gain can be obtained without increasing the size of the input transistor. As a result, a differential amplifier circuit without an increase in layout area, waveform distortion, and deterioration in frequency characteristics can be obtained.
[0059]
According to the second invention, the first and second load transistors are constituted by diode-connected first conductivity type MOS (for example, NMOS), and the first and second input transistors are the same as these load transistors. The first and second constant current sources are constituted by NMOS, and the first and second constant current sources are constituted by PMOS. As a result, a differential amplifier circuit having the same effects as the first embodiment can be obtained with a simple circuit configuration.
[Brief description of the drawings]
FIG. 1 is a circuit diagram of a differential amplifier circuit according to an embodiment of the present invention.
FIG. 2 is a circuit diagram illustrating an example of a conventional differential amplifier circuit.
[Explanation of symbols]
1-4 NMOS
5,6 PMOS
7 Constant current source

Claims (2)

First and second input transistors, each of which is controlled to be conductive by a differential input signal;
First and second load transistors of the same conductivity type as the first and second input transistors and diode-connected in series to the first and second input transistors, respectively;
First and second constant current sources for supplying a constant current to the first and second input transistors, respectively;
A third constant current source for controlling a sum of currents flowing through the first and second input transistors to a constant value;
A differential amplifier circuit comprising: The first load transistor includes a first conductivity type MOS transistor having a drain and a gate connected to a power supply potential and a source connected to a first output node.
The second load transistor comprises a first conductivity type MOS transistor having a drain and a gate connected to the power supply potential and a source connected to a second output node.
The first constant current source includes a second conductivity type MOS transistor having a source and a drain connected to the power supply potential and a first output node, respectively, and a gate to which a first bias voltage is applied,
The second constant current source includes a second conductivity type MOS transistor having a source and a drain connected to the power supply potential and a second output node, respectively, and a second bias voltage applied to a gate.
The first input transistor is a first conductivity type MOS transistor having a drain and a source connected to the first output node and a third constant current source, respectively, and a gate to which one of the differential input signals is supplied. Make up,
The second input transistor is a first conductivity type MOS transistor having a drain and a source connected to the second output node and a third constant current source, respectively, and a gate supplied with the other of the differential input signals. Configured
The differential amplifier circuit according to claim 1, wherein:

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