KR100592775B1 - Digital to Analog Converter of power amplifier - Google Patents

Abstract

The present invention provides a digital-to-analog converter (DAC) of a power amplifier capable of automatically detecting the power supply voltage and automatically changing the output voltage range according to the change of the power supply voltage to always control the maximum output voltage range. To start. To this end, a power detection unit for comparing the power supply voltage and the reference voltage and output trimming data corresponding to the comparison result value, and controlled by the enable signal and corresponding to the digital signal using the reference voltage and trimming data It characterized in that it comprises a voltage generator for generating an output voltage.

Description

Digital to Analog Converter of power amplifier

1 is a block diagram illustrating a digital-to-analog converter (DAC) of a power amplifier according to the present invention.

FIG. 2 is a detailed circuit diagram illustrating a power comparator shown in FIG. 1. FIG.

FIG. 3 is a detailed block diagram illustrating a digital analog converter shown in FIG. 1. FIG.

4 is a detailed circuit diagram illustrating the bias generator shown in FIG. 3.

FIG. 5 is a detailed block diagram illustrating the current cell array block shown in FIG. 3. FIG.

FIG. 6 is a detailed circuit diagram illustrating the current cell array shown in FIG. 5. FIG.

FIG. 7 is a graph illustrating a change simulation of an output voltage with respect to a change in a power supply voltage in a DAC of the power amplifier shown in FIG.

The present invention relates to a digital-to-analog converter (DAC) of a power amplifier, and more particularly, automatically detects a power supply voltage and automatically changes the output voltage range according to a change in the power supply voltage, thereby always outputting a maximum output. A DAC of a power amplifier that can be controlled over a voltage range.

In general, when a digital to analog converter (DAC) is used to adjust the output power of a power amplifier, the power amplifier's output control range changes when the power supply voltage changes.

However, since the range of the output voltage of the DAC is fixed, there is a problem in that the output of the power amplifier cannot be controlled to the maximum.

To solve this problem, a circuit or chip is added to increase or decrease the output voltage of the DAC. In this case, an additional chip area and cost are generated.

An object of the present invention for solving the above problems is to automatically detect the power supply voltage to automatically change the output voltage range in accordance with the change in the power supply voltage to control to the maximum output voltage range.

Another object of the present invention is to reduce the chip area and hence time and cost by not using additional circuitry to control the maximum output voltage.

The DAC of the power amplifier of the present invention for achieving the above object outputs trimming data obtained by comparing the detected voltage detecting the level of the power supply voltage with a reference voltage and converting the detected voltage into a code value corresponding to the power supply voltage. A power detector; And a voltage generator which is controlled by an enable signal to generate a bias voltage according to the trimming data according to the reference voltage, and adjusts the current by the digital signal according to the bias voltage to generate an output voltage corresponding to the digital signal. It features.

The above and other objects and features and advantages of the present invention will become more apparent from the following detailed description taken in conjunction with the accompanying drawings.

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings.

1 is a block diagram showing a DAC of a power amplifier according to the present invention. Here, an 8-bit DAC is described as an example.

In addition, a current steering type DAC that generates a desired analog output voltage vout by turning on and off a current cell composed of a switch by a digital signal d <0: 7>, for example. Explain.

The DAC according to the present invention includes a power detector 2 and a digital analog converter 4.

The power detector 2 includes a voltage divider 6 and a power comparator 8. The voltage divider 6 includes two resistors 10 and 12 connected in series between a power supply voltage and a ground voltage to output a detected voltage vettet divided at a constant ratio at a common node, and the power comparator 8 ) Compares the detection voltage vette output from the voltage divider 6 with the reference voltage vrefb and outputs trimming data trimm <0: 3> corresponding to the comparison result. The trimming data trimm <0: 3> is a data value obtained by converting the detection voltage vette into a code value corresponding to the power supply voltage.

The digital-to-analog converter 4 uses the enable signal en, the reference voltage vrefb, and the trimming data trimm <0: 3> to output the digital signal d <0 output from the control circuit of the power amplifier. Change the output voltage (vout) corresponding to: 7>.

FIG. 2 is a detailed circuit diagram illustrating the power comparison unit 8 shown in FIG. 1.

The power comparator 8 includes a level divider 14, a comparator 16, and an encoder 18.

The level divider 14 includes a plurality of resistors 15 connected in series between the reference voltage vrefb and the ground voltage to divide the reference voltage vrefb into a comparison voltage having a plurality of levels.

The comparator 16 includes a plurality of comparators 17 to compare the detected voltage vette with a comparison voltage having a corresponding level output from the level divider 14.

The encoder 18 encodes the comparison result output from the comparator 16 and outputs trimming data trim <0: 3>.

FIG. 3 is a detailed block diagram showing the digital-analog converter 4 shown in FIG.

The digital analog converter 4 includes a digital signal buffer 20, an enable signal buffer 22, a trimming data buffer 24, a bias generator 26, a current cell array block 28, and a voltage converter ( 30).

The digital signal buffer 20 buffers and outputs the digital signals d <0: 7>, and the enable signal buffer unit 22 includes two inverters 32 and 33 connected in series to enable the signal (en). ) And the trimming data buffer 24 buffers and outputs the trimming data trim <0: 3>, including a plurality of inverters 36 to 47 connected in series.

The bias generator 26 generates the bias voltages vb1 and vb2 according to the trimming data trimb <0: 3> buffered by the trimming data buffer 24.

The current cell array block 28 includes a plurality of current cell arrays including a corresponding number of current cells so that the current by the corresponding digital signal db <0: 7> may be changed according to the bias voltages vb1 and vb2. Adjust

The voltage converter 30 includes a resistor 48 to convert the current output from the current cell array block 28 into an output voltage vout.

4 is a detailed circuit diagram illustrating the bias generator 26 illustrated in FIG. 3.

The bias generator 26 includes a self bias unit 50, a current converter 52, and a current mirror 54.

The self bias unit 50 generates a bias vbop in accordance with the enable signal enb buffered by the enable signal buffer 22. Here, the inverted enable signal enbb is in phase with the enable signal enb buffered by the enable signal buffer 22.

The current converter 52 includes an operational amplifier to drive the current mirror 54 by comparing the supply voltage vvd with the reference voltage vrefb.

The current mirror 54 is controlled by the inversion enable signal enbb, is driven by the signal output from the current converter 52, and is trimmed by the trimming data buffer 24. The trimming data trimb <0: 7 The bias voltages vb1 and vb2 are generated according to the >

FIG. 5 is a detailed block diagram showing the current cell array block 28 shown in FIG.

The current cell array block 28 includes a plurality of current cell arrays 56 to 70 which are driven by corresponding digital signals db <0: 7> and whose current is regulated by the bias voltages vb1 and vb2. do. Here, each current cell array includes a corresponding number of current cells. That is, the first current cell array 56 includes one current cell, the second current cell array 58 includes two current cells, and the third current cell array 60 uses four current cells. The fourth current cell array 62 comprises eight current cells, the fifth current cell array 64 comprises sixteen current cells, and the sixth current cell array 66 comprises thirty-two current cells. The seventh current cell array 68 includes 64 current cells, and the eighth current cell array 70 includes 128 current cells.

FIG. 6 is a detailed circuit diagram illustrating the current cell array 56 shown in FIG. 5. Here, since the first current cell array 56 includes one current cell, it has the same configuration as the current cell.

The current cell array 56 is an NMOS transistor connected in series between an output terminal io and a ground voltage GND and to which a digital signal db <0> corresponding to a gate and bias voltages vb1 and vb2 are applied, respectively. 72, 74, 76).

The operation of the DAC of the power amplifier according to the present invention configured as described above is as follows.

[Table 1] shows codes according to power supply voltage and corresponding DAC output range.

TABLE 1

power 2.7 2.8 2.9 3.0 3.1 3.2 3.3 3.4 3.5 3.6 3.7 3.8 3.9 4.0 4.1 4.2 code 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111 Output range 0.3 to 2.7 0.3 to 2.8 0.3 to 2.9 0.3 to 3.0 0.3 to 3.1 0.3 to 3.2 0.3 to 3.3 0.3 to 3.4 0.3 to 3.5 0.3 to 3.6 0.3 to 3.7 0.3 to 3.8 0.3 to 3.9 0.3 to 4.0 0.3 to 4.1 0.3 to 4.2

Table 1 summarizes the code values so that the maximum output voltage range is always set even when the supply voltage changes from 2.7 to 4.2V.

In addition, in order to cope with more change in power supply voltage, there are various applications such as increasing the number of bits of a code or increasing the interval of power supply voltage between codes.

For example, when the power supply voltage is 3.3V, the current that can flow in one current cell is 1.96uA.

And, if the 8-bit code is "00000000", all the current cells are turned on to flow 500uA of current.

This current generates an output voltage vout voltage-dropped by the resistor 48 of the voltage converter 30. That is, if the resistor 48 has a resistance value of 6K ?, a voltage drop of 3V occurs and the magnitude of the output voltage vout becomes 0.3V.

In addition, if the 8-bit code is "11111111", all current cells are turned off and a current of 0A flows.

The current does not generate a voltage drop due to the resistance 48 of the voltage converter 30, so that the output voltage vout becomes 3.3V.

The reason why the minimum value of the output voltage vout is set to 0.3V is because the bias circuit is designed such that the minimum value at which the lower end of the NMOS transistor of the current cell can be in the saturation region is 0.3V. to be.

On the other hand, when the power supply voltage is 2.7V, the unit current is 1.56uA, and when the power supply voltage is 3.6V, it is controlled by the bias circuit so that the output voltage range is 0.3V to the power supply voltage.

FIG. 7 is a graph illustrating a simulation of a change in an output voltage of a digital signal according to a power supply voltage in the DAC of the power amplifier shown in FIG. 1.

Referring to FIG. 7, when the power supply voltage is 2.7V, 3.3V, or 3.6V, the output voltage vout for the 8-bit digital signal d <0: 7> always ranges from 0.3V to the power supply voltage. It can be seen that it has.

As described above, the DAC of the power amplifier according to the present invention has the effect of automatically detecting the power supply voltage and automatically changing the output voltage range according to the change of the power supply voltage to always control the maximum output voltage range. .

In addition, the DAC of the power amplifier according to the present invention does not use an additional circuit for controlling the maximum output voltage has the effect of reducing the chip area and the resulting time and cost.

In addition, a preferred embodiment of the present invention is for the purpose of illustration, those skilled in the art will be able to various modifications, changes, substitutions and additions through the spirit and scope of the appended claims, such modifications and changes are the following claims It should be seen as belonging to a range.

Claims (8)

A power detector which compares the detection voltage detecting the level of the power supply voltage with a reference voltage and outputs trimming data obtained by converting the detected voltage into a code value corresponding to the power supply voltage; And A voltage generator which is controlled by an enable signal to generate a bias voltage according to the trimming data according to the reference voltage, and adjusts a current of the digital signal according to the bias voltage to generate an output voltage corresponding to the digital signal. Digital analog converter of a power amplifier comprising a. delete The method of claim 1, The power detector further comprises a voltage divider for dividing the power supply voltage at a constant ratio. The method of claim 1, wherein the power detector A level divider for dividing the reference voltage into a plurality of levels; A plurality of comparison units for comparing the corresponding level output from the level dividing unit with the power supply voltage, respectively; And And an encoder for generating the trimming data by encoding the comparison results output from the plurality of comparison units. The method of claim 1, wherein the voltage generator A bias generator which generates a bias voltage according to the trimming data; A plurality of current cell arrays including a plurality of current cells to adjust a current by a corresponding digital signal according to the bias voltage; And And a voltage converter converting currents output from the plurality of current cell arrays into voltages. The method of claim 5, wherein the bias generator is A self bias unit for generating a bias according to the enable signal; A current mirror controlled by an enable signal and generating the bias voltage in accordance with the trimming data; And And a current converter configured to drive the current mirror by comparing the power supply voltage with the reference voltage. The method of claim 6, And the current converter comprises an operational amplifier. The method of claim 5, And the current cell comprises a plurality of NMOS transistors connected in series between an output terminal and a ground voltage and to which a corresponding digital signal and a bias voltage are respectively applied to a gate.

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