KR100589487B1 - Semiconductor Device Manufacturing Method - Google Patents

Abstract

The present invention relates to a method for fabricating a semiconductor device for tensioning an electron transfer channel by forming a double gate spacer, comprising: stacking a secondary oxide film and a nitride film on a gate spacer on which a primary oxide film and a nitride film are formed, and etching the gate spacer. As a result of the step, the wet etching, and the silicide forming, the upper part of the pillar is compressed in the general gate spacer structure, and the lower part where the channel is located is tensioned to improve the mobility of the electron.

Double Gate Spacers, Electrophoretic Channels, Silicides, Transistors

Description

Semiconductor Device Manufacturing Method

1 is a cross-sectional view showing the structure of a conventional gate spacer,

2A through 2D are flowcharts illustrating a semiconductor device manufacturing process according to the present invention.

  Explanation of symbols on the main parts of the drawings

101p: Pillar 101: silicon substrate

110: primary spacer 111, 121: oxide film

112, 122: nitride film 120: secondary spacer

131: low concentration (n−) region 132: high concentration (n +) source / drain

140: channel 150: silicide film

160: gap

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a semiconductor device, and in particular, to form a double gate spacer to tension an electron transfer channel.

As the integration of semiconductor devices proceeds, the size of the semiconductor device is reduced and the channel length of the semiconductor device is also reduced. However, as the channel length of the semiconductor device is reduced, undesired electrical characteristics of the semiconductor device, for example, a short channel effect appear.

In order to solve the short channel effect, a vertical reduction such as a thickness of the gate insulating layer and a junction depth of a source / drain must be performed along with a horizontal reduction such as a reduction of the gate electrode length. In addition, the horizontal reduction and the vertical reduction reduce the voltage of the applied power supply, increase the doping concentration of the semiconductor substrate, and in particular, control the doping profile of the channel region should be efficiently performed.

However, since the size of a semiconductor device is being reduced but the operating power required by electronic products is not yet low, for example, in the case of an NMOS transistor, electrons injected from a source are accelerated severely in a high potential gradient state of the drain. Hot carriers are susceptible to fragile structures. Accordingly, a lightly doped drain (LDD) structure has been proposed to improve an NMOS transistor vulnerable to the hot carrier.

In the LDD transistor, a low concentration (n−) region is positioned between a channel and a high concentration (n +) source / drain, and the low concentration (n−) region buffers a high drain voltage around the drain junction to cause a sudden potential change. By not doing so, the generation of hot carriers is suppressed. As the manufacturing technology of high-density semiconductor devices has been studied, various techniques for manufacturing MOSFETs of LDD structures have been proposed. Among them, the LDD manufacturing method for forming spacers on the sidewalls of the gate electrode is the most typical method, and has been used in most mass production techniques to date.

1 is a cross-sectional view showing the structure of a conventional gate spacer.

As shown in FIG. 1, in the structure of the gate spacer 1, a spacer pattern is formed on the silicon substrate 10, and low concentration (n−) regions 21 are formed at left and right sides of the pillar 11, respectively. And a high concentration (n +) source / drain 22, a spacer 1 is formed on the left and right sides of the pillar 11, and the silicide 40 is formed on the top surface of the high concentration region 22 and the pillar 11. Is formed.

Even in the gate spacer having such a structure, an electrical characteristic such as an undesirable short channel effect of the semiconductor device is generated while the channel length of the semiconductor device is reduced.

The present invention is invented to solve the problems of the prior art as described above, to provide a semiconductor device manufacturing method for improving the mobility of electrons by tensioning the channel of the gate spacer to solve the short channel effect. There is a purpose.

In accordance with another aspect of the present invention, a method of manufacturing a semiconductor device includes stacking a secondary oxide film and a nitride film on a gate spacer on which a primary oxide film and a nitride film are formed, etching the gate spacer, and performing wet etching. Characterized in that it comprises a step and, forming a silicide.

Hereinafter, with reference to the accompanying drawings, preferred embodiments of a semiconductor device manufacturing method according to the present invention will be described in detail.

2A through 2D are flowcharts illustrating a semiconductor device manufacturing process according to the present invention.

As shown in FIG. 2A, the primary oxide film 111 and the primary nitride film 112 are stacked on the silicon substrate 101 having the pillars 101p formed thereon, and then dry-etched and ion implanted to form a low concentration (n−) region. 131 is formed between channel 140 and high concentration (n +) source / drain 132.

As shown in FIG. 2B, the secondary oxide layer 121 and the secondary nitride layer 122 are stacked on the device on which the primary spacer 110 is formed, and dry etching to form the secondary spacer 120. At this time, the thickness of the secondary oxide film 121 is the same as the thickness of the silicide film 150 which is subsequently advanced.

After the secondary spacers 120 are formed, the secondary oxide layer 121 under the secondary nitride layer 122 is removed as shown in FIG. 2B using wet etching. Then, the gap 160 is formed between the silicon substrate 101 and the nitride film 122.

In this state, as shown in FIG. 2C, the silicide film 150 is formed. The silicide layer 150 stacked as described above is filled between the silicon substrate 101 and the nitride layer 122, and the volume thereof expands. As the volume of the silicide layer 150 expands, the nitride layer 122 has a lower silicide layer. It is pressurized upward by the volume expansion of the membrane 150. At this time, the secondary spacer 120 corresponding to the top surface of the pillar 101p is formed with a space 170 by the loss of the oxide film 121 during the wet etching process, and the space 170 is formed of the nitride film 122. By providing the movable range of the nitride film 122 even when the pressure is moved upward, the nitride film 122 is in contact with the silicide film 150 laminated on the upper surface of the pillar 101p to avoid the stress of the silicide film 150. Can be.

Meanwhile, as shown in FIG. 2D, the nitride film 122 located at both sides of the pillar 101p moves upward, and the upper portion of the pillar 101p is compressed and compressed, but on the contrary, the lower silicide layer 150 is referred to. As a result, the silicon substrate 101, ie, the channel 140, beneath it is subjected to a tensile force.

As the channel 140 is stretched by the tensile force, the mobility of electrons is relatively improved compared to the untensioned channel.

As described in detail above, the semiconductor device manufacturing method of the present invention has an advantage in that the upper portion of the pillar is compressed in the general gate spacer structure and the lower portion in which the channel is positioned is tensioned to improve the mobility of electrons.

As such, the mobility of electrons is improved, and thus a semiconductor device having a high degree of integration can be manufactured while solving the short channel effect.

Although the technical idea of the method for manufacturing a semiconductor device of the present invention has been described with the accompanying drawings, this is for illustratively describing the best embodiments of the present invention and not for limiting the present invention.

Claims (1)

In the semiconductor device manufacturing method, Depositing and etching a gate oxide film and poly silicon on the semiconductor substrate to form a gate; Stacking a primary oxide layer and a primary nitride layer on the semiconductor substrate on which the gate is formed, and dry etching to form primary spacers on sidewalls of the gate; Forming a source / drain by ion implantation with the gate formed with the primary spacer interposed therebetween; Stacking and dry etching a secondary oxide layer and a secondary nitride layer on the semiconductor substrate to form secondary spacers on sidewalls of the gates on which the primary spacers are formed; Wet etching the semiconductor substrate to remove the secondary oxide layer under the secondary nitride layer; And Forming silicide on the gate and the source / drain.

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