CN111403284B - Fin type field effect transistor stress engineering optimization and manufacturing method thereof - Google Patents

Fin type field effect transistor stress engineering optimization and manufacturing method thereof Download PDF

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CN111403284B
CN111403284B CN202010145943.9A CN202010145943A CN111403284B CN 111403284 B CN111403284 B CN 111403284B CN 202010145943 A CN202010145943 A CN 202010145943A CN 111403284 B CN111403284 B CN 111403284B
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polysilicon layer
polysilicon
ion implantation
amorphous silicon
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CN111403284A (en
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鲍宇
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Shanghai Huali Integrated Circuit Manufacturing Co Ltd
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Shanghai Huali Integrated Circuit Manufacturing Co Ltd
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66787—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel
    • H01L29/66795—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66545—Unipolar field-effect transistors with an insulated gate, i.e. MISFET using a dummy, i.e. replacement gate in a process wherein at least a part of the final gate is self aligned to the dummy gate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/7842—Field effect transistors with field effect produced by an insulated gate means for exerting mechanical stress on the crystal lattice of the channel region, e.g. using a flexible substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/785—Field effect transistors with field effect produced by an insulated gate having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET

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  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Ceramic Engineering (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Manufacturing & Machinery (AREA)
  • Chemical & Material Sciences (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • Thin Film Transistor (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)

Abstract

The invention relates to a fin field effect transistor stress engineering optimization method and a fin field effect transistor manufacturing method, and relates to a semiconductor manufacturing technology.

Description

Fin type field effect transistor stress engineering optimization and manufacturing method thereof
Technical Field
The present invention relates to semiconductor manufacturing technologies, and in particular, to a method for optimizing stress engineering of a fin field effect transistor and a method for manufacturing a fin field effect transistor.
Background
In the field of semiconductor technology, the feature size of MOSFET transistors is continually shrinking in order to keep pace with moore's law. As the size of the semiconductor device is scaled down, the channel length of the device is shortened, the distance between the drain and the source is also shortened, and there is a problem that the threshold voltage is lowered as the channel length is reduced, the leakage current is increased, etc., that is, a short channel effect is generated in the semiconductor device.
The above challenges have led to the development of Fin Field effect transistors, i.e., finfets, for example, industry has begun to employ Fin Field effect transistor (FinFET, fin Field-Effect Transistor) structures at 14 nm. I.e., planar CMOS transistors transition to three-dimensional (3D) fin field effect transistor (Fin Field Effect Transistor, finFET) device structures. In the FinFET, the gate can control the ultrathin body from at least two sides, has much stronger gate-to-channel control capability than a planar MOSFET device, and can well inhibit short channel effect.
However, the performance of current finfet devices remains to be improved.
Disclosure of Invention
The invention provides a fin field effect transistor stress engineering optimization method, which comprises the following steps: s1: forming a fin structure on a semiconductor substrate; s2: depositing a first polysilicon layer, wherein the first polysilicon layer covers the upper surface of the semiconductor substrate and the upper surface and the side surface of the fin structure; s3: performing an ion implantation process on the first layer of polysilicon to form an amorphous silicon layer; s4: depositing a second polysilicon layer, wherein the second polysilicon layer covers the upper surface and the side surface of the amorphous silicon layer, then carrying out a planarization process on the second polysilicon layer, and forming a pseudo gate structure through a photoetching process; s5: and performing a high-temperature annealing process to convert the amorphous silicon into polycrystalline silicon.
Further, in step S1, a buried insulating layer is further formed on the semiconductor substrate, and then the fin structure is formed on the buried insulating layer.
Further, in step S2, the thickness of the first polysilicon layer is greater than 10nm.
Further, in step S3, the ion-implanted material of the ion implantation process is Ge or Ar.
Further, in step S3, an ion implantation depth of the ion implantation process is less than or equal to a thickness of the first layer of polysilicon.
Further, in step S4, the planarization process is a chemical mechanical polishing process.
Further, in step S5, the annealing temperature of the high temperature annealing process is greater than 600 ℃.
Further, in step S5, the atmosphere of the high temperature annealing process is an inert gas atmosphere.
Further, in step S5, the annealing time of the high temperature annealing process is longer than 1S.
The invention also provides a manufacturing method of the fin field effect transistor, which comprises the following steps: s1: forming a fin structure on a semiconductor substrate; s2: depositing a first polysilicon layer, wherein the first polysilicon layer covers the upper surface of the semiconductor substrate and the upper surface and the side surface of the fin structure; s3: performing an ion implantation process on the first layer of polysilicon to form an amorphous silicon layer; s4: depositing a second polysilicon layer, wherein the second polysilicon layer covers the upper surface and the side surface of the amorphous silicon layer, then carrying out a planarization process on the second polysilicon layer, and forming a pseudo gate structure through a photoetching process; s5: performing a high-temperature annealing process to convert the amorphous silicon into polycrystal; s6: depositing an interlayer dielectric layer and carrying out a planarization process; s7: and removing the pseudo gate structure, and forming a metal gate in the removed region of the pseudo gate structure.
Further, in step S2, the thickness of the first polysilicon layer is greater than 10nm.
Further, in step S3, the ion-implanted material of the ion implantation process is Ge or Ar.
Further, in step S3, an ion implantation depth of the ion implantation process is less than or equal to a thickness of the first layer of polysilicon.
In step S5, the annealing temperature of the high temperature annealing process is greater than 600 ℃, the atmosphere is inert gas atmosphere, and the annealing time is greater than 1S.
Further, the fin field effect transistor is an NMOS transistor.
According to the fin field effect transistor stress engineering optimization method and the fin field effect transistor manufacturing method, in the post gate process of the fin field effect transistor, the pseudo gate structure of the double-layer structure comprising amorphous silicon and polycrystalline silicon is formed through the ion implantation process, the amorphous silicon is annealed, the volume expansion generates compressive stress, the fin structure is extruded in the vertical direction, and therefore the performance of the fin field effect transistor is improved.
Drawings
Fig. 1 is a flowchart of a finfet stress engineering optimization method according to an embodiment of the invention.
Fig. 2a-2f are schematic diagrams illustrating a process of a finfet stress engineering optimization method according to an embodiment of the invention.
Fig. 3 is a schematic diagram illustrating a process of fabricating a finfet in accordance with an embodiment of the present invention.
Detailed Description
The following description of the embodiments of the present invention will be made more apparent and fully hereinafter with reference to the accompanying drawings, in which some, but not all embodiments of the invention are shown. All other embodiments, which can be made by those skilled in the art based on the embodiments of the invention without making any inventive effort, are intended to be within the scope of the invention.
In an embodiment of the invention, a method for optimizing stress engineering of a finfet is provided. Specifically, referring to fig. 1, fig. 1 is a flowchart illustrating a method for optimizing stress engineering of a finfet according to an embodiment of the invention. Referring to fig. 2a-2f, fig. 2a-2f are schematic diagrams illustrating a process of a stress engineering optimization method for a finfet according to an embodiment of the invention. The fin field effect transistor stress engineering optimization method of the embodiment of the invention comprises the following steps: s1: forming a fin structure on a semiconductor substrate; s2: depositing a first polysilicon layer, wherein the first polysilicon layer covers the upper surface of the semiconductor substrate and the upper surface and the side surface of the fin structure; s3: performing an ion implantation process on the first layer of polysilicon to form an amorphous silicon layer; s4: depositing a second polysilicon layer, wherein the second polysilicon layer covers the upper surface and the side surface of the amorphous silicon layer, then carrying out a planarization process on the second polysilicon layer, and forming a pseudo gate structure through a photoetching process; s5: and performing a high-temperature annealing process to convert the amorphous silicon into polycrystalline silicon.
More specifically, the method for optimizing the stress engineering of the fin field effect transistor according to an embodiment of the present invention includes:
s1: a fin structure is formed on a semiconductor substrate.
Referring specifically to fig. 2a, a fin structure 120 is formed on a semiconductor substrate 100.
In an embodiment of the present invention, a Buried OXide (BOX) is further formed on the semiconductor substrate 100, and then the fin structure 120 is formed on the Buried OXide.
S2: a first polysilicon layer is deposited, the first polysilicon layer covering an upper surface of the semiconductor substrate and upper surfaces and sides of the fin structure.
Referring specifically to fig. 2b, a first polysilicon layer 130 is deposited, and the first polysilicon layer 130 covers the upper surface of the semiconductor substrate 100 and the upper surface and sides of the fin structure 120.
In an embodiment of the present invention, preferably, the thickness of the first polysilicon layer is greater than 10nm.
S3: and carrying out an ion implantation process on the first layer of polysilicon to form an amorphous silicon layer.
Referring to fig. 2c, an ion implantation process is performed on the first polysilicon layer 130 to form an amorphous silicon layer 131.
In an embodiment of the present invention, preferably, the ion-implanted material of the ion implantation process is Ge or Ar. However, the present invention is not limited to these two materials, and any material that can perform an ion implantation process on polysilicon to form amorphous silicon may be used.
In an embodiment of the present invention, the ion implantation depth of the ion implantation process is less than or equal to the thickness of the first layer of polysilicon 130, i.e., the fin structure 120 is not contacted by ion implantation.
S4: and depositing a second polysilicon layer, wherein the second polysilicon layer covers the upper surface and the side surface of the amorphous silicon layer, then carrying out a planarization process on the second polysilicon layer, and forming a pseudo gate structure through a photoetching process.
Referring to fig. 2d and fig. 2e specifically, a second polysilicon layer 141 is deposited, the second polysilicon layer 141 covers the upper surface and the side surface of the amorphous silicon layer 131, and then a planarization process is performed on the second polysilicon layer, and a dummy gate structure 140 is formed through a photolithography etching process.
In an embodiment of the present invention, the planarization process is a chemical mechanical polishing process.
S5: and performing a high-temperature annealing process to convert the amorphous silicon into polycrystalline silicon.
Referring to fig. 2f specifically, a high temperature annealing process is performed to convert the amorphous silicon layer 131 into polycrystallization, and the volume expansion generates compressive stress, so as to squeeze the fin structure 120 to provide stress, thereby improving mobility of carriers or holes and performance of the finfet.
In an embodiment of the present invention, the annealing temperature of the high temperature annealing process is greater than 600 ℃.
In an embodiment of the present invention, the atmosphere of the high temperature annealing process is an inert gas atmosphere.
In an embodiment of the present invention, the annealing time of the high temperature annealing process is greater than 1s.
In an embodiment of the present invention, a method for fabricating a finfet is further provided, and in particular, referring to fig. 3, fig. 3 is a schematic diagram illustrating a process of fabricating a finfet according to an embodiment of the present invention, where the method further includes, based on the above-mentioned method for optimizing stress engineering of a finfet:
s6: and depositing an interlayer dielectric layer and carrying out a planarization process.
Referring specifically to fig. 3, an interlayer dielectric layer 150 is deposited and planarized.
S7: and removing the pseudo gate structure, and forming a metal gate in the removed region of the pseudo gate structure.
In an embodiment of the present invention, the finfet is an NMOS transistor.
In summary, in the back gate process of the fin field effect transistor, the dummy gate structure including the double-layer structure of amorphous silicon and polysilicon is formed by the ion implantation process, and the annealing volume expansion of amorphous silicon generates compressive stress, so as to squeeze the fin structure in the vertical direction, thereby improving the performance of the fin field effect transistor.
Finally, it should be noted that: the above embodiments are only for illustrating the technical solution of the present invention, and not for limiting the same; although the invention has been described in detail with reference to the foregoing embodiments, it will be understood by those of ordinary skill in the art that: the technical scheme described in the foregoing embodiments can be modified or some or all of the technical features thereof can be replaced by equivalents; such modifications and substitutions do not depart from the spirit of the invention.

Claims (14)

1. The fin field effect transistor stress engineering optimization method is characterized by comprising the following steps of:
s1: forming a fin structure on a semiconductor substrate;
s2: depositing a first polysilicon layer, wherein the first polysilicon layer covers the upper surface of the semiconductor substrate and the upper surface and the side surface of the fin structure;
s3: performing an ion implantation process on the first layer of polysilicon to form an amorphous silicon layer;
s4: depositing a second polysilicon layer, wherein the second polysilicon layer covers the upper surface and the side surface of the amorphous silicon layer, then carrying out a planarization process on the second polysilicon layer, and forming a pseudo gate structure through a photoetching process; and
s5: and performing a high-temperature annealing process to convert the amorphous silicon into polycrystal, wherein the annealing temperature is higher than 600 ℃.
2. The method of claim 1, further comprising forming a buried insulating layer on the semiconductor substrate and then forming the fin structure on the buried insulating layer in step S1.
3. The method of claim 1, wherein in step S2, the thickness of the first polysilicon layer is greater than 10nm.
4. The method according to claim 1, wherein in step S3, the ion implanted material of the ion implantation process is Ge or Ar.
5. The method according to claim 1, wherein in step S3, the ion implantation depth of the ion implantation process is less than or equal to the thickness of the first layer polysilicon.
6. The method according to claim 1, wherein in step S4, the planarization process is a chemical mechanical polishing process.
7. The method according to claim 1, wherein in step S5, the atmosphere of the high temperature annealing process is an inert gas atmosphere.
8. The method of claim 1, wherein in step S5, the annealing time of the high temperature annealing process is greater than 1S.
9. A method of fabricating a fin field effect transistor, comprising:
s1: forming a fin structure on a semiconductor substrate;
s2: depositing a first polysilicon layer, wherein the first polysilicon layer covers the upper surface of the semiconductor substrate and the upper surface and the side surface of the fin structure;
s3: performing an ion implantation process on the first layer of polysilicon to form an amorphous silicon layer;
s4: depositing a second polysilicon layer, wherein the second polysilicon layer covers the upper surface and the side surface of the amorphous silicon layer, then carrying out a planarization process on the second polysilicon layer, and forming a pseudo gate structure through a photoetching process;
s5: performing a high-temperature annealing process to convert the amorphous silicon into polycrystal, wherein the annealing temperature is higher than 600 ℃;
s6: depositing an interlayer dielectric layer and carrying out a planarization process; and
s7: and removing the pseudo gate structure, and forming a metal gate in the removed region of the pseudo gate structure.
10. The method of manufacturing a finfet in accordance with claim 9, wherein in step S2, a thickness of said first polysilicon layer is greater than 10nm.
11. The method according to claim 9, wherein in the step S3, the ion-implanted material of the ion implantation process is Ge or Ar.
12. The method according to claim 9, wherein in the step S3, the ion implantation depth of the ion implantation process is less than or equal to the thickness of the first layer polysilicon.
13. The method of manufacturing a finfet in accordance with claim 9, wherein in step S5, the atmosphere is an inert gas atmosphere, and the annealing time is greater than 1S.
14. The method of claim 9, wherein the finfet is an NMOS transistor.
CN202010145943.9A 2020-03-05 2020-03-05 Fin type field effect transistor stress engineering optimization and manufacturing method thereof Active CN111403284B (en)

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Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN103854987A (en) * 2012-12-04 2014-06-11 中芯国际集成电路制造(上海)有限公司 Dummy gate forming method, silicon selective deposition method and plug forming method
CN103855022A (en) * 2012-12-04 2014-06-11 中芯国际集成电路制造(上海)有限公司 Forming method of fin-type field effect transistor
CN104701234A (en) * 2015-03-16 2015-06-10 上海华力微电子有限公司 Manufacturing method of semiconductor device
CN104821277A (en) * 2014-01-30 2015-08-05 中芯国际集成电路制造(上海)有限公司 Method for forming transistor
CN106328538A (en) * 2015-06-30 2017-01-11 意法半导体公司 A self-aligned SiGe FinFET

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN103854987A (en) * 2012-12-04 2014-06-11 中芯国际集成电路制造(上海)有限公司 Dummy gate forming method, silicon selective deposition method and plug forming method
CN103855022A (en) * 2012-12-04 2014-06-11 中芯国际集成电路制造(上海)有限公司 Forming method of fin-type field effect transistor
CN104821277A (en) * 2014-01-30 2015-08-05 中芯国际集成电路制造(上海)有限公司 Method for forming transistor
CN104701234A (en) * 2015-03-16 2015-06-10 上海华力微电子有限公司 Manufacturing method of semiconductor device
CN106328538A (en) * 2015-06-30 2017-01-11 意法半导体公司 A self-aligned SiGe FinFET

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