KR100589383B1 - Clock control device and light emitting display device using the control device - Google Patents

Abstract

The present invention relates to a clock control device and a light emitting display device using the same.

The present invention includes a panel in which pixel circuits are formed in an area where a data line and a scan line intersect, and first and second scan drivers respectively formed on both sides of the panel to supply a scan signal to the scan line. The clock controller provides first and second clock signals for driving to the first and second scan drivers, respectively. Here, the first clock signal is the same as the second clock signal.

According to the present invention, as the clock signals for driving the respective driving units are synchronized in the dual driving type light emitting display device, malfunction of the driving unit is prevented.

Organic EL, Clock Signal, Synchronization, Dual Drive

Description

Clock control device and light emitting display device using the same {CLOCK CONTROL DEVICE AND LIGHT EMITTING DISPLAY DEVICE USING THE CONTROL DEVICE}

1 is a schematic plan view of a light emitting display device according to a first embodiment of the present invention.

FIG. 2 is a structural diagram of a clock controller and a scan driver shown in FIG. 1.

3 is a waveform diagram of a clock signal according to an exemplary embodiment of the present invention.

4 is a schematic plan view of a light emitting display device according to a second embodiment of the present invention.

5 is a schematic plan view of a light emitting display device according to a third embodiment of the present invention.

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a light emitting display device, and more particularly, to a clock control device and an organic electroluminescent display device using the same.

In general, an organic EL display device is a display device for electrically exciting a fluorescent organic compound to emit light, and is capable of displaying an image by voltage driving or current driving M × N organic light emitting cells. The organic light emitting cell has a structure of an anode (ITO), an organic thin film, and a cathode layer (metal). The organic thin film has a multilayer structure including an emission layer (EML), an electron transport layer (ETL), and a hole transport layer (HTL) in order to improve the emission efficiency by improving the balance between electrons and holes. It also includes a separate electron injection layer (EIL) and a hole injection layer (HIL).

As such a method of driving the organic light emitting cell, there are a simple matrix method and an active matrix method using a thin film transistor (TFT). In the simple matrix method, the anode and the cathode are orthogonal and the line is selected and driven, whereas the active driving method connects the thin film transistors to each indium tin oxide (ITO) pixel electrode and the capacitance of the capacitor connected to the gate of the thin film transistor. Is driven according to the maintained voltage. In this case, the active driving method is divided into a voltage driving method and a current driving method according to the type of the signal applied to set the voltage to the capacitor.

In the conventional organic EL display device, pixels are formed in an area where the data line and the scan line cross each other, and each pixel is selected according to a signal applied from the scan line and then emits light according to display information applied through the data line. On the display panel of the organic EL display device, a plurality of pixels operating as described above are connected to the scan line. As the distance from the scan driver increases, the signal output from the scan driver is distorted by the resistance component on the scan line.

To this end, scan driving units are provided on both sides of the display panel based on the display panel, and a dual driving method is used to prevent the signal from being distorted and the luminance difference between the pixels as the distance from the scan driver increases.

By the way, in the dual drive type organic EL display device, when the operation of each scan driver is not synchronized, noise is generated or accurate image reproduction is not performed.

SUMMARY OF THE INVENTION The present invention has been made in an effort to solve a conventional problem and to synchronize clock signals for driving each driving unit in a dual driving type light emitting display device.

In accordance with one aspect of the present invention, a light emitting display device includes a plurality of data lines that transmit data signals and are formed in one direction, a plurality of scan lines that transmit scan signals and cross the data lines, and the scan lines. A display panel each formed in the intersecting pixel region and including a plurality of pixel circuits for displaying an image corresponding to an applied data signal; A data driver supplying a data signal to the data line; First and second scan drivers respectively formed on both sides of the display panel and respectively operated according to first and second clock signals applied to supply the scan signals to the scan lines; And a clock controller configured to synchronize the first and second clock signals to supply the first and second clock signals to the first and second scan drivers.

Here, the data driver may be configured as first and second data drivers respectively operating according to the third and fourth clock signals applied to supply data signals to the data lines.

In this case, the clock controller may include: a first clock controller configured to synchronize the first and second clock signals to supply the first and second scan drivers; And a second clock controller configured to synchronize the third and fourth clock signals to supply the first and second data drivers.

On the other hand, the clock control unit includes a first buffer for buffering the basic clock signal applied from the outside; A second buffer for buffering the base clock signal applied from the outside; A first calculation unit configured to perform an OR operation on the basic clock signal output from the first buffer and the applied main clock signal to output one clock signal; And a second operation unit configured to perform an OR operation on the basic clock signal output from the second buffer and the applied main clock signal to output another clock signal.

In this case, the first and second scan drivers may include a shift register configured to shift a scan signal applied by operating in accordance with the first and second clock signals; An arithmetic operation configured to perform an NOR operation on the shifted and output scan signal; And a buffer for buffering the scan signal output from the calculator and supplying the scan signal to the scan line of the display panel.

According to another aspect of the present invention, a clock control apparatus includes a scan driver supplying a scan signal to the scan line on a panel on which a pixel circuit is formed in an area where the data line and the scan line intersect, and a data driver supplying a data signal to the data line. And at least one of the scan driver and the data driver has a dual shape, the clock control device comprising: a first buffer configured to buffer a basic clock signal applied from the outside; A second buffer for buffering the base clock signal applied from the outside; A first calculator configured to perform an OR operation on the basic clock signal output from the first buffer and the applied main clock signal to output the first clock signal; And a second calculator configured to perform an OR operation on the basic clock signal output from the second buffer and the applied main clock signal to output the second clock signal as a second clock signal. The first clock signal and the second clock signal may be in a dual driving form. Inputs are made to the driving units respectively.

In the present invention having such a feature, the first and second clock signals may be the same signal.

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings so that those skilled in the art may easily implement the present invention. As those skilled in the art would realize, the described embodiments may be modified in various different ways, all without departing from the spirit or scope of the present invention.

In the drawings, parts irrelevant to the description are omitted in order to clearly describe the present invention. Like parts are designated by like reference numerals throughout the specification. When a part is connected to another part, this includes not only a directly connected part but also an electrically connected part with another element in between.

A light emitting display device, a pixel circuit, and a driving method thereof according to an exemplary embodiment of the present invention will now be described in detail with reference to the accompanying drawings. The light emitting display device described below is an organic light emitting display device having an organic light emitting cell, but the light emitting display device according to the present invention is not limited thereto.

First, a light emitting display device according to an exemplary embodiment will be described in detail with reference to FIG. 1. 1 is a schematic plan view of a light emitting display device according to an exemplary embodiment of the present invention.

As shown in FIG. 1, the light emitting display device according to the exemplary embodiment of the present invention includes an organic EL display panel (hereinafter, referred to as a display panel 100), a data driver 200, a first scan driver 300, and a second scan. The driving unit 400 is included.

The display panel 100 includes a plurality of data lines Y ₁ -Y _n extending in a row direction, a plurality of scanning lines X ₁ -X _m extending in a column direction, and a plurality of pixel circuits 110. The pixel circuit 110 is formed in the pixel region defined by the data lines Y ₁ -Y _n and the scanning lines X ₁ -X _m .

The data driver 200 applies a data current I _DATA to the data lines Y ₁ -Y _n . The first scan driver 300 sequentially applies a scan signal for selecting a pixel circuit to the scan lines X ₁ -X _m , and the second scan driver 400 also scans the scan lines X ₁ -X _m . Are applied sequentially. In particular, the first and second scan drivers 300 and 400 operate according to the applied clock signal to apply the scan signal to the corresponding scan line. Here, the scan signal may be one or more. For example, the scan signal may be classified into a scan signal for selecting a pixel and a scan signal for emitting light of the pixel.

The clock controller 500 supplies the clock signals synchronized to the first and second scan drivers 300 and 400, respectively.

2 illustrates a structure of a clock controller and a scan driver according to an exemplary embodiment of the present invention.

The clock control unit 500 according to an exemplary embodiment of the present invention may include first and second buffers 510 and 530 which respectively receive first and second basic clock signals C1 and C2 provided from a controller or a clock generator, not shown. ) And the first and second calculators 520 and 540 for performing an OR operation on the signal output from the first buffer 510 and the main clock signal MCLK (for example, provided from the clock generator). Is done. The signal output from the first calculator 520 is the first clock signal CLK1 provided to the first scan driver 300, and the signal output from the second calculator 540 is the second scan driver 400. The second clock signal CLK2 is provided.

As shown in FIG. 2, the first and second scan drivers 300 and 400 respectively driven according to the first and second clock signals applied from the clock control unit 500 having such a structure include the input clock signals CLK1, Shift registers 310 and 410 for shifting the scan signal (provided from the controller) applied by operating in accordance with CLK2), and outputs from the arithmetic units 320 and 420 and the arithmetic units 320 and 4210 to perform an NOR operation on the shifted output scan signal. And buffers 330 and 430 which buffer the scanned signal to be supplied to the scan line of the display panel 100. For convenience of explanation, the clock signals before the synchronization process are respectively referred to as the "first basic clock signal" and the "second basic clock signal", and the synchronized clock signals are referred to as the "first clock signal" and the "second clock signal," respectively. Clock signal ". In the embodiment of the present invention, the synchronization of signals indicates that two clock signals are output at the same timing with the same period.

Meanwhile, the first scan driver 300, the second scan driver 400, and / or the data driver 200 may be electrically connected to the display panel 100 or may be bonded to the display panel 100 and electrically connected to the display panel 100. The tape carrier package (TCP) may be mounted in the form of a chip. Alternatively, a flexible printed circuit (FPC) or a film, which is bonded to the display panel 100 and electrically connected to the display panel 100, may be mounted in the form of a chip or the like, which is referred to as a chip on film (COF) method. do. Alternatively, the first scan driver 300, the second scan driver 400, and / or the data driver 200 may be directly mounted on the glass substrate of the display panel, which is called a chip on glass (COG) method. It may also be replaced with a drive circuit formed on the glass substrate in the same layers as the scan line, data line and thin film transistor. In addition, the clock controller 500 may be mounted on the display panel according to the COG method or on a control printed circuit board on which a controller (not shown) is mounted.

Next, the operation of the light emitting display device in the exemplary embodiment of the present invention will be described based on the structure.

The basic clock signals Cl and C2 generated from the controller mounted on the control printed circuit board or the clock generator are input to the clock controller 500, respectively.

The first and second buffers 510 and 530 of the clock controller 500 buffer the input first and second basic clock signals Cl and C2, respectively. After being buffered, the first and second basic clock signals Cl and C2 are input to the first and second calculators 520 and 540, respectively.

The first calculator 520 performs a rational operation on the input first basic clock signal C1 and the input main clock signal MCLK and outputs the result. A high level signal is output only when the first basic clock signal C1 and the main clock signal MCK are at high levels according to the OR operation, and the first basic clock signal C1 and the main clock signal MCLK are output. In case of different levels or low levels, low level signals are output. According to the operation, the first basic clock signal C1 may be output as the first clock signal CLK1 by varying an output level according to the main clock signal MCLK. The second basic clock signal C2 is also processed by the second calculator 540 and output as the second clock signal CLK2 in the same manner as the first basic clock signal C1. 3 illustrates first and second clock signals CLK1 and CLK2 according to an exemplary embodiment of the present invention which are processed and output as described above.

As described above, the first and second clock signals CLK1 and CLK2 having the same output timing, period, or the like adjusted according to the same main clock signal are respectively the first scan driver 300 and the second scan driver 400. ) Is entered.

The first and second scan drivers 300 and 400 operate according to the input first and second clock signals CLK1 and CLK2, respectively. The scan signals provided from the controller are sequentially output on the scan lines of the display panel 100.

Thereafter, the pixel circuit 110 of the display panel 100 selected according to the scan signal emits light according to the data signal from the data driver 200.

In the light emitting display device operating as described above, as clock signals input to the first and second scan drivers 300 and 400 are synchronized, noise of the signal is removed and malfunctions are prevented.

Meanwhile, the above-described first embodiment has been described based on a light emitting display device in which the scan driver is positioned on both sides of the display panel, respectively, to dual drive the scan lines. However, the data driver is disposed on the upper and lower sides of the display panel. The clock control unit as described above can also be applied to a light emitting display device which is positioned so that each data driver supplies a data signal to the upper and lower portions of the display panel, respectively.

4 is a schematic structural diagram of a light emitting display device according to a second embodiment of the present invention.

The light emitting display device according to the second embodiment of the present invention includes a display panel 100 having the same structure as that of the first embodiment. Unlike the first embodiment, one scan driver 300 is provided. And two data drivers 210 and 220.

As shown in FIG. 4, the data driver includes first and second data drivers 210 and 220 formed on upper and lower sides of the display panel 100, respectively. In this case, the data lines are separated with respect to a predetermined reference line. For example, when the display panel is divided into upper and lower parts based on the predetermined reference line, the first data driver 210 supplies a data signal to the upper part of the display panel. The second data driver 220 supplies a data signal under the display panel. In this case, the scan driver 300 may be divided into two scan drivers corresponding to the upper and lower portions of the display panel, but one scan driver 300 may supply the scan signals to the corresponding scan lines on the upper and lower portions of the panel, respectively.

As such, when the data driver includes dual data drivers (first and second data drivers), the display panel is generally divided into upper and lower parts, and accordingly, the first data driver 210 and the second data driver ( 220 must be driven at the same timing. To this end, as in the above embodiment, the clock control unit 500 is formed to synchronize and output the clock signal provided from the controller, and the clock signals synchronized through the clock control unit 500 are respectively the first data driver 210. ) And the second data driver 220.

Accordingly, the first and second data drivers 210 and 220 are properly synchronized, so that the image display device can be stably operated.

On the other hand, unlike the second embodiment, the scan driver includes a first scan driver and a second scan driver formed on both sides of the display panel as in the first embodiment, and the data driver includes the second driver. As shown in the example, the clock control unit according to the exemplary embodiment of the present invention may also be applied to a dual driving light emitting display device including a first data driver and a second data driver formed on the display panel.

5 illustrates a structure of a light emitting display device according to a third embodiment of the present invention.

As shown in FIG. 5, in the light emitting display device including the display panel 100, the first and second scan drivers 300 and 400, and the first and second data drivers 210 and 220, first and second scans may be used. The first clock controller 510 for controlling the clock signals input to the drivers 300 and 400 and the second clock controller 520 for controlling the clock signals input to the first and second data drivers 210 and 220 are respectively formed. can do. The structures of the first and second clock controllers 510 and 520 may be configured as shown in FIG. 2. Here, since the operations of the first and second clock controllers 510 and 520 are the same as those of the first embodiment, detailed description thereof will be omitted.

Even in a light emitting display device having a dual scan driver and a data driver, the clock signals supplied to the scan driver and the data driver are synchronized, thereby stably operating the light emitting display device.

Although the preferred embodiments of the present invention have been described in detail above, the scope of the present invention is not limited thereto, and various modifications and improvements of those skilled in the art using the basic concepts of the present invention defined in the following claims are also provided. It belongs to the scope of rights.

As described above, according to the present invention, as the clock signals input to the respective driving units are the same in various types of dual driving type light emitting display devices, noise of the signal is removed and the operation of the driving unit is performed stably, thereby making it possible to accurately correct the light emitting display device. Image reproduction is performed.

Claims (6)

A plurality of data lines which transmit data signals and are formed in one direction; A display panel including a plurality of scan lines that transmit a scan signal and intersect the data lines, and a plurality of pixel circuits respectively formed in pixel regions where the scan lines intersect, and which display an image corresponding to an applied data signal; ; A data driver supplying a data signal to the data line; First and second scan drivers respectively formed on both sides of the display panel and respectively operated according to first and second clock signals applied to supply the scan signals to the scan lines; And A clock control unit configured to synchronize the first and second clock signals and supply the first and second clock signals to the first and second scan drivers; A light emitting display device comprising a. The method of claim 1 The data driver is composed of first and second data drivers respectively operating according to the third and fourth clock signals applied to supply data signals to the data lines. The clock controller may include: a first clock controller configured to synchronize the first and second clock signals to supply the first and second scan drivers; A second clock controller configured to synchronize the third and fourth clock signals to supply the first and second data drivers; A light emitting display device comprising a. The method according to claim 1 or 2 The clock control unit A first buffer for buffering a basic clock signal applied from the outside; A second buffer for buffering the base clock signal applied from the outside; A first calculation unit configured to perform an OR operation on the basic clock signal output from the first buffer and the applied main clock signal to output one clock signal; And A second operation unit configured to perform an OR operation on the basic clock signal output from the second buffer and the applied main clock signal to output another clock signal; A light emitting display device comprising a. The method of claim 1 The first and second scan driver A shift register configured to shift the scanning signal applied by operating in response to the first and second clock signals; An arithmetic operation configured to perform an NOR operation on the shifted and output scan signal; And A buffer that buffers the scan signal output from the calculator and supplies the scan signal to the scan line of the display panel. A light emitting display device comprising a. A scan driver for supplying a scan signal to the scan line on the panel on which the pixel circuit is formed, and a data driver for supplying a data signal to the data line in an area where the data line and the scan line cross each other; and at least one of the scan driver and the data driver. In the clock control device of the light emitting display device having a dual form, A first buffer for buffering a basic clock signal applied from the outside; A second buffer for buffering the base clock signal applied from the outside; A first calculator configured to perform an OR operation on the basic clock signal output from the first buffer and the applied main clock signal to output the first clock signal; And A second operation unit configured to perform an OR operation on the basic clock signal output from the second buffer and the applied main clock signal to output the second clock signal; And the first clock signal and the second clock signal are respectively input to a driving unit having a dual driving form. The method of claim 5 And the first and second clock signals are the same signal.

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