KR100588266B1 - Method of depositing amorphous silicon based films having controlled conductivity - Google Patents

Abstract

The present invention relates to a deposition method for producing an amorphous silicon based thin film having controlled resistance and low stress. Such thin films can be used as intermediate layers in FED fabrication. Such thin films can also be used in other electronic devices that require thin films with controlled resistance in the range between the insulator and the resistance of the conductor. The deposition method described in the present invention applies a chemical vapor deposition method or a plasma enhanced chemical vapor deposition method, and other deposition techniques such as a physical vapor deposition method may be applied. In one embodiment, the amorphous silicon-based thin film comprises a silicon-based volatile, a conductivity increasing volatile comprising one or more components to increase the conductivity of the amorphous silicon-based thin film, and one or more components to reduce the conductivity of the amorphous silicon-based thin film into the deposition chamber. It is formed by introducing a conductive reducing volatile containing.

Description

Method for Deposition of Amorphous Silicon Thin Films with Controlled Conductivity {METHOD OF DEPOSITING AMORPHOUS SILICON BASED FILMS HAVING CONTROLLED CONDUCTIVITY}

1 is a schematic cross-sectional view of a plasma enhanced chemical vapor deposition chamber in which a method according to the invention may be performed.

2 is an enlarged cross-sectional view of a typical field emission display device.

3 is a graph showing the dependence of the resistance on the flow rate ratio between PH ₃ and NH ₃ .

4 is a graph showing the dependence of the stress on the flow rate ratio between PH ₃ and NH ₃ .

5 is a graph showing the resistance of an amorphous silicon-based thin film with respect to the flow ratio of hydrogen phosphide: methane.

Explanation of symbols on the main parts of the drawings

10: plasma enhanced chemical vapor deposition apparatus

12 deposition chamber 16 gas inlet manifold (first electrode)

18: susceptor (second electrode) 22: bottom wall (of the deposition chamber)

24: lift-off plate 26: lift-off pin

28: hole 30: gas outlet

32: side wall (of the deposition chamber) 36: RF source

38: substrate 50: field emission display device

52: resistive layer 54: glass substrate

56: insulating layer 58: metal gate layer

60: metal microtip

This application is filed on July 11, 1995, entitled "METHOD OF DEPOSITING AMORPHOUS SILICON BASED FILMS HAVING CONTROLLED CONDUCTIVITY". As part of a continuous application of 08 / 500,728, this is incorporated herein by reference.

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention generally relates to a method for depositing an amorphous silicon based thin film having a controlled conductivity on a substrate, and more particularly to controlling the conductivity between the conductivity of intrinsic amorphous silicon and the conductivity of n ⁺ doped amorphous silicon. It relates to a method of depositing an amorphous silicon-based thin film having a predetermined conductivity. Such thin films may be deposited onto a substrate by a chemical vapor deposition process. Recently, flat panel display devices have been developed for use in many electronic fields, including notebooks. As one of such devices, an active matrix liquid crystal display device has been frequently used. However, such liquid crystal displays have inherent problems that are inadequate in many fields. For example, a liquid crystal display has a manufacturing problem in that the process of depositing amorphous silicon on glass is slow, the manufacturing process is complicated, and the yield is low. Such liquid crystal displays require power-consuming fluorescent backlights, and much of the light is wasted. Liquid crystal display images are also difficult to identify in bright daylight or at large viewing angles, which has become a major concern in many fields.

More recently developed field emission displays (FEDs) overcome some of these problems and provide advantages over liquid crystal display devices. For example, field emission displays have a high contrast ratio, large viewing angles, high maximum brightness, low power consumption, and a wide operating temperature range compared to typical thin film transistor liquid crystal display devices.

Unlike liquid crystal displays, field emission displays generate their own light using colored phosphors. Field emission displays do not require complex power-consuming backlights and filters, and users can see almost all the light generated by the field emission display. Field emission displays do not require large thin film transistor arrays. Thus, the main problem of the yield of the active matrix liquid crystal display is solved.

In field emission displays, electrons are emitted from the cathode and collide with the fluorescent material behind the transparent faceplate to form an image. This cathodic emission process is one of the most efficient ways to generate light. Unlike conventional CRTs, each pixel in a field emission display has its own electron source, that is, an array of emitting microtips. The voltage difference between the cathode and the gate extracts electrons from the cathode and accelerates the electrons toward the fluorescent material. The emission current and thus the display brightness strongly depends on the work function of the emitting material. Thus, the cleanliness and uniformity of the emitter source material is indispensable.

Most field emission displays are discharged at low pressure, ie 10 ⁻⁷ Torr, providing a long average free path for emitting electrons and preventing tip contamination and deterioration. The resolution of the display is improved by aiming electrons emitted from the microtip using a focus grid.

The first field emission cathode developed for the display device used a metal microtip emitter made of molybdenum. In such a device, the silicon wafer is first oxidized to form a thick SiO ₂ layer, and then a metal gate layer is deposited on top of the oxide. Thereafter, the gate layer is patterned to form a gate hole. The etching of SiO ₂ under the hole cuts the bottom of the gate to form a well. Molybdenum is then deposited at a vertical angle of incidence, and at the same time a sacrificial material, such as nickel (Ni), is deposited from a source located on the device side so that a cone with pointed points grows inside the cavity. The emitter cone remains when the sacrificial layer is removed.

In other field emission display devices, silicon microtip emitters are formed by thermally oxidizing a silicon substrate, patterning the silicon oxide to expose the underlying silicon substrate, and selectively etching the exposed silicon to form a silicon tip. In addition, oxidation and etching protects the silicon and sharpens the tip of the silicon tip.

In another design, the microtip is added on a substrate of a desired material, such as glass, which is an ideal substrate material for large area flat panel displays. The microtip can be made of a conductive material, such as a doped semiconductor or metal. In such field emission display devices, an interlayer having a controlled conductivity positioned between the cathode and the microtip is highly desirable. Proper treatment of the resistance of the interlayer allows the display device to be operated in a stable and controllable manner. Although the resistance of the intermediate layer has a value between the insulator and the conductor, the actual desired value depends on the specific device configuration.

Chemical vapor deposition (CVD) or plasma enhanced chemical vapor deposition (PECVD) is a widely used process for depositing material layers on various substrates in the manufacture of semiconductor devices. In a conventional PECVD process, the substrate is placed in a vacuum deposition chamber equipped with a pair of parallel plate electrodes. Such substrates are typically mounted on susceptors that act as bottom electrodes. Reactant gas enters the vacuum chamber through a gas inlet manifold that acts as an upper electrode. Radio frequency (RF) voltage is applied between the two electrodes to generate sufficient RF power to form a plasma in the reaction gas. The plasma decomposes the reaction gas and deposits the desired layer of material on the surface of the substrate. An additional layer of other electronic material can be deposited on the first surface by flowing a reactant gas containing the additional layer of material to be deposited into the deposition chamber. Each reactant gas is exposed to a plasma, which deposits the desired layer of material.

In the manufacture of field emission display devices, it is desirable to deposit an amorphous silicon-based thin film having a conductivity in the middle range between the conductivity of intrinsic amorphous silicon and the conductivity of n ⁺ doped amorphous silicon. The conductivity of n ⁺ doped amorphous silicon is controlled by controlling the amount of phosphor atoms contained in the thin film. Although it is possible to produce intermediate conductivity thin films by adding very small amounts of phosphor atoms, this is a very difficult task because it requires a specially premixed PH ₃ / H ₂ to precisely control the amount of phosphor atoms.

Since field emission display devices use very thick layers, it has been required to deposit low stress thin films to prevent the glass from bending and peeling off of the thin films. Standard processes for deposition for depositing amorphous silicon form high compression films, especially when deposited at high deposition rates.

Accordingly, the present invention is to solve the above problems of the prior art, an object of the present invention is to provide a method for producing an amorphous silicon-based thin film having a controlled resistance and low stress.

The amorphous silicon based thin film can be used as an intermediate layer when manufacturing the field emission display device. Such thin films can also be used in other electronic devices that require thin films having a controlled resistance in the range between the resistance of the insulator and the resistance of the conductor. The deposition method described in the present invention applies a chemical vapor deposition method or a plasma enhanced chemical vapor deposition method, and other deposition techniques such as a physical vapor deposition method may be applied.

According to one aspect, the present invention provides a method of forming an amorphous silicon-based thin film on a substrate located in a deposition chamber, the method comprising the steps of introducing a silicon-based volatile material into the deposition chamber and one for increasing the conductivity of the amorphous silicon-based thin film into the deposition chamber. Introducing a conductivity increasing volatile comprising the above components and introducing a conductivity reducing volatile comprising one or more components into the deposition chamber to reduce the conductivity of the amorphous silicon based thin film.

According to another aspect, the present invention provides a method of forming an amorphous silicon-based thin film on a substrate located in a deposition chamber, the method comprising the steps of: introducing a silicon-based volatile material into the deposition chamber, introducing hydrogen phosphine into the deposition chamber; And introducing a nitrogen-containing volatile into the deposition chamber.

According to another aspect, the present invention provides a method of forming an amorphous silicon-based thin film on a substrate located in a deposition chamber, the method comprising the steps of introducing silicon-based volatiles into the deposition chamber, introducing hydrogen phosphide into the deposition chamber, and Introducing a carbon-containing volatile into the deposition chamber.

Embodiments may include one or more of the following features.

Conductivity increasing volatiles and conductivity reducing volatiles may be introduced into the deposition chamber at each relative flow rate selected to achieve the desired thin film resistance. These relative flow rates (relative flow rate) may be selected to achieve a film resistance of about 10 ^{3-10 7} ohm -cm. The conductivity increase volatile may be composed of hydrogen phosphide, the conductivity decrease volatile may be composed of ammonia, and the hydrogen phosphide and ammonia may have a flow ratio ranging from about 1: 1000 to about 1:10 (hydrogen phosphide: ammonia). Is introduced into the deposition chamber. Instead, the conductivity increasing volatile may be composed of hydrogen phosphide, the conductivity reducing volatile may be composed of methane, and such hydrogen phosphide and methane may be from about 1: 100 to about 1: 1 (hydrogen phosphide: methane). It is introduced into the deposition chamber at a flow rate ratio in the range.

The conductivity increasing volatile may comprise a dopant. Such dopants may include n-type dopants (eg, phosphorus) or p-type dopants (eg, boron).

Amorphous silicon-based thin films may be characterized by band gaps, and the conductivity-reducing volatiles increase the band gap of the amorphous silicon-based thin films as compared to thin films formed under similar conditions that do not include a band gap increasing component. Contains increasing ingredients. The conductivity reducing volatiles may include nitrogen, ammonia, N ₂ , N ₂ O, carbon (eg methane).

In one embodiment of the present invention, the silicon-based thin film is composed of silane, the conductivity increasing volatile material is composed of hydrogen phosphide, the conductivity reducing volatile material is composed of ammonia. In another embodiment, the silicon-based thin film consists of silane, the conductivity increasing volatile material consists of hydrogen phosphide, and the conductivity reducing volatile material consists of methane. In another embodiment, the silicon based thin film is composed of silane, the conductivity increasing volatile material is composed of hydrogen phosphide, the first conductivity reducing volatile material is comprised of ammonia, and the second conductivity reducing volatile material is comprised of methane.

A second conductivity reducing volatile may be introduced into the deposition chamber.

In a preferred embodiment, an amorphous silicon-based thin film with finely controlled conductivity and low stress is formed by flowing a reaction gas mixture into a plasma enhanced chemical vapor chamber. This reaction gas mixture includes hydrogen phosphide, silane, and ammonia carried by hydrogen gas. By changing the content of the fluorescent material by controlling the partial pressure of hydrogen phosphide, the n-type conductivity of the amorphous silicon-based thin film can be changed. In other words, increasing the content of the fluorescent substance increases the conductivity. By changing the nitrogen content of the reaction gas by controlling the ammonia partial pressure, the resistance can be changed. In other words, increasing the nitrogen content increases the resistance of the amorphous silicon-based thin film. The ideal range of resistance for field emission display devices is between about 10 ³ to 10 ⁷ ohm-cm. The novel method according to the present invention can control the resistance of the amorphous silicon-based thin film within the preferred range between 10 ³ and 10 ⁷ ohm-cm. The thin film formed by the method according to the invention has a low tensile stress to prevent the thin film from bending or peeling off from the substrate.

The present invention also relates to a field emission display device fabricated by plasma enhanced chemical vapor deposition techniques, wherein a reactant gas mixture comprising silane, hydrogen, hydrogen phosphide (carried by hydrogen), and ammonia provides controlled conductivity. It is used to form an amorphous silicon-based thin film having. By controlling the flow rate of each component gas, an amorphous silicon-based thin film having finely controlled conductivity and low stress can be obtained to form a field emission device.

Advantages of the present invention are as follows.

The present invention provides a method for depositing amorphous silicon-based thin films having controlled conductivity and low stress in a chemical vapor deposition process or a plasma enhanced chemical vapor deposition process by combining simple process control steps. The present invention also provides a method of depositing an amorphous silicon based thin film having controlled conductivity and low stress in a chemical vapor deposition process or a plasma enhanced chemical vapor deposition process by using a reaction gas mixture comprising PH ₃ or NH ₃ . The present invention also provides a method of depositing an amorphous silicon-based thin film having controlled conductivity and low stress in a chemical vapor deposition process or a plasma enhanced chemical vapor deposition process by controlling the flow rate of the reaction gas in the reaction chamber.

Hereinafter, the present invention will be described in detail with reference to the accompanying drawings.

The present invention discloses an improved method for depositing amorphous silicon-based thin films having controlled conductivity and low stress on a substrate by plasma enhanced chemical vapor deposition techniques for electronic devices such as field emission display devices.

First, referring to FIG. 1, a plasma enhanced chemical vapor deposition apparatus 10 capable of carrying out the method according to the invention is schematically illustrated. Such a device is disclosed in US Pat. No. 5,512,320 to Turner et al. Deposition chamber 12 includes an opening through top wall 14 and a gas inlet manifold or first electrode 16. Instead, top wall 14 may be formed with an electrode 16 adjacent its inner surface. In the chamber 12 there is a plate-shaped susceptor 18 extending parallel to the first electrode 16. The susceptor 18 generally consists of aluminum and is coated with an aluminum oxide layer. The susceptor 18 is grounded and acts as a second electrode to be connected to the RF source 36 across the two electrodes 16, 18.

The susceptor 18 is mounted at the end of the shaft 20 extending vertically through the bottom wall 22 of the deposition chamber 12. The axis 20 may move vertically, whereby the susceptor 18 may move vertically in the direction toward the first electrode 16 and away from the first electrode 16. A lift-off plate 24 extends horizontally and moves vertically between the susceptor 18 and the bottom wall 22 of the deposition chamber 12 substantially parallel to the susceptor 18. It is possible. The lift-off pin 26 projects vertically upward from the lift-off plate 24. The lift-off pin 26 is positioned to extend through the lift hole 28 in the susceptor 18 and has a length slightly longer than the thickness of the susceptor 18. Although only two lift-off pins 26 are shown in the figure, more lift-off pins 26 may be spaced around the lift-off plate 24.

The gas outlet 30 extends through the side wall 32 of the deposition chamber 12 and is connected to a means (not shown) for discharging the deposition chamber 12. The gas inlet pipe 42 extends into the gas inlet manifold or first electrode 16 of the deposition chamber 12 and is connected to a source (not shown) through a gas switching network (not shown) of various gases. It is. The first electrode 16 is connected to the RF power source 36. Transfer paddles for transferring the substrate onto susceptor 18 in deposition chamber 12 through a load-lock door (not shown) and also for removing the coated substrate from deposition chamber 12. (Not shown) is provided.

In operation of the deposition apparatus 10, the substrate 38 is first loaded into the deposition chamber 12 and positioned on the susceptor 18 by a transfer paddle (not shown). Substrate 38 is sized to extend over lift hole 28 in susceptor 18. Substrates that can be used in flat panel display devices range from approximately 360 mm to 465 mm. The susceptor 18 is positioned above the lift-off pin 26 by moving the shaft 20 upward so that the lift-off pin 26 does not extend through the hole 28. The substrate 38 is relatively adjacent to the first electrode 16. The electrode space or distance between the substrate surface and the discharge surface of the gas inlet manifold 16 is about 12-50 mm. More preferred electrode space is about 20 to 36 mm.

Prior to the deposition process of the present invention, the substrate 38, which may be a large sheet of transparent material, is treated according to known techniques. In a preferred embodiment after the initial process, the top layer comprising the patterned metal layer is deposited.

At the start of the deposition process of the present invention, the deposition chamber 12 is first discharged through the gas outlet 30. The patterned substrate 38 is then placed on the susceptor 18. The substrate 38 is maintained at a temperature between about 200 ° C. and 400 ° C. during the deposition of the amorphous silicon thin film. During the deposition process, the preferred temperature range of the substrate is between about 300 ° C and 350 ° C. During the deposition process, the pressure in the reaction chamber is maintained between about 0.5 Torr and 5 Torr, with a preferred temperature range of about 1.5 Torr to 2.5 Torr. The process of treating a substrate using such an apparatus is described in more detail in US Pat. No. 5,399,387 to Law et al., Which is incorporated herein by reference.

2 is an enlarged cross-sectional view of a typical field emission display device 50. The display device 50 is formed by depositing a resistive layer 52 of an amorphous silicon based thin film on a glass substrate 54. Thereafter, the insulating layer 56 and the metal gate layer 58 are formed successively, and are etched to form the metal microtip 60. Cathode structure 60 is covered with a resistive layer 52. Thus, an amorphous silicon layer 52, which is resistive but somewhat conductive, is placed under the high insulating layer 56, such as SiO ₂ . Rather than controlling the amorphous silicon layer 52 to have excessive resistance, the amorphous silicon layer 52 acts as a limiting resistor to prevent excessive current flow when one of the microtips 60 is shorted with the metal layer 58. It is important to control the resistance.

Although field emission display devices are shown herein to demonstrate the method of the present invention, it should be noted that such methods are not limited to the manufacture of FED. The method of the present invention can also be used in the manufacture of other electronic devices that require a deposition layer having a controlled resistance.

A series of tests was performed on test samples prepared by the method of the present invention to determine the effect of reactant flow rate on the conductivity and stress of the prepared thin film. Their results are summarized in Table 1 and Table 2.

Example 1

Example 1 relates to a deposition process for an intrinsic amorphous silicon thin film that does not include a doping gas in a reaction gas mixture. This thin film is formed on a heated substrate as a byproduct of the reaction of silane and hydrogen in the plasma. The flow rate of the silane is controlled at 1000 sccm, the flow rate of hydrogen is controlled at 1000 sccm, the plasma power used (i.e., the RF power supplied to the electrode 16) is 300 W, and the chamber pressure is maintained at 2.0 Torr. The space (ie, the space between the electrode 16 and the susceptor 18) is maintained at 962 mils (2.44 cm), and the susceptor for heating the substrate by contact heating is maintained at a temperature of 410 ° C., and obtained Deposited rate is 168 nm / min. After the deposition process was completed, the obtained thin film was tested and found to be 8.0 × 10 ^8. It was confirmed that it had physical properties of a compressive stress of dyne / cm ² and a resistance of 2.0 × 10 ⁹ ohm-cm.

Example 2

Example 2 relates to a deposition process of the thin film is deposited p- doped amorphous silicon thin film on the flow state of the PH ₃ gas with no NH ₃ gas. The flow rate of silane is 1000sccm, the flow rate of PH ₃ is 0.5sccm, the flow rate of hydrogen is 1000sccm, the RF power is 300W, the chamber pressure is 2.0 Torr, the electrode space is 962mils (2.44cm), The acceptor temperature is 410 ° C., and the deposition rate obtained is 156 nm / min. Hydrogen phosphide has a concentration of 0.5% in the hydrogen carrier at this flow rate. The amorphous silicon thin film obtained was 1.7 × 10 ⁹ dyne / cm ² It has a compressive stress of and a resistance of 1.7 × 10 ² ohm-cm.

Example 3

In this example, only ammonia gas is used in the reaction gas mixture without using the PH ₃ gas. The flow rate of silane gas used is 1000sccm, the flow rate of NH ₃ is 500sccm, the flow rate of hydrogen is 1000sccm, the RF power is 300W, the chamber pressure is maintained at 2.0 Torr, the electrode space is 962mils (2.44cm) ), The susceptor temperature is 410 ° C, and the deposition rate obtained is 135 nm / min. The physical properties obtained in such a thin film are significantly different from the physical properties of the thin film obtained in Example 2. Thin film stress is 7.4 × 10 ⁹ dyne / cm ² Is the tensile mode. The resistance of the thin film measured has a high value of 2.2 × 10 ¹⁰ ohm-cm.

Example 4

In this example, a doping gas of PH ₃ and a nitrogen containing NH ₃ gas are used as the reaction gas mixture. The flow rate ratio of PH ₃ to NH ₃ is 1.25 × 10 ⁻² to 1. The flow rate of silane gas used is 1000sccm, the flow rate of PH ₃ is 2.5sccm, the flow rate of NH ₃ is 200sccm, the flow rate of hydrogen is 1000sccm, the RF power is 600W, and the chamber pressure is maintained at 2.0 Torr. Electrode space is 962 mils (2.44 cm), susceptor temperature is 400 ° C., and the deposition rate obtained is 197 nm / min. An amorphous silicon thin film having a desired resistance is obtained. The thin film obtained was 4.0 × 10 ⁸ dyne / cm ² It has a physical property of tensile stress and resistance of 1.6 × 10 ⁵ ohm-cm. Here, the resistance value is the value measured in Examples 2 and 3, i.e. 1.7 × 10 ² and 2.2 × 10 ¹⁰ It should be noted that it is approximately midway between.

Example 5

In this example, both PH ₃ and NH ₃ gases are used in the reaction gas mixture. The flow rate ratio of PH ₃ to NH ₃ is 0.75 × 10 ⁻² to 1. In this chemical vapor deposition process, the flow rate of silane gas used is 1000sccm, the flow rate of PH ₃ is 1.5sccm, the flow rate of NH ₃ is 200sccm, the flow rate of hydrogen is 1000sccm, the RF power is 600W, the chamber The pressure of is maintained at 2.0 Torr, the electrode space is 962 mils (2.44 cm), the susceptor temperature is 400 ℃, and the deposition rate obtained is 197 nm / min. The thin film obtained was 1.3 × 10 ⁹ dyne / cm ² It has a physical property of tensile stress and resistance of 9.6 × 10 ⁵ ohm-cm. By decreasing the flow rate of PH _{3 relative to} the flow rate of NH ₃ , it can be seen that the resistance of the thin film is increased and the tensile stress is slightly increased in comparison with Example 4.

Example 6

In this example, PH ₃ and NH ₃ gases are used in the reaction gas mixture. The flow rate ratio of PH ₃ to NH ₃ is 1.5 × 10 ⁻² to 1. In this chemical vapor deposition process, the flow rate of silane gas used is 1000sccm, the flow rate of PH ₃ is 1.5sccm, the flow rate of NH ₃ is 100sccm, the flow rate of hydrogen is 1000sccm, the RF power is 600W, the chamber The pressure of is maintained at 2.0 Torr, the electrode space is 962 mils (2.44 cm), the susceptor temperature is 400 ℃, and the deposition rate obtained is 240 nm / min. Thereby, 4.7x10 ⁹ dyne / cm ² An amorphous silicon thin film having physical properties of tensile stress of and a resistance of 3.6x10 ⁵ ohm-cm is obtained. Compared with Example 5, it can be seen that by reducing the ammonia content in the reaction gas mixture relative to the PH ₃ content, the resistance of the deposited thin film is reduced and the tensile stress is slightly increased.

Example 7

In this example, PH ₃ and NH ₃ gases are used in the reaction gas mixture. The flow rate ratio of PH ₃ to NH ₃ is 0.6 × 10 ⁻² to 1. A flow ratio of PH ₃ to NH ₃ as low as 0.1 × 10 ⁻² or 0.001: 1 may be used. In this chemical vapor deposition process, the flow rate of silane gas used is 1000sccm, the flow rate of PH ₃ is 1.5sccm, the flow rate of NH ₃ is 200sccm, the flow rate of hydrogen is 1000sccm, the RF power is 400W, the chamber The pressure of is maintained at 2.0 Torr, the electrode space is 962 mils (2.44 cm), the susceptor temperature is 400 ℃, and the deposition rate obtained is 180 nm / min. Thereby, 6.3 × 10 ⁹ dyne / cm ² An amorphous silicon thin film having physical properties of tensile stress of and resistivity of 7.0x10 ⁶ ohm-cm is obtained. In comparison with Example 6, it can be seen that by increasing the flow rate of NH ₃ , the resistance of the thin film is significantly increased while the tensile stress is kept substantially constant.

Example 8

In this example, PH ₃ and NH ₃ gases are used in the reaction gas mixture. The flow rate ratio of PH ₃ to NH ₃ is 2.5 × 10 ⁻² to 1. Flow ratios of PH ₃ to NH ₃ as high as 1 × 10 ⁻¹ or 0.1: 1 may be used. In this chemical vapor deposition process, the flow rate of silane gas used is 1000sccm, the flow rate of PH ₃ is 2.5sccm, the flow rate of NH ₃ is 100sccm, the flow rate of hydrogen is 1000sccm, the RF power is 400W, the chamber The pressure of is maintained at 2.0 Torr, the electrode space is 962 mils (2.44 cm), the susceptor temperature is 400 ℃, and the deposition rate obtained is 190 nm / min. Thereby, 4.8 × 10 ⁹ dyne / cm ² A thin film having physical properties of tensile stress of and resistance of 6.0 × 10 ⁴ ohm-cm is obtained. In comparison with Example 7, it can be seen that by increasing the flow rate of PH ₃ , the resistance of the thin film is significantly reduced, while the tensile stress is kept almost constant.

Example 9

In Example 9, a doping gas of PH ₃ and gaseous nitrogen N ₂ are used in the reaction gas mixture. The flow rate of silane gas used is 1000sccm, the flow rate of PH ₃ is 2.5sccm, the flow rate of N ₂ is 1500sccm, the flow rate of hydrogen is 1000sccm, the RF power used is 600W, and the chamber pressure is maintained at 1.2 Torr. Electrode space is 962 mils (2.44 cm), susceptor temperature is 400 ° C., and the deposition rate obtained is 190 nm / min. An amorphous silicon thin film having a desired resistance is obtained. These films are 2.5 × 10 ⁹ dyne / cm ² It has a physical property of tensile stress and resistance of 9.6 × 10 ⁵ ohm-cm. As expected, increasing the nitrogen concentration increases the resistance and decreases the conductivity.

Example 10

In example 10, a doping gas of PH ₃ and gaseous nitrogen N ₂ are used in the reaction gas mixture. The flow rate of silane gas used is 1000sccm, the flow rate of PH ₃ is 2.5sccm, the flow rate of N ₂ is 500sccm, the flow rate of hydrogen is 1500sccm, the RF power is 600W, the chamber pressure is maintained at 1.2 Torr Electrode space is 962 mils (2.44 cm), susceptor temperature is 400 ° C., and the deposition rate obtained is 194 nm / min. An amorphous silicon thin film having a desired resistance is obtained. These films are 1.1 × 10 ⁹ dyne / cm ² It has a physical property of tensile stress and resistance of 8.2 × 10 ² ohm-cm. This data is consistent with the results obtained in other examples.

Examples 1 to 3 described above are comparative examples prepared by the method according to the prior art. Examples 4 to 10 above describe the advantages possibly achieved by the present invention. Data for Examples 1-10 are disclosed in Tables 1 and 2 below.

Example 1 Example 2 Example 3 Example 4 Example 5 SiH ₄ (sccm) 1000 1000 1000 1000 1000 PH ₃ (sccm) - 5.5 - 2.5 1.5 NH ₃ (sccm) - - 500 200 200 PH ₃ / PH ₃ × 10 ² - - - 1.25 0.75 H ₂ (sccm) 1000 1000 1000 1000 1000 Power (W) 300 300 300 600 600 Pressure (tor) 2.0 2.0 2.0 2.0 2.0 Thickness (mil) 962 962 962 962 962 Temperature (℃) 410 410 410 400 400 Deposition Rate (nm / min) 168 156 135 197 197 Stress (dyne / cm ² ) C 8.0E8 C 1.7E9 T 7.4 E9 T 4.0E8 T 1.3E9 Resistance (Ohm-cm) 2.0E9 1.7E2 2.2E10 1.6E5 9.6E5

Example 6 Example 7 Example 8 Example 9 Example 10 SiH ₄ (sccm) 1000 1000 1000 1000 1000 PH ₃ (sccm) 1.5 1.5 2.5 2.5 2.5 NH ₃ (sccm) 100 250 100 - - PH ₃ / PH ₃ × 10 ² 1.50 0.60 2.50 - - N ₂ (sccm) - - - 1500 500 H ₂ (sccm) 1000 1000 1000 1000 1500 Power (W) 600 400 400 600 600 Pressure (tor) 2.0 2.0 2.0 1.2 1.2 Thickness (mil) 962 962 962 962 962 Temperature (℃) 400 400 400 400 400 Deposition Rate (nm / min) 240 180 190 190 194 Stress (dyne / cm ² ) T 4.7E9 T 6.3E9 T 4.8E9 T 2.5E9 C 1.1E9 Resistance (Ohm-cm) 3.6E5 7.0E6 6.0E4 9.0E5 8.2e2

By mixing PH ₃ and NH ₃ doping gas in various ratios, that is, from about 1000: 1 to about 10: 1 ratio with respect to NH ₃ : PH ₃ , an amorphous silicon thin film having a desired stress value and resistance value can be obtained. As shown in FIG. 3, by changing the hydrogen phosphide content in the reaction gas mixture, the conductivity of the thin film can be changed. For example, an increase in the hydrogen phosphate content increases the conductivity of the thin film because the hydrogen phosphide is an election donor. Similarly, the resistance of the thin film obtained by changing the nitrogen content in the reaction gas mixture is changed because nitrogen contributes to the insulation of the thin film. For example, by increasing the nitrogen content of the reaction gas mixture, the resistance of the amorphous silicon thin film obtained is increased. The preferred range of resistance of the amorphous silicon-based thin film of the present invention is about 10 ³ to 10 ⁷ ohm-cm. This range can be obtained by the data shown in Table 1 and is not provided in other experimental data. The preferred range of resistance is about 10 ⁵ to 10 ⁶ ohm-cm. Therefore, by using the reaction gas mixture of PH ₃ and NH ₃ of the present invention, an amorphous silicon based thin film having controlled conductivity and low stress may be formed.

The stress level in the thin film is generally preferably minimized. Stress value is a low of 10 ⁹ dyne / cm ² or higher should be maintained at 10 ⁸ dyne / cm ² range. As can be seen in FIG. 4, the stress level remains almost constant with respect to the change in the flow rate ratio of PH ₃ : NH ₃ . The method according to the invention can adequately control the stress in the deposited amorphous silicon thin film and can predict and select the resulting resistance.

Examples 1 through 8 used ammonia as the nitrogen containing gas, Examples 9 and 10 used gaseous nitrogen as the nitrogen containing gas, and a controllable resistance in the range of 10 ² to 10 ⁴ ohm-cm occurred. It is believed that other nitrogen containing gases, such as N ₂ O, can achieve similar results. It is believed that nitrogen is introduced into the amorphous silicon matrix at a level much higher than the level associated with the doping level. Increasing the concentration of dopant P in the n-type semiconductor from PH ₃ increases the conductivity (decreases in resistance), while increasing the concentration of nitrogen reduces the electron band gap as the output gradually changes from amorphous silicon to silicon nitride. There is a tendency to increase. The larger the band gap, the higher the resistance. Thus, similar results can be obtained by using a carbon containing gas or an oxygen containing gas that advances the material towards semi-insulating silicon carbide and dielectric silicon oxide.

For example, to control the conductivity of the deposited thin film, a carbon containing volatile (eg, gas or gaseous material) may be introduced during deposition of the amorphous silicon-based thin film. In one embodiment, methane (CH ₄ ) is introduced into the deposition chamber together with a silicon-containing volatile (eg silane gas) and a dopant volatile (eg PH ₃ gas or B ₂ H ₆ gas), An amorphous silicon-based thin film is formed. As shown in FIG. 5, when hydrogen phosphide gas is used as the dopant volatile, as the flow rate of methane increases relative to the flow rate of hydrogen phosphate gas (ie, as the flow rate ratio of PH ₃ : NH ₃ decreases), deposition is performed. The resistance of the thin film is increased. Thus, the addition of a carbon-containing volatile deposition chamber tends to increase the resistance of the deposited thin film and other factors remain unchanged. In other embodiments, the nitrogen-containing volatiles (eg, NH ₃ , N ₂ , or N ₂ O) are carbon-containing volatiles (eg, CH ₄ ) and dopant volatiles (eg, PH ₃ or B ₂ H ₆ ) may be introduced into the deposition chamber. In this embodiment, the carbon-containing volatiles and the nitrogen-containing volatiles serve to increase the resistance of the deposited thin film, and the dopant volatiles serve to increase the conductivity of the deposited thin film. In any of these embodiments, amorphous silicon-based thin films may be formed by various thin film formation techniques including chemical vapor deposition (CVD), plasma enhanced chemical vapor deposition (PECVD), and physical vapor deposition (PVD). When the thin film is formed using PVD, carbon containing volatiles may be introduced into the deposition chamber by RF sputtering a high purity silicon carbide target.

The above examples describe an amorphous silicon thin film having a controllable resistance in the range of 10 ² to 10 ⁷ ohm-cm. Applicants have found that this controllable range can be extended to 10 ¹⁰ ohm-cm by using very small amounts of hydrogen phosphide, especially hydrogen phosphide having a high ammonia concentration of Example 3, which is readily obtainable in the prior art. Could not.

Although the invention has been described by way of example, it is to be understood that the terminology used is not a limitation of technical characteristics.

In addition, although the present invention has been described by the preferred embodiments, those skilled in the art will be able to readily adapt the techniques of the present invention. For example, other volume ratios between the doping gases may be used in place of the volume ratios shown in the examples. Examples of PH ₃ dopant gas provide n-type doping. Other n-type dopant gases may be used in the present invention. Also, a p-type dopant gas such as B ₂ H ₆ may be used in the present invention. Although hydrogen is used to deposit high quality amorphous silicon, the hydrogen gas of the examples is reduced less than NH ₃ , so the hydrogen gas mainly acts as a carrier gas. Another carrier gas that is less reduced than the nitrogen containing gas may replace H ₂ . Examples of such carrier gases include argon and helium. Moreover, although PECVD processes are used to deposit layers in field emission display devices, other processes such as CVD may be used to deposit amorphous silicon-based thin films with controlled conductivity in other semiconductor devices.

Other embodiments are within the scope of the claims.

According to the present invention described above, by providing a method for manufacturing an amorphous silicon-based thin film having a controlled resistance and low stress, it is possible to prevent the bending of the glass and the peeling of the thin film which is a problem with the field emission display device according to the prior art. .

Claims (31)

A method of forming an amorphous silicon based thin film on a substrate located in a deposition chamber, Introducing a silicon-based volatile into the deposition chamber; Introducing a conductivity increasing volatile material comprising at least one component for increasing the conductivity of the amorphous silicon based thin film into the deposition chamber, and Introducing a conductivity reducing volatile material comprising one or more components to reduce the conductivity of the amorphous silicon based thin film into the deposition chamber. The method of claim 1, wherein the conductivity increasing volatile and the conductivity reducing volatile are introduced into the deposition chamber at respective relative flow rates selected to achieve a desired thin film resistance. ^3. The method of claim 2, wherein the relative flow rates are selected to achieve a thin film resistance of 10 ³ to 10 ⁷ ohm-cm. The method of claim 1, wherein the conductivity increasing volatile material is composed of hydrogen phosphide, the conductivity reducing volatile material is composed of ammonia, the hydrogen phosphide and ammonia is in the range of 1: 1000 to 1: 10 (hydrogen phosphide: ammonia) A method for forming an amorphous silicon based thin film introduced into the deposition chamber at a flow rate ratio. The method of claim 1, wherein the conductivity increasing volatile material is composed of hydrogen phosphide, the conductivity reducing volatile material is composed of methane, the hydrogen phosphide and methane is in the range of 1: 100 to 1: 1 (hydrogen phosphide: methane) A method for forming an amorphous silicon based thin film introduced into the deposition chamber at a flow rate ratio. The method of claim 1, wherein the conductivity increasing volatile material comprises a dopant. The method of claim 6, wherein the dopant comprises an n-type dopant. 8. The method of claim 7, wherein the n-type dopant comprises phosphorus. The method of claim 6, wherein the dopant comprises a p-type dopant. 10. The method of claim 9, wherein the p-type dopant comprises boron. 2. The method of claim 1, wherein the amorphous silicon-based thin film is characterized in that the band gap, the band gap increasing component for increasing the band gap of the amorphous silicon-based thin film compared to the thin film formed without a band gap increasing component to reduce the conductivity A method for forming an amorphous silicon-based thin film containing a material. The method of claim 1, wherein the conductivity reducing volatile material comprises nitrogen. The method of claim 12, wherein the conductivity reducing volatile material comprises ammonia. The method of claim 1, wherein the conductivity reducing volatile material comprises N ₂ O. 7. The method of claim 1, wherein the conductivity reducing volatile material comprises carbon. The method of claim 15, wherein the conductivity reducing volatile comprises methane. The method of claim 1, wherein the silicon-based thin film comprises silane, the conductivity increasing volatile material comprises hydrogen phosphide, and the conductivity reducing volatile material consists of ammonia. The method of claim 1, wherein the silicon-based thin film is made of silane, the conductivity increasing volatile material is made of hydrogen phosphide, and the conductivity reducing volatile material is made of methane. The method of claim 1, further comprising introducing a second conductivity reducing volatile into the deposition chamber. 20. The method of claim 19, wherein the silicon-based thin film is composed of silane, the conductivity increasing volatile material is composed of hydrogen phosphide, the conductivity reducing volatile material is composed of ammonia, the second conductivity reducing volatile material is composed of methane Amorphous silicon-based thin film formation method. delete delete delete A method of forming an amorphous silicon based thin film on a substrate located in a deposition chamber, Introducing a silicon-based volatile into the deposition chamber; Introducing hydrogen phosphide into the deposition chamber, and A method of forming an amorphous silicon-based thin film comprising introducing a nitrogen-containing volatile material into the deposition chamber. delete delete delete A method of forming an amorphous silicon based thin film on a substrate located in a deposition chamber, Introducing a silicon-based volatile into the deposition chamber; Introducing hydrogen phosphide into the deposition chamber, and Introducing a carbon-containing volatile into the deposition chamber. delete delete delete

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