GB2199987A - Doped polycrystalline silicon layers for semiconductor devices - Google Patents

Abstract

An improved phosphorus doped polycrystalline silicon layer for semiconductor devices is deposited in the amorphous state by low pressure chemical vapor deposition in an isothermal reactor (Fig 2) from a gas mixture containing an increased amount of phosphine over the amount conventionally used. The gas proportions are 16 x 10<-4> to 17 x 10<-4> parts by volume of phosphine to each part by volume of silane. After deposition the layer is annealed to convert it to the polycrystalline state. A layer formed by this method is characterized by exceptional uniformity of doping, enlarged grain size, significantly increased electrical conductivity and improved radiation hardness in comparison to layers formed by conventional processes. <IMAGE>

Description

DOPED POLYCRYSTALLINE SILICON LAYERS FOR SEMICONDUCTOR DEVICES This invention relates to the formation of doped polycrystalline silicon layers in semiconductor devices and structures.

A MOS (metal-oxide-semiconductor) device conventionally includes a semiconductor substrate, an insulating layer of oxide on the substrate and a gate: electrode disposed thereover. In a SOS device, the substrate is sapphire with a layer of silicon thereover.

In such devices, polycrystalline silicon is used as the gate electrode and must be doped to render it conductive.

Doping is conventionally carried out by diffusion of phosphorus in an oxidizing ambient, typically utilizing phosphorus oxychloride at 9000-10000C.

In recent years, it has been shown that an improved polycrystalline silicon layer having a smoother surface can be produced by initially depositing silicon in the amorphous state and heat annealing to convert it to the polycrystalline state. Typically, the amorphous silicon layer is formed by low pressure chemical vapor deposition (LPCVD) from silane at a temperature of from about 5500 to 5800C. The layer may be directly heat annealed or may be converted to the polycrystalline state by heating in a subsequent processing step, such as oxidation or diffusion doping. The silicon layer is conventionally doped by diffusion since, heretofore, doping of such a layer in-situ by adding a dopant, i.e., phosphine, to the LPCVD gas mixture has not been demonstrated to be commercially attractive.

The in-situ doping of silicon layers, although attractive in terms of providing a reduction in the number of processing steps required to fabricate a device, has suffered from two disadvantages. First, in comparison to undoped silicon, in-situ doping produces a layer having inferior radial thickness uniformity. Second, in the deposition techniques heretofore utilized, the dopant concentration of the layers is not uniform. In areas where there would be an excess of dopant ions, the excess ions would be in the interstitial spaces between the grains of the layer. Ions in the interstitial spaces, i.e., the grain boundaries, readily migrate and will diffuse into adjacent silicon dioxide layers during heat annealing to the detriment of the device. In addition, dopant ions which are in the grain boundaries are not electrically active.This is a further disadvantage as maximum electrical activity is desired when the doped silicon layer is functioning, e.g. as a gate electrode in MOS integrated circuit fabrication. This nonuniformity of dopant concentration is also true for conventional diffusion doping.

In accordance with this invention, a process of producing an in-situ doped silicon film is provided which does not suffer from the above-named disadvantages and which, unexpectedly, produces a doped silicon layer which is markedly more electrically active and which has increased radiation hardness in comparison to similar layers produced by conventional processes.

Such an in-situ doped silicon layer is produced by low pressure chemical vapor deposition in an isothermal reactor from a gas mixture containing a concentration of a source of the dopant, e.g., phosphine, significantly larger than that typically used.

In the accompanying drawing: FIGURE 1 is a schematic illustration of a cross-sectional view of a typical MOS device.

FIGURE 2 is a cross-sectional view of an isothermal reactor.

The present invention relates to semiconductor or other electronic devices which contain one or more layers of polycrystalline silicon. Such devices or structures commonly contain or are part of an electronic circuit.

Examples of such devices include MOS gates, interconnects, load resistors, double poly capacitors and numerous devices found in the high density integrated circuit technology.

As utilized herein, the term '#device" shall include semiconductor#structures or assemblies. In general, this invention is applicable to any electronic device requiring one or more layers of polycrystalline silicon, such as that illustrated in FIGURE 1.

FIG. 1 illustrates a typical MOS field-effect device such as would be utilized, for example, in large scale integrated logic and memory circuits. The device shown in FIG. 1 comprises a substrate 10 of a semiconductor material such as silicon, or a layer of such material overlying an insulator such as sapphire or silicon dioxide.

A thin layer of gate oxide 12 overlies the semiconductor substrate 10. Underlying the layer of gate oxide 12 are source and drain regions 14 which have been defined by ion implantation through an opening in a layer of field oxide 16. The gate oxide 12 and field oxide 16 are silicon dioxide. Overlying the layer of gate oxide 12 is a polycrystalline silicon gate 18. Typically, the gate 18 is part of a first level of polycrystalline silicon in a multilayer device.

Conventionally, a layer of silicon is deposited over the entire surface of the substrate 10 to overlie the dielectric layer 12, doped by diffusion and then lithographically patterned to form isolated structures such as the gate 18. As noted previously, diffusion doping of the polysilicon layer can produce uneven distribution of the dopant which, in turn, can result in migration of the dopant, particularly phosphorus, into the gate dielectric layer 12 during heat annealing. This can result in malfunctioning of the device. It will be appreciated that, as the degree of uniformity of dopant decreases and as the concentration of dopant ions at the grain boundaries of the silicon gate increases, it becomes more likely that the device will malfunction.The conductivity of the silicon gate 18, on the other hand, will increase with dopant uniformity and a corresponding drop in dopant concentration at the grain boundaries.

In addition, conventional diffusion doping with phosphorus oxychloride introduces a significant level of chlorine ions into the silicon layer. Chlorine ions are a recognized contaminant which can adversely affect the reliability of a device containing them.

Conductive silicon gates and similar structures are formed in accordance with this invention by chemical vapor depositing (CVD), suitably, by low pressure chemical deposition (LPCVD) in an isothermal reacton vessel. Such apparatus is known and is commercially available from Anicon Corp., San Jose, Califormia. FIG. 2 illustrates a portion of an isothermal reactor deposition system having an inner crucible 20 and an outer crucible 22. An outer housing 24 has an interior cavity 26 which contains therein the outer crucible 22. The outer crucible 22 is retained within the cavity 26 by a bracket plate 28 which supports the weight of the crucible 22 and is attached to the outer housing 24. The outer crucible 22 includes an interior chamber 30 within which a wafer carrier support 32 is arranged as shown in FIG. 2.A gas feeder tube 34 projects upwardly through openings in a support 32 and terminates in an injector 36 from which process, i.e., reactant or purge, gases, indicated by the arrows 38, are emitted. A pair of typical wafer carriers 40 having wafers 42 thereon are shown on the support 32. A stainless steel dome 44 is arranged to completely cover the injector 36, the wafer carriers 40, and wafers 42. A pair of brackets 46 are attached to each side of the dome 44 and project outwardly toward the interior wall of the outer crucible 22. A passage 52 is provided in the support 32 for directing the process gasses 38 into the interior of a central column 54 for evacuation by a pumping system, not shown. When it is desired to load wafers onto the support 32 for deposition or to remove processed wafers, the housing 24 and retained crucible 22 are raised upwardly, in the direction indicated by the arrow A in FIG. 2. The brackets 46 project near the interior wall of the outer crucible 22 so that they engage projections 50 which are disposed on the lower edge of the wall. Therefore, as the housing 24 and outer crucible 22 are raised, the brackets 46 engage the projections 50 and the dome 44 is lifted off the support 32 and raised along with the housing 24 and crucible 22.

As disclosed in Tino, U.S. patent application Serial No. 897,421, filed August 18, 1986 (RCA 83,238), the exposed surfaces of the isothermal reactor which would normally be contacted by the process gases are suitably coated with a layer of phosphorus-doped polycrystalline silicon at least 50 nm thick and suitably between about 100 and 150 nm thick. The phosphorus concentration in the silicon coating is as close as possible to saturation, suitably not lower than about 7 X leo20 atoms per cm3. The presence of the coating effectively getters mobile ion contamination in the deposition chamber, thereby substantially reducing the possibility of contamination of the silicon layers deposited in accordance with the subject process.

In accordance with this invention, in-situ phophorus-doped silicon is deposited in the amorphous state by LPCVD in an isothermal reactor from a deposition gas mixture of silane and phosphine. Conventionally, such gas mixtures typically contain 8 X 10 4 part of phosphine per part of silane, utilizing one percent phosphine diluted with hydrogen or nitrogen. This was considered to be about the practical limit of phosphine concentration as higher concentrations were found to retard the deposition rate, adversely affect the deposition uniformity and produce excess phosphorus in the grain boundaries where a subsequent heating step, e.g., annealing the film, would drive it into an adjacent silicon dioxide layer.The subject process contemplates phosphine/silane gas mixtures of from about 16 X 10 4 to 17 X 101"4 preferably about 16.6 X 10 4 part of phosphine per part of silane. Utilizing an isothermal reactor, it has been found that none of the above phenomena occur with the increased phosphine concentration. Further, the increased concentration of phosphorus in the deposited film has been found to be uniform and electrically active. Therefore, the subject process produces a doped silicon layer which is significantly more electrically active than similar films produced by the conventional in-situ doping process.

While it is not known exactly why the subject process permits a higher than conventional amount of dopant in the gas mixture without the expected adverse effects and, unexpectedly, produces a significant increase in the electrical activity of the resulting silicon layer, it-is believed to be related to the fact that the isothermal reactor produces an exceptionally uniform film with increased grain size. The increased grain size permits a larger concentration of phosphorus within the grains.

There is also less grain boundary space available in the film in which the dopant can accumulate. Doped polycrystalline silicon layers produced by the subject process are advantageous in being ideally suited to the formation of gates in structures such as illustrated in FIG. 1 since the subject process makes possible a thinner, substantially more electrically active silicon layer which would exhibit little if any phosphorus diffusion into underlying gate oxide layers. The substantially increased conductivity of doped polycrystalline silicon layers formed by the subject process is advantageous in that devices incorporating them are capable of a corresponding increase in operating speed.Doped polycrystalline silicon structures formed by the subject process are further advantageous in that, unexpectedly, they have markedly increased radiation hardness in comparison with similar structures formed by conventional techniques.

The formation of silicon layers by the subject process is carried out in an isothermal reactor such as illustrated in FIG. 2 utilizing a mixture suitably comprising, on a volume basis, from about 3.9 to about 4.1, preferably about 4, parts of a carrier gas, from about 2.9 to about 3.1, preferably about 3, parts of silane and from about .49 to about .51, preferably about .5, part of a mixture of one percent of phosphine in the carrier gas.

Typically, the carrier gas is nitrogen or hydrogen, with the latter being preferred. The preferred ratio provides about 16.6 X 10 4 part by volume of phosphine for each part by volume of silane. Deposition is suitably carried out at a pressure of from about 500 to 700, preferably about 600, mtorr at a temperature of from about 5600 to 5750C, suitably about 5650C, and a total gas flow of from about 745 to 755, preferably about 750, cm3/min. A phosphorus-doped amorphous silicon film is deposited at the rate of about 1.8 nm/min.

The silicon layers produced in accordance with this invention are annealed to the polycrystalline state by heating to a temperature of from about 8000 to l0000C. If a subsequent processing operation will attain these temperatures, a separate annealing step is not required.

Typically, heating at 8500C for about 20 minutes is sufficient to anneal the layers and convert them to the polycrystalline state. In general, doped polycrystalline silicon layers formed in accordance with this invention are from about 50 to about 700 nm in thickness.

The following Examples further illustrate this invention, it being understood that the invention is in no way intended to be limited to the details described therein. In the Examples, all parts and percentages are on a weight basis and all temperatures are in degrees Celsius, unless otherwise states.

EXAMPLE 1 Deposition of a phosphorus-doped polycrystalline silicon was carried out on (100) silicon substrates having a 300 nm thick layer of thermally grown oxide in an isothermal reactor, model number V-SIN 4096, manufactured by Anicon Corp., San Jose, California. The gas mixture comprised, on a volume basis, 4 parts of hydrogen, 3 parts of silane and .5 part of a mixture of one percent by volume of phosphine in hydrogen. Total gas flow was 750 cm3/min.

The reaction chamber was heated to 5650 and purged with dry nitrogen prior to deposition of the silicon layer. A layer of doped amorphous silicon 300 nm thick was deposited over 163 minutes.

Samples of silicon layers were annealed in a furnace under nitrogen for 20 minutes at various temperatures and the sheet resistivity of each was determined. The results are given in Table I. Each value is the average of 100 samples.

TABLE I Anneal Temp. Resistivity (ohm/sq.) 7400 16.5 800 13.9 8000 10.9 8500 9.4 950 9.4 10000 8.3 For comparison purposes, resistivity was determined on samples of silicon layers of comparable thickness deposited by conventional LPCVD and doped by conventional diffusion using phosphorus oxychloride.

Groups of 100 samples were annealed for one hour at 9500 and 10000, respectively. The resistivity average at each temperature was 13.7 and 12.9 ohm/sq., respectively. It can be seen that comparable resistivity can be obtained with the subject method utilizing a substantially lower anneal temperature. This is a decided advantage in that it facilitates processing at lower temperatures which reduces the amount of phosphorus diffusion from the silicon layer.

In addition to the fact that the conventional diffusion doping process required a longer anneal period and introduced a significant level of chlorine ion contamination into the silicon layer, there is the problem of the layer of oxide that forms on the silicon surface due to the oxygen content of phosphorus oxychloride. This is conventionally removed by immersion in buffered HF for up to 45 additional minutes. The advantages of the subject process are demonstrated by these results.

EXAMPLE 2 Referring to FIG. 1 and utilizing a suitable mask, silicon substrates were ion implanted with suitable impurities to form source and drain regions 14. The substrate was photolithographically masked and the exposed areas of the surface locally oxidized to form thick deposits 'of field oxide 16. The mask was removed and a layer of high purity gate oxide 12 was grown on the substrate to a thickness of 50 nm by oxidizing in steam at 8000. A layer of silicon 37.5 nm thick was then deposited over the structure as in Example 1.

As a control, a layer of silicon was deposited and doped over a similar structure by conventional diffusion as in Example 1. The silicon layers on all substrates were lithographically patterned to form isolated gate structures 18, thus forming a polycrystalline silicon gate capacitor.

The threshold voltage of the capacitors was determined. All capacitors were subjected to one megarad of radiation in a Gamma Cell Cobalt 60 radiation source.

In such devices, radiation is known to cause a positive charge build up in the gate oxide layer 12 close to the interface with the substrate 10. The accumulation of charge produced by irradiation will cause a shift, i.-e. an increase, in the threshold voltage required to cause current to flow between the source and drain regions 14.

Comparing the average of 24 devices tested, the difference (delta) in threshold voltage for devices prepared by conventional diffusion doping was about two and one-half times that for devices prepared according to the subject process.

Claims (10)

CLAIMS:

1. A process of forming a semiconductor device comprising, in part, the steps of depositing a layer of phosphorus-doped silicon in the amorphorous state on a substrate by low pressure chemical vapor deposition from a mixture of silane, phosphine and a carrier gas and annealing the layer to convert it to the polycrystalline state, wherein the deposition of said layer is performed in an isothermal reactor from a mixture containing, for each part by volume of silane, from about 16 X 10 4 to about 17 X 10 4 part by volume of phosphine.

2. A process in accordance with Claim 1, wherein the mixture contains about 16.6 X 10 4 part by volume of phosphine for each part of silane.

3. A process in accordance with Claim 1, wherein the carrier gas is hydrogen.

4. A process in accordance with Claim 1, wherein the carrier gas is nitrogen.

5. A process in accordance with Claim 1, wherein the layer of silicon is deposited at a temperature of from about 5600 to 5750C.

6. A process in accordance with Claim 5, wherein the layer is deposited at a temperature of about 5650C.

7. X process in accordance with Claim 1, wherein the layer is annealed at a temperature of from about 8000 to 10000C.

8. A semiconductor device containing one or more layers of phosphorus-doped polycrystalline silicon, formed in the amorphous state by low pressure chemical vapor deposition in an isothermal reactor from a mixture of silane, phosphine and a carrier gas containing for each part by volume of silane, from about 16 X 10 -4 to about 17 X 10 part by volume of phosphine and annealed to convert them to the polycrystalline state.

9. A device in accordance with Claim 8, wherein the mixture contained about 16.6 X 10-4 part by volume of phosphine for each part by volume of silane.

10. The provision in a semiconductor device, of a layer of phosphorus-doped polycrystalline silicon made by an improved method substantially as hereinbefore described with reference to the accompanying drawing.