CN117012649A

CN117012649A - Trench MOSFET (Metal-oxide-semiconductor field Effect transistor) capable of reducing on-resistance based on P-type epitaxy and preparation method

Info

Publication number: CN117012649A
Application number: CN202311252110.2A
Authority: CN
Inventors: 黄伟宗
Original assignee: Shenzhen Sirius Semiconductor Co ltd
Current assignee: Shenzhen Sirius Semiconductor Co ltd
Priority date: 2023-09-26
Filing date: 2023-09-26
Publication date: 2023-11-07

Abstract

The invention provides a trench MOSFET for reducing on-resistance based on P-type epitaxy and a preparation method thereof, belonging to the technical field of semiconductors, wherein the method comprises the following steps: forming a body region above the drift region by adopting an epitaxial process; forming a source region by ion implantation on the upper layer of the body region; etching a through hole in the body region and the source region, and etching a groove in the upper layer of the drift region, wherein the through hole is connected with the groove; a drain is deposited under the substrate, a source is deposited over the source region, and a gate is deposited in the trench. According to the invention, the epitaxial process is used for forming the body region instead of an ion implantation and diffusion method in the prior art, and the epitaxial process can accurately control the depth of the body region, so that the channel length is effectively shortened, the channel resistance can be reduced, the doping ions of the channel can be uniformly distributed, the on-resistance of the trench MOSFET is effectively reduced, and the electrical performance of the trench MOSFET is improved.

Description

Trench MOSFET (Metal-oxide-semiconductor field Effect transistor) capable of reducing on-resistance based on P-type epitaxy and preparation method

Technical Field

The invention relates to the technical field of semiconductors, in particular to a trench MOSFET (metal oxide semiconductor field effect transistor) capable of reducing on-resistance based on P-type epitaxy and a preparation method thereof.

Background

The third-generation semiconductor material silicon carbide has the characteristics of wide band gap, high breakdown field intensity, high heat conductivity, high saturated electron migration rate, stable physical and chemical properties and the like, and can be suitable for high-temperature, high-frequency, high-power and extreme environments. Silicon carbide has a larger forbidden bandwidth and a higher critical breakdown field strength. Compared with a silicon power device under the same condition, the withstand voltage degree of the silicon carbide device is about 10 times of that of a silicon material. The silicon carbide device has higher electron saturation rate, small forward on-resistance and lower power loss, is suitable for large-current and large-power application, and reduces the requirement on heat radiation equipment. MOSFETs made of silicon carbide material are a field effect transistor that can be widely used in analog and digital circuits. MOSFETs can be classified as "N-type" and "P-type" MOSFETs, depending on the polarity of their "channel," and are commonly referred to as NMOSFETs and PMOSFETs.

The majority carriers in an N-type semiconductor drift from the source to the drain through the N-type semiconductor, which forms a channel of free electrons or current, called a "channel". The resistance of the channel is controlled by the internal electric field of the PN junction between the P-type gate and the N-type channel because the current is formed by the drift of the majority carriers in the N-type semiconductor. The effect of channel resistance on the MOSFET is mainly: the channel resistance affects the switching characteristics of the MOSFET. Channel resistance is an internal dissipation of a MOSFET when turned off, which reduces the energy available to the MOSFET when turned off, making the MOSFET more susceptible to failure when turned on. Therefore, reducing the channel resistance can improve the switching characteristics of the MOSFET. Channel resistance affects power output capability. As the channel resistance increases, the power output capability also decreases. Therefore, if the MOSFET is to be made to exert the maximum power output capability, the channel resistance should be kept as low as possible. The forward conduction characteristics are also affected. As the channel resistance increases, the forward conduction saturation decreases. This means that the channel resistance must be made as low as possible if it is desired to ensure good forward conduction characteristics of the MOSFET.

The channel resistance is a key factor affecting the on resistance of the low-voltage trench MOSFET device, and the current channel forming method is to form a body region by utilizing ion implantation and diffusion, but is limited by a process technology, the channel length cannot be effectively reduced, and the channel length and the doping concentration are unevenly distributed on a chip, so that the on resistance is improved, and the electrical performance of the trench MOSFET is reduced.

Disclosure of Invention

The invention aims to provide a trench MOSFET based on P-type epitaxy for reducing on-resistance and a preparation method thereof.

A preparation method of a trench MOSFET for reducing on-resistance based on P-type epitaxy comprises the following steps:

forming a body region above the drift region by adopting an epitaxial process;

forming a source region by ion implantation on the upper layer of the body region;

etching a through hole in the body region and the source region, and etching a groove in the upper layer of the drift region, wherein the through hole is connected with the groove;

a drain is deposited under the substrate, a source is deposited over the source region, and a gate is deposited in the trench.

Preferably, the forming the body region above the drift region by using an epitaxial process specifically includes:

filling reaction gas into a reaction chamber according to a preset flow rate, adjusting the temperature in the reaction chamber to a preset temperature, and adjusting the pressure in the reaction chamber to a preset pressure;

the reaction gas reacts on the surface of the drift region to form a body region film;

and stopping the reaction after the body area film grows to a preset value.

Preferably, stopping the reaction after the body region film grows to a preset value specifically comprises: when the body region film grows to 0.1-2um, the reaction gas stops filling the reaction chamber.

Preferably, the adjusting the temperature in the reaction chamber to a preset temperature specifically includes: the temperature in the reaction chamber was adjusted to 950-1150 ℃.

Preferably, the reaction gas includes: h ₂ 、N ₂ 、CH ₄ 、O ₂ And SiH ₄ 。

Preferably, the adjusting the pressure in the reaction chamber to a preset pressure specifically includes: the pressure in the reaction chamber was adjusted to 101.325KPa.

Preferably, the thickness of the body region is 0.1-2um.

Preferably, the doping concentration of the body region is 1×10 ¹⁴ -1×10 ¹⁷ cm ^-3 。

Preferably, before the forming the body region above the drift region by using an epitaxial process, the method further comprises: a drift region is epitaxially formed over the substrate.

A P-type epitaxial reduced on-resistance trench MOSFET comprising: a substrate, a drift region, a body region, a source, a drain and a gate;

the drain is deposited under the substrate;

the substrate is positioned below the drift region;

the drift region is located below the body region;

the body region is located below the source region;

the source electrode is deposited above the source electrode region;

the gate is deposited in the trench.

In the prior art, when the trench MOSFET is manufactured, the trench is etched in the drift region, then the body region and the source region are formed by ion implantation in the drift region, finally, the trench MOSFET is formed by depositing an electrode, in the ion implantation process, the channel length cannot be effectively reduced, the channel length and the doping concentration are unevenly distributed on a chip, so that the on-resistance is greatly improved, the device performance of the trench MOSFET is reduced, and in order to overcome the defects in the prior art, the epitaxial process is adopted to replace the traditional ion implantation method to form the body region, and because the epitaxial process can accurately control the depth of the body region, the channel length is effectively reduced, the channel resistance is reduced, and the channel doping concentration distribution is better. The body region formed by adopting the epitaxial process can effectively reduce the on-resistance of the groove MOEFST and improve the device performance of the groove MOSFET.

Drawings

The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate embodiments consistent with the invention and together with the description, serve to explain the principles of the invention.

In order to more clearly illustrate the embodiments of the invention or the technical solutions of the prior art, the drawings which are used in the description of the embodiments or the prior art will be briefly described, and it will be obvious to a person skilled in the art that other drawings can be obtained from these drawings without inventive effort.

FIG. 1 is a schematic diagram of a process flow for fabricating a trench MOSFET according to the present invention;

FIG. 2 is a schematic diagram of a trench MOSFET manufacturing process according to the present invention;

fig. 3 is a schematic diagram of a trench MOSFET structure according to the present invention.

Detailed Description

The following description of the embodiments of the present invention will be made clearly and fully with reference to the accompanying drawings, in which it is evident that the embodiments described are only some, but not all embodiments of the invention. All other embodiments, which can be made by those skilled in the art based on the embodiments of the invention without making any inventive effort, are intended to be within the scope of the invention.

It should be noted that all directional indicators (such as up, down, left, right, front, and rear … …) in the embodiments of the present invention are merely used to explain the relative positional relationship, movement, etc. between the components in a particular posture (as shown in the drawings), and if the particular posture is changed, the directional indicator is changed accordingly.

Furthermore, the description of "first," "second," etc. in this disclosure is for descriptive purposes only and is not to be construed as indicating or implying a relative importance or implicitly indicating the number of technical features indicated. Thus, a feature defining "a first" or "a second" may explicitly or implicitly include at least one such feature. In addition, the technical solutions of the embodiments may be combined with each other, but it is necessary to base that the technical solutions can be realized by those skilled in the art, and when the technical solutions are contradictory or cannot be realized, the combination of the technical solutions should be considered to be absent and not within the scope of protection claimed in the present invention.

Example 1

A method for manufacturing a trench MOSFET based on P-type epitaxy to reduce on-resistance, referring to FIGS. 1 and 2, comprises the following steps:

s100, forming a body region above the drift region by adopting an epitaxial process;

in the epitaxial process, a chemical vapor deposition method is generally adopted to perform body region growth, and in the process of body region growth, the temperature in a reaction chamber, the concentration and gas components of a reaction gas, the flow rate of the reaction gas and the pressure in the reaction chamber can influence the generation rate and quality of the body region, and a trench MOSFET meeting the market requirements can be grown only by strictly controlling the above main parameters.

Chemical vapor deposition is a technique used in the semiconductor industry to deposit a wide variety of materials, including a wide range of insulating materials, most goldBelonging to materials and metal alloy materials. Chemical vapor deposition is a process in which two or more gaseous starting materials are introduced into a reaction chamber, and then the reactants chemically react with each other to form a new material that is deposited onto the wafer surface. Such as: deposition of silicon nitride film (Si ₃ N ₄ ) Is formed by the reaction of silane and nitrogen. Chemical vapor deposition is a technique for preparing semiconductor crystal thin films in bulk regions, and the principle is that gaseous precursor reactants are utilized to decompose certain components in the gaseous precursor through chemical reaction between atoms and molecules so as to form the thin films on a substrate. Chemical vapor deposition includes Plasma Enhanced Chemical Vapor Deposition (PECVD), ultra-high vacuum chemical vapor deposition (UHV CVD), microwave Plasma Chemical Vapor Deposition (MPCVD), low Pressure Chemical Vapor Deposition (LPCVD), thermal Chemical Vapor Deposition (TCVD), and the like.

Plasma enhanced chemical vapor deposition: plasma enhanced chemical vapor deposition is a method of performing epitaxy by exciting a gas in chemical vapor deposition to generate low-temperature plasma and enhance chemical activity of a reactant substance. The method can form a solid film at a lower temperature. For example, a substrate material is placed on a cathode in a reaction chamber, reaction gas is introduced to lower pressure (1-600 Pa), the substrate is kept at a certain temperature, glow discharge is generated in a certain mode, gas near the surface of the substrate is ionized, the reaction gas is activated, and cathode sputtering is generated on the surface of the substrate, so that the surface activity is improved. There are not only usual thermochemical reactions but also complex plasma chemical reactions on the surface. The deposited film is formed by the combined action of the two chemical reactions. The method for igniting glow discharge mainly comprises the following steps: radio frequency excitation, direct current high voltage excitation, pulse excitation and microwave excitation. The plasma enhanced chemical vapor deposition has the main advantages of low deposition temperature and small influence on the structure and physical properties of the matrix; the thickness and the component uniformity of the film are good; the membrane tissue is compact and the pinholes are few; the adhesive force of the film layer is strong; the application range is wide.

Microwave plasma chemical vapor deposition: the microwave plasma chemical vapor deposition technology is suitable for preparing the high-quality hard film and the crystal with large area, good uniformity, high purity and good crystal form. Microwave plasma chemical vapor deposition is one of the effective means for preparing large-size single crystals. The method uses electromagnetic wave energy to excite the reactant gases. The plasma is pure due to electrodeless discharge, and meanwhile, the discharge area of the microwave is concentrated but not expanded, so that various atomic groups such as atomic hydrogen and the like can be activated and generated, the maximum kinetic energy of the generated ions is low, and the generated crystals cannot be corroded. By adjusting the structure of the microwave plasma chemical vapor deposition reaction chamber structure, a large-area and stable plasma ball can be generated in the deposition cavity, so that the large-area and uniform deposition of crystals is facilitated, and the superiority of the microwave plasma method for preparing the large-size single crystal film is quite outstanding in all preparation methods.

Ultra-high vacuum chemical vapor deposition: the ultra-high vacuum chemical vapor deposition is used for preparing high-quality submicron crystal films, nano-structure materials and film technologies for developing silicon-based high-speed high-frequency devices and nano-electronic devices. Ultra-high vacuum chemical vapor deposition technique is below 10 ^-6 Pa(10 ^-8 Torr) is suitable for depositing a single crystal thin film on a surface of a substrate having high chemical activity. Unlike conventional vapor phase epitaxy, the ultra-high vacuum chemical vapor deposition technology adopts low-pressure and low-temperature growth, can effectively reduce solid diffusion of doping sources, and inhibits three-dimensional growth of epitaxial films. The ultra-high vacuum of the ultra-high vacuum chemical vapor deposition system reactor avoids oxidation of the surface of the Si substrate and effectively reduces impurity doping into the grown film generated by the reaction gas. Under the ultra-high vacuum condition, the reaction gas molecules can be directly transmitted to the surface of the substrate, the diffusion of the reaction gas and the complex interaction among the molecules do not exist, and the deposition process mainly depends on the reaction of a gas-solid interface. In conventional vapor phase epitaxy, the diffusion of vapor phase precursors through the boundary layer to the substrate surface determines the growth rate of the epitaxial film. The ultrahigh vacuum enables the gas phase precursor molecules to directly impact the surface of the substrate, and the growth of the film is mainly controlled by chemical reaction of the surface. Thus, the vapor phase precursor silane or germane component of all the substrate (substrate) surfaces on the supportThe sub-flows are all the same, and epitaxial growth can be realized on multiple substrates at the same time.

Low pressure chemical vapor deposition: the operating pressure of the reaction gas in the reactor during the deposition reaction is reduced to a chemical vapor deposition reaction of about 133Pa or less. The low pressure chemical vapor deposition pressure is reduced to below 133Pa, and accordingly, the free range and gas diffusion coefficient of molecules are increased, so that the mass transmission rate of gaseous reactants and byproducts is increased, the reaction rate of forming a film is increased, even if the distance between substrates placed in parallel and vertically is reduced to 5-10 mm, the mass transmission limit is not considered compared with the chemical reaction rate of the surfaces of the substrates, thereby creating conditions for vertically and densely packing the substrates and greatly improving the packing amount of each batch. The thin film deposited by the low pressure chemical vapor deposition method has better step coverage capability, better composition and structure control, and higher deposition rate and output. Furthermore, low pressure chemical vapor deposition does not require carrier gas, thereby greatly reducing the particle pollution source, and is widely used in the semiconductor industry with high added value for film deposition.

Thermal chemical vapor deposition: a method for vapor phase growth by using high temperature activated chemical reaction. Thermal chemical vapor deposition falls into several broad categories in terms of its chemical reaction forms: chemical transportation method: the constituent film materials react with another solid or liquid material in the source region to form a gas. Then the material is transported to a growth area at a certain temperature, the required material is generated through opposite thermal reaction, the positive reaction is the thermal reaction in the transportation process, and the reverse reaction is the thermal reaction in the crystal growth process. (2) pyrolysis: the film is produced by transferring volatile matter containing film elements to growth area and thermal decomposition reaction to produce required matter at 1000-1050 deg.c. (3) synthetic reaction method: several gaseous species react in the growth zone to form the grown species, chemical transport methods are commonly used for bulk crystal growth, decomposition reaction methods are commonly used for thin film material growth, and synthesis reaction rules are used in both cases. Thermal chemical vapor deposition is applied to semiconductor materials such as various oxides of Si, gaAs, and other materials.

In the embodiment of the invention, different epitaxial processes are required to be selected according to the requirements of the actual conditions on the parameters of the body region, for example, when the body region with larger area is required to be generated, a low-pressure chemical vapor deposition method can be adopted, and a large quantity of constituent MOSFETs with larger chip area can be produced in batches. When it is desired to produce microchips, ultra-high vacuum chemical vapor deposition may be used because it can produce high quality submicron crystalline films and nanostructured materials. In order to save the production cost, a thermal chemical vapor deposition method can be adopted, and because the reaction conditions required by the chemical vapor deposition method are easy to achieve, the products required by the reaction are easy to obtain, and the produced body region has good quality and is suitable for industrial production of most body region growth.

S200, forming a source region by ion implantation on the upper layer of the body region;

the invention adopts ion implantation to form a source region on the upper layer of the body region. The source region is formed after the formation of the body region, and in the embodiment of the present invention, the source region is an N-type heavily doped semiconductor formed by ion implantation of pentavalent ions such As nitrogen (N), phosphorus (P), arsenic (As), antimony (Sb), bismuth (Bi) and potassium (Mc) into the semiconductor. + is heavily doped (high doping concentration), -is lightly doped (low doping concentration), the P-type semiconductor is formed by ion implantation of trivalent ions in the semiconductor, for example: boron, aluminum, gallium, indium, thallium. The heavily doped N+ type semiconductor is adopted in the source electrode region, so that the resistivity of the semiconductor can be reduced, and good ohmic contact is formed between the heavily doped N+ type semiconductor and the metal electrode. Ion implantation is the emission of an ion beam in vacuum towards a solid material, which, after being directed towards the solid material, is slowly slowed down by the resistance of the solid material and finally stays in the solid material. Ions of one element are accelerated into a solid target, thereby altering the physical, chemical or electrical properties of the target. Ion implantation is commonly used in the fabrication of semiconductor devices, metal surface treatment, and materials science research. If the ions stop and remain in the target, the ions change the elemental composition of the target (if the ions differ from the composition of the target). The ion implantation beam line design includes a common set of functional elements. The main part of the ion beam line comprises an apparatus called ion source for generating ion species. The source is tightly coupled to a bias electrode to extract ions into the beam line and most commonly to some way of selecting a particular ion species for transmission into the main accelerator section. The "mass" selection is accompanied by the extracted ion beam passing through a region of the magnetic field whose exit path is limited by a blocked aperture or "slit" which allows only ions to have mass and velocity/charge to continue along the beam line. If the target surface is larger than the ion beam diameter and the implant dose is uniformly distributed over the target surface, some combination of beam scanning and wafer motion may be used. Finally, the implanted surface is combined with some method for collecting the accumulated charge of the implanted ions so that the delivered dose can be measured in a continuous manner and the implantation process stopped at the desired dose level.

Doping semiconductors with boron, phosphorus or arsenic is a common application of ion implantation. When implanted into a semiconductor, each doping atom may generate charge carriers in the semiconductor after annealing. A hole may be created for the P-type dopant and an electron may be created for the N-type dopant. The conductivity of the semiconductor near the doped region is changed.

S300, etching through holes in the body region and the source region, etching grooves in the upper layer of the drift region, and connecting the through holes with the grooves;

according to the invention, through holes are etched in the body region and the source region by a one-time etching method, grooves are etched in the upper layer of the drift region, and the through holes are connected with the grooves. Etching is a process of selectively removing unwanted material from the surface of a silicon wafer by chemical or physical means, and is a generic term for stripping and removing material by solution, reactive ions or other mechanical means. The etching technology is mainly divided into dry etching and wet etching. The dry etching mainly uses the reaction gas and the plasma for etching; the wet etching mainly uses chemical reagents to chemically react with the etched material for etching.

Ion beam etching is a physical dry etching process. Thereby, argon ions are irradiated onto the surface with an ion beam of about 1 to 3 keV. Due to the energy of the ions, they strike the material of the surface. The wafer is vertically or obliquely directed into the ion beam and the etching process is absolutely anisotropic. The selectivity is low because it is not different for each layer. The gas and abraded material are evacuated by the vacuum pump, but since the reaction products are not gaseous, particles can deposit on the wafer or chamber walls. All materials can be etched in this way and the wear on the vertical walls is low due to the vertical radiation.

Plasma etching is a chemical etching process and has the advantage that the wafer surface is not damaged by accelerated ions. The method is used to remove the entire film (e.g., backside cleaning after thermal oxidation) because the etch profile is isotropic due to the movable particles of the etch gas. One type of reactor used for plasma etching is a downstream reactor. So that the plasma is ignited at a high frequency of 2.45GHz by impact ionization, the location of which is separated from the wafer.

The etch rate depends on the pressure, the power of the high frequency generator, the process gas, the actual gas flow and the wafer temperature. Anisotropy increases with an increase in high-frequency power, a decrease in pressure, and a decrease in temperature. The uniformity of the etching process depends on the gas, the distance between the two electrodes and the material of the electrodes. If the distance is too small, the plasma cannot be unevenly dispersed, resulting in non-uniformity. If the distance of the electrodes is increased, the etch rate is reduced because the plasma is distributed in the enlarged volume. Carbon has proven to be the material of choice for electrodes. Since fluorine and chlorine also attack carbon, the electrodes produce a uniformly strained plasma and the wafer edge is affected by the same effect as the wafer center. The selectivity and etch rate are largely dependent on the process gas. For silicon and silicon compounds, fluorine gas and chlorine gas are mainly used.

S400, depositing a drain electrode below the substrate, depositing a source electrode above the source region, and depositing a grid electrode in the groove.

Metal electrode deposition processes are classified into Chemical Vapor Deposition (CVD) and Physical Vapor Deposition (PVD). Chemical vapor deposition refers to a process of depositing a coating on a wafer surface by chemical means, typically by applying energy to a gas mixture. Assuming that the substance (a) is deposited on the wafer surface, two gases (B and C) that can generate the substance (a) are first input to the deposition apparatus, and then energy is applied to the gases to cause the gases B and C to chemically react.

PVD (physical vapor deposition) coating techniques are mainly divided into three categories: vacuum evaporation coating, vacuum sputtering coating and vacuum ion coating. The main methods of physical vapor deposition are: vacuum evaporation, sputter coating, arc plasma coating, ion coating, molecular beam epitaxy, and the like. The corresponding vacuum coating equipment comprises a vacuum evaporation coating machine, a vacuum sputtering coating machine and a vacuum ion coating machine.

Chemical Vapor Deposition (CVD) and Physical Vapor Deposition (PVD) can be used as a means of depositing metal electrodes. In the embodiment of the invention, a chemical vapor deposition method is adopted to deposit the metal electrode, and the chemical vapor deposition process is divided into three stages: the reaction gas diffuses toward the surface of the substrate, the reaction gas is adsorbed on the surface of the substrate, and chemical reaction occurs on the surface of the substrate to form solid deposits, and the generated gas phase byproducts are separated from the surface of the substrate. The most common chemical vapor deposition reactions are thermal decomposition reactions, chemical synthesis reactions, chemical transport reactions, and the like. TiC or TiN is usually deposited by introducing TiCl into a reaction chamber at 850-1100 DEG C ₄ ，H ₂ ，CH ₄ And forming a coating layer on the surface of the substrate through chemical reaction of the gases.

The deposited grid adopts a polysilicon deposition method, namely, a grid electrode and local connection lines are formed on the silicide stack on the first layer of polysilicon (Poly 1), and the second layer of polysilicon (Poly 2) forms contact plugs between the source electrode/drain electrode and the unit connection lines. The silicide is stacked on the third layer polysilicon (Poly 3) to form a cell connection, and the fourth layer polysilicon (Poly 4) and the fifth layer polysilicon (Poly 5) form two electrodes of the storage capacitor with a dielectric medium with high dielectric coefficient sandwiched therebetween. To maintain the desired capacitance value, the size of the capacitor may be reduced by using a dielectric with a high dielectric coefficient. Polysilicon deposition is a Low Pressure Chemical Vapor Deposition (LPCVD) process by depositing three species in a reaction chamber (i.e., in a furnace tube)Arsenic Hydride (AH) ₃ ) Phosphorus trihydride (PH) ₃ ) Or diborane (B) ₂ H ₆ ) The doping gas of the silicon material is directly input into the silicon material gas of silane or DCS, so that the polysilicon doping process of the in-situ low-pressure chemical vapor deposition can be performed. Polysilicon deposition is performed at low pressure conditions of 0.2-1.0Torr and deposition temperatures between 600 and 650 ℃ using pure silane or silane diluted with nitrogen to a purity of 20% to 30%. The deposition rate of both deposition processes is between 100-200 a/min, which is determined primarily by the temperature at which the deposition is performed.

The formation of the body region above the drift region by an epitaxial process is specifically:

filling reaction gas into a reaction chamber according to a preset flow rate, adjusting the temperature in the reaction chamber to a preset temperature, and adjusting the pressure to a preset pressure;

reactants enter the reaction chamber in gaseous form and are activated within the reaction chamber. The activation mode comprises the following steps: heating, plasma, or a combination of heating and plasma. Therefore, the temperature and pressure in the reaction chamber need to be regulated to a preset value to improve the reaction rate, so that a product with better quality can be obtained more quickly.

the activated reactants react at the substrate surface (drift region surface) to form a thin film. The reactions that occur include: oxidation, reduction, deposition, and the like.

And stopping the reaction after the body area film grows to a preset value.

After the film starts to grow, reactants are continuously filled into the reaction chamber to react with the surface of the substrate, so that a thin sheet is formed. The growth rate of the flakes is affected by the reaction conditions and the concentration of the reactants. The reactant concentration is higher in a certain range, the growth rate of the thin sheet is faster, when the reactant concentration exceeds the maximum value, side reactions can occur, a large amount of byproducts are generated, raw materials are wasted, and the quality of crystals is reduced.

Stopping the reaction after the body area film grows to a preset value specifically comprises the following steps: when the body region film grows to 0.1-2um, the reaction gas stops filling the reaction chamber.

The thickness of the body region of the trench MOSFET of different types is different, the thickness of the body region is 0.1-2um, the thickness generated by the body region can be controlled by controlling the reaction according to the actual production requirement, and the thickness of the body region is easy to control in the epitaxial process, but in the ion implantation process, the thickness of the body region is often difficult to control due to the diffusion effect, the ion concentration of the body region is also easy to be unevenly distributed, so that the on-resistance of the finally generated trench MOSFET is very large, and the requirement of industrial production is not met. Therefore, the epitaxy process is adopted to replace the traditional ion implantation method to generate the body region, and good electrical performance improvement can be achieved with lower production cost. As a preferred embodiment, the invention stops the gas filling and reduces the temperature to terminate the reaction when the body region film grows to 0.5 um.

The adjusting the temperature in the reaction chamber to a preset temperature specifically includes: the temperature in the reaction chamber was adjusted to 950-1150 ℃.

The reaction temperature is an important parameter in the epitaxial process, and needs to be strictly controlled, in the embodiment of the invention, the temperature in the reaction chamber is controlled to be 1000 ℃, so that the reaction gas can react with the substrate more quickly, crystals are deposited, and the chemical activity of the reactant can be increased by high temperature, so that the reaction is easier to occur.

The reaction gas includes: h ₂ 、N ₂ 、CH ₄ 、O ₂ And SiH ₄ 。

The reactive species of the chemical vapor deposition reaction generally include gaseous, liquid, solid, etc., and common reactive species include oxygen, chlorides, hydrides, organometals, metal oxides, etc. Different reactive species have different chemical properties and therefore play different roles in the reaction mechanism. For example, oxygen may provide oxygen atoms in the reaction, acting as an oxidation reaction; the organic metal can provide metal atoms to perform the reduction reaction. The reactants used in the chemical vapor deposition reaction must have extremely high purity because any impurities are eventually incorporated into the deposited film. These impurities can cause uncontrolled changes in thin film material properties, which can be detrimental to device performance.By H ₂ 、N ₂ 、CH ₄ 、O ₂ And SiH ₄ As a gaseous material source in the epitaxy process, production costs can be saved because of H ₂ 、N ₂ 、CH ₄ 、O ₂ And SiH ₄ The method is easy to obtain, has stable physicochemical properties, has mature equipment in process production, can obtain high-quality body region components with higher yield, ensures that the ion concentration in the produced body region is uniform, the surface is flat, the structure is stable, and can greatly improve the device performance of the trench MOSFET.

The adjusting the pressure in the reaction chamber to a preset pressure specifically comprises: the pressure in the reaction chamber was adjusted to 101.325KPa.

In the embodiment of the invention, the pressure in the reaction chamber is controlled at the atmospheric pressure to react, the capability of high deposition rate and thick coating can be obtained without ultrahigh vacuum in the process of depositing the body region, and the production cost can be saved.

The thickness of the body region is 0.1-2um.

The thickness of the body region of the trench MOSFET of different types is different, the thickness of the body region is 0.1-2um, the thickness generated by the body region can be controlled by controlling the reaction according to the actual production requirement, and the thickness of the body region is easy to control in the epitaxial process, but in the ion implantation process, the thickness of the body region is often difficult to control due to the diffusion effect, the ion concentration of the body region is also easy to be unevenly distributed, so that the on-resistance of the finally generated trench MOSFET is very large, and the requirement of industrial production is not met. Therefore, the epitaxy process is adopted to replace the traditional ion implantation method to generate the body region, and good electrical performance improvement can be achieved with lower production cost. As a preferred embodiment, the present invention stops the gas filling and reduces the temperature in the reaction chamber to terminate the reaction when the body region film grows to 0.5 um.

The doping concentration of the body region is 1×10 ¹⁴ -1×10 ¹⁷ cm ^-3 。

The doping concentration of the body region is light doping, and the ion concentration range is 1 multiplied by 10 ¹⁴ -1×10 ¹⁷ cm ^-3 . As a bestIn an alternative embodiment, the invention sets the doping concentration of the body region to be 1×10 ¹⁶ cm ^-3 . The body region with uniform doping concentration distribution can conduct electricity better, and the on-resistance is reduced.

Before forming the body region above the drift region using an epitaxial process, the method further comprises: a drift region is epitaxially formed over the substrate.

The drift region of the semiconductor device refers to a region in the semiconductor device in which current is transferred within the drift region. The drift region is one of the most important parts of a semiconductor device, and directly affects the performance and operation of the device. In semiconductor devices, the drift region is typically formed of a doped material. Doping refers to the introduction of impurity atoms into a semiconductor crystal to alter its conductive properties. In the drift region, the type and concentration of the doping material determine the current transport characteristics. The main function of the drift region is to provide a channel for current transport. When an applied voltage is applied to the semiconductor device, the charge in the drift region is moved by the electric field force. This movement forms the transmission of current. The width and length of the drift region determine the current transmission speed and efficiency.

In semiconductor devices, the design and optimization of the drift region is very important. First, the width and length of the drift region need to be reasonably selected according to the requirements of the device. If the drift region is too narrow or too short, the current transfer rate may be limited, affecting the device performance. If the drift region is too wide or too long, the size and power consumption of the device may be increased, reducing the efficiency of the device. Secondly, the choice of doping material and the control of the concentration of the drift region are also critical. Different doping materials have different conductive properties and can be used to implement different device functions. The concentration of the doping material determines the conductivity of the drift region, and too high or too low a concentration can affect the device performance.

Example 2

A P-type epitaxial reduced on-resistance trench MOSFET, referring to fig. 3, comprising: a substrate, a drift region, a body region, a source, a drain and a gate;

the drain electrode is deposited below the substrate;

the drain is the charge sink in the MOSFET, which is connected to the channel and is the charge sink. When the MOSFET is in a conducting state, a conducting path is formed between the drain electrode and the source electrode, electrons flow into the drain electrode from the source electrode, and current transmission is completed. The voltage change of the drain electrode has little influence on the working state of the MOSFET, and mainly plays a role in current inflow.

The substrate is positioned below the drift region;

the electric field distribution of the drift region plays a key role in the on-characteristics and current control of the MOSFET. When a gate voltage is applied to the MOSFET, the electric field distribution in the drift region is modulated by the gate voltage, thereby controlling the flow of current between the source and drain. During operation of the MOSFET, current between the source and drain is transferred primarily through the drift region. The doping type and concentration of the drift region determine the conduction type (N-type or P-type) and the magnitude of the current. The structure and characteristics of the drift region directly influence the current control capability of the MOS transistor. By adjusting the shape, size and doping concentration of the drift region, accurate control of current can be achieved, thereby meeting the requirements of different applications.

The drift region is positioned below the body region;

the body region is used to form the channel of the MOSFET, and the doping concentration of the body region affects the on-resistance of the MOSFET.

The body region is positioned below the source region;

the source region is connected with the source electrode and is a high-concentration doped semiconductor region, has lower resistivity and forms ohmic contact with the metal electrode. The contact surface of the metal and the semiconductor is classified into two types of schottky contact and ohmic contact. Ohmic contacts are low barrier layers formed when a semiconductor with high doping concentration is contacted with a metal when the semiconductor is high in doping concentration, electrons can pass through the barrier layers by means of tunneling effect, and therefore low-resistance ohmic contacts are formed.

A source electrode is deposited above the source electrode region;

the source is the source of charge in the MOSFET and is the exit of the charge. When the MOSFET is in a conducting state, a conducting path is formed between the source electrode and the drain electrode, electrons flow into the drain electrode from the source electrode, and current transmission is completed. Meanwhile, the source electrode also plays a role of modulating the grid voltage, and the control of the MOSFET is realized by controlling the change of the source electrode voltage.

A gate is deposited in the trench.

The gate is the control electrode in the MOSFET, and is separated from the channel by an insulating layer, which is a critical part of the MOSFET. The voltage variation of the gate can change the charge density in the channel, thereby controlling the magnitude of the current between the drain and the source.

The foregoing is only a specific embodiment of the invention to enable those skilled in the art to understand or practice the invention. Various modifications to these embodiments will be readily apparent to those skilled in the art, and the generic principles defined herein may be applied to other embodiments without departing from the spirit or scope of the invention. Thus, the present invention is not intended to be limited to the embodiments shown herein but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.

Claims

1. The preparation method of the trench MOSFET based on the P-type epitaxy for reducing the on-resistance is characterized by comprising the following steps of:

forming a body region above the drift region by adopting an epitaxial process;

2. The method for manufacturing a trench MOSFET with reduced on-resistance based on P-type epitaxy as claimed in claim 1, wherein forming a body region above a drift region by epitaxy process specifically comprises:

and stopping the reaction after the body area film grows to a preset value.

3. The method for manufacturing a trench MOSFET according to claim 2, wherein stopping the reaction after the body film grows to a predetermined value specifically comprises: when the body region film grows to 0.1-2um, the reaction gas stops filling the reaction chamber.

4. The method for fabricating a trench MOSFET with reduced on-resistance based on P-type epitaxy of claim 2, wherein the adjusting the temperature in the reaction chamber to a predetermined temperature specifically comprises: the temperature in the reaction chamber was adjusted to 950-1150 ℃.

5. The method for manufacturing a P-type epitaxial reduced on-resistance trench MOSFET according to claim 2, wherein the reactive gas comprises: h ₂ 、N ₂ 、CH ₄ 、O ₂ And SiH ₄ 。

6. The method for fabricating a trench MOSFET with reduced on-resistance based on P-type epitaxy of claim 2, wherein the adjusting the pressure in the reaction chamber to a predetermined pressure specifically comprises: the pressure in the reaction chamber was adjusted to 101.325KPa.

7. The method for manufacturing a P-type epitaxial reduced on-resistance trench MOSFET according to claim 1, wherein the thickness of the body region is 0.1-2um.

8. The method for manufacturing a trench MOSFET with reduced on-resistance based on P-type epitaxy as claimed in claim 1, wherein the doping concentration of the body region is 1×10 ¹⁴ -1×10 ¹⁷ cm ^-3 。

9. The method for fabricating a P-type epitaxial reduced on-resistance trench MOSFET of claim 1, further comprising, prior to forming a body region over a drift region using an epitaxial process: a drift region is epitaxially formed over the substrate.