KR100585849B1 - Flash Memory Device Comprising Floating Gate Utilizing Nanocrystals Embeded In Polymer Thin Film And Fabrication Method Thereof - Google Patents
Flash Memory Device Comprising Floating Gate Utilizing Nanocrystals Embeded In Polymer Thin Film And Fabrication Method Thereof Download PDFInfo
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- KR100585849B1 KR100585849B1 KR1020040021073A KR20040021073A KR100585849B1 KR 100585849 B1 KR100585849 B1 KR 100585849B1 KR 1020040021073 A KR1020040021073 A KR 1020040021073A KR 20040021073 A KR20040021073 A KR 20040021073A KR 100585849 B1 KR100585849 B1 KR 100585849B1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/823437—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type with a particular manufacturing method of the gate conductors, e.g. particular materials, shapes
-
- B—PERFORMING OPERATIONS; TRANSPORTING
- B82—NANOTECHNOLOGY
- B82Y—SPECIFIC USES OR APPLICATIONS OF NANOSTRUCTURES; MEASUREMENT OR ANALYSIS OF NANOSTRUCTURES; MANUFACTURE OR TREATMENT OF NANOSTRUCTURES
- B82Y10/00—Nanotechnology for information processing, storage or transmission, e.g. quantum computing or single electron logic
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66825—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a floating gate
Abstract
본 발명은 고분자 박막 내에 자발형성된 금속 또는 금속산화물 나노결정체를 이용한 나노 플로팅 게이트를 갖는 고효율 저비용의 플래쉬 메모리 소자 및 그 제조방법에 관한 것으로 종래의 플래쉬 메모리 소자의 나노 결정체의 형성과정보다 매우 간단하게 나노 결정체를 형성할 수 있으며 전체적으로 균일한 분포를 가지는 결정체들이 고분자층으로 둘러쌓여있어 결정체의 응집현상 없이 나노 결정체의 크기나 밀도를 제어할 수 있으며 종래의 나노 플로팅 게이트보다 전기적으로나 화학적으로 안정성을 갖는 나노 플로팅 게이트를 이용함으로써 고효율 저비용의 나노 플로팅 게이트의 메모리 소자 및 그 제조방법을 제공하는 효과가 있다.The present invention relates to a highly efficient low-cost flash memory device having a nano-floating gate using a metal or metal oxide nanocrystals spontaneously formed in a polymer thin film and a method of manufacturing the same. Crystals that can form crystals and have a uniform distribution as a whole are surrounded by a polymer layer to control the size or density of nanocrystals without agglomeration of crystals, and have more electrical or chemical stability than conventional nano floating gates. By using the floating gate, there is an effect of providing a memory device of a nano floating gate having high efficiency and a manufacturing method thereof.
플래시 메모리, 나노 결정체, 플로팅 게이트, 고분자 박막, 폴리이미드 박막Flash Memory, Nano Crystal, Floating Gate, Polymer Thin Film, Polyimide Thin Film
Description
도 1은 폴리이미드 내에 형성된 나노 결정체를 이용한 나노 플로팅 게이트를 가지는 플래쉬 메모리 소자의 개략도이다.1 is a schematic diagram of a flash memory device having a nano floating gate using nano crystals formed in a polyimide.
도 2는 폴리이미드 박막 내에 나노 결정체로 형성된 ZnO 나노 결정체의 투과전자현미경 사진이다.2 is a transmission electron micrograph of ZnO nanocrystals formed of nanocrystals in a polyimide thin film.
도 3은 ZnO 나노 결정체가 내재된 폴리이미드 박막 단면의 투과전자현미경 사진이다.3 is a transmission electron micrograph of a cross section of a polyimide thin film containing ZnO nanocrystals.
도 4는 폴리이미드 박막 내에 나노 결정체로 형성된 Cu2O 나노 결정체의 투과전자현미경 사진이다.4 is a transmission electron micrograph of Cu 2 O nanocrystals formed of nanocrystals in a polyimide thin film.
*도면의 주요부분에 대한 부호의 설명** Description of the symbols for the main parts of the drawings *
100:반도체 기판 110:플로팅 게이트 전극 111:금속산화물 나노결정체DESCRIPTION OF SYMBOLS 100: Semiconductor substrate 110: Floating gate electrode 111: Metal oxide nanocrystals
121:소스영역 122:드레인 영역 130:콘트롤 게이트121: source region 122: drain region 130: control gate
본 발명은 나노 플로팅 게이트를 갖는 플래쉬 메모리 소자 및 그 제조방법에 관한 것으로, 보다 상세하게는, 고분자 박막 내에 자발형성된 나노결정체를 이용한 나노 플로팅 게이트를 갖는 고효율 저비용의 플래쉬 메모리 소자 및 그 제조방법에 관한 것이다.The present invention relates to a flash memory device having a nano-floating gate and a method of manufacturing the same, and more particularly, to a high-efficiency low-cost flash memory device having a nano-floating gate using nanocrystals spontaneously formed in a polymer thin film and a method of manufacturing the same will be.
최근 절연체로 현재 주로 사용되고 있는 SiO2를 대체할 새로운 물질들의 개발이 요구되어지고 있다. 그 중에서도 기존의 무기절연재료를 대체할 물질로 유기 절연재료인 폴리이미드가 등장하게 되었다. 폴리이미드는 독특한 열적, 기계적, 유전적 특성 때문에 집적회로의 절연 중간층, 고밀도 연결소자 패키지를 포함한 여러 분야의 초정밀 전자 공업에서 광범위하게 사용되고 있다. 특히, 폴리이미드의 유전율은 기존 무기재료에 비해 낮은 것으로 알려져 있다. Recently, development of new materials to replace SiO 2 , which is mainly used as an insulator, is required. Among them, polyimide, an organic insulating material, has emerged as a material to replace the existing inorganic insulating material. Because of their unique thermal, mechanical, and dielectric properties, polyimides are widely used in the high-precision electronics industry in many fields, including insulated interlayers of integrated circuits and high-density interconnect package. In particular, the dielectric constant of polyimide is known to be lower than that of conventional inorganic materials.
한편, 플래쉬 메모리는 EPROM(Erasable Programmable ROM)의 작은 셀면적과 EEPROM(Electrically Erasable Programmable ROM)의 전기적 소거가 가능하다는 장점을 조합하여 개발된 것으로 EEPROM과 달리 블록단위로 내용을 지울 수도 있고, 다시 프로그램이 가능하여 수정이 쉽고 속도가 빠른 장점을 가지고 있다.Flash memory, on the other hand, was developed by combining the advantages of small cell area of erasable programmable ROM (EPROM) and electrically erasing of electrically erasable programmable ROM (EEPROM). Unlike EEPROM, flash memory can be erased and reprogrammed. This has the advantage of being easy to modify and fast.
이러한 플래쉬 메모리는 현재의 메인보드 상의 바이오스용으로 많이 사용되 고 있으며, 이동전화기, 위성박스, 디지털카메라, DVD, MP3 플레이어, 게임기 등과 같은 전자 기기에 널리 쓰이고 있다.Such flash memory is widely used for BIOS on the current motherboard, and is widely used in electronic devices such as mobile phones, satellite boxes, digital cameras, DVDs, MP3 players, and game machines.
플래쉬 메모리 소자는 일반적으로 실리콘 기판 상부에 박막의 터널 산화막과, 그 상부에 폴리실리콘으로 이루어진 플로팅 게이트와 플로팅 게이트 전극 상부에 형성되는 게이트 전극간 절연막과, 소정의 전압을 인가받는 콘트롤(control) 게이트 전극이 구비된다.Flash memory devices generally include a tunnel oxide film of a thin film on a silicon substrate, a floating gate made of polysilicon and an inter-gate insulating film formed on a floating gate electrode, and a control gate to which a predetermined voltage is applied. An electrode is provided.
종래의 터널 산화막은 7nm이상의 두꺼운 터널링 SiO2박막을 사용하므로 그 제조방법이 복잡하고 높은 프로그래밍 전압이 요구되는 단점이 있었다.Conventional tunnel oxide film has a disadvantage in that the manufacturing method is complicated and high programming voltage is required because a thick tunneling SiO 2 thin film of 7nm or more.
따라서, 차세대 메모리 소자인 플래쉬 메모리 소자의 나노 플로팅 게이트 형성에 있어서, 상온에서 낮은 전압에서도 기판에서 전자의 투과를 하여 나노 결정체에 구속되는 효과가 가능한 물질과 간단하게 입자의 크기나 밀도의 제어가 가능한 기술이 요구되어 왔다.Therefore, in forming a nano floating gate of a flash memory device, which is a next generation memory device, it is possible to control the particle size and density and the material capable of being constrained to the nanocrystals by the transmission of electrons from the substrate even at a low voltage at room temperature. Technology has been required.
본 발명은 상기와 같은 문제점을 해결하기 위한 것으로 별도의 터널 산화막의 형성이 필요없이 간단한 증착법과 열처리를 통해 고분자 내에 금속 또는 금속산화물 나노 결정체를 간단하게 형성함으로써 그 나노 결정체를 이용한 나노 플로팅 게이트를 가진 고효율 저비용의 플래쉬 메모리 소자 및 그 제조방법을 제공함을 목적으로 한다.
The present invention has been made to solve the above problems, and by forming a metal or metal oxide nanocrystals in the polymer simply by a simple deposition method and heat treatment without the need for the formation of a separate tunnel oxide film having a nano-floating gate using the nanocrystals An object of the present invention is to provide a highly efficient low cost flash memory device and a method of manufacturing the same.
상기와 같은 목적을 달성하기 위한 본 발명의 플래쉬 메모리 소자는 활성 영역을 갖는 반도체 기판; 상기 활성영역에 형성되되, 서로 이격된 드레인 영역 및 소오스 영역; 상기 드레인 영역 및 상기 소오스 영역 사이의 채널 영역 상에 형성되되, 상기 소오스 영역에 인접하도록 형성되고 고분자 박막 내의 금속 또는 금속 산화물 나노 결정체로 구성된 플로팅 게이트와, 상기 플로팅 게이트 상부에 상기 고문자 박막에 의해 전기적으로 분리되어 형성된 컨트롤 게이트를 포함하여 구성된다. 상기 고분자 박막 내의 금속 또는 금속 산화물 나노 결정체는 단층 또는 다층으로 형성될 수 있다.Flash memory device of the present invention for achieving the above object is a semiconductor substrate having an active region; A drain region and a source region formed in the active region and spaced apart from each other; A floating gate formed on the channel region between the drain region and the source region, the floating gate formed adjacent to the source region and composed of metal or metal oxide nanocrystals in a polymer thin film; It is configured to include a control gate formed electrically separated. The metal or metal oxide nanocrystals in the polymer thin film may be formed in a single layer or multiple layers.
바람직하게는, 상기 고분자 박막은 폴리이미드 박막이다. Preferably, the polymer thin film is a polyimide thin film.
또한, 본 발명의 플래쉬 메모리 소자의 제조방법은 반도체 기판의 전면상에 고분자 박막 내의 금속 또는 금속 산화물 나노 결정체로 구성된 플로팅 게이트를 형성하는 단계; 상기 플로팅 게이트 양측부에 소오스 및 드레인을 형성한 후 전체 상부면에 컨트롤 게이트를 순차적으로 형성하는 단계를 포함한다. In addition, the method of manufacturing a flash memory device of the present invention comprises the steps of forming a floating gate consisting of metal or metal oxide nanocrystals in a polymer thin film on the front surface of a semiconductor substrate; And forming source and drain portions on both sides of the floating gate, and sequentially forming control gates on the entire upper surface.
바람직하게는, 상기 플로팅 게이트를 형성하는 단계는, 반도체 기판상에 금속을 코팅하는 단계와, 절연체 고분자 단량체를 포함하는 산성 전구체를 용매에 녹여 액상으로 만든 후, 이를 상기 코팅된 금속 상에 스핀 코팅하는 단계와, 상기 코팅된 산성 전구체로부터 용매를 제거하는 단계와, 상기 코팅된 산성전구체 내부에서 가교결합이 일어나도록, 상기 고분자 물질에 열을 가하는 단계를 포함한다. Preferably, the forming of the floating gate may include coating a metal on a semiconductor substrate, dissolving an acidic precursor containing an insulator polymer monomer in a solvent to form a liquid, and then spin coating the coated metal on the coated metal. And removing the solvent from the coated acidic precursor, and applying heat to the polymeric material such that crosslinking occurs within the coated acidic precursor.
보다 바람직하게는, 상기 반도체 기판상에 코팅되는 금속은 구리, 아연, 주석, 코발트, 철, 카드뮴, 납, 마그네슘, 바륨, 몰리브덴, 인듐, 니켈, 텅스텐, 비스무트, 은, 망간 및 이들의 합금으로 이루어지는 군으로부터 선택되며 상기 절연체 고분자 단량체를 포함하는 산성 전구체는 카르복실기를 포함하는 산성 전구체가 바람직하다.More preferably, the metal to be coated on the semiconductor substrate is copper, zinc, tin, cobalt, iron, cadmium, lead, magnesium, barium, molybdenum, indium, nickel, tungsten, bismuth, silver, manganese and alloys thereof The acidic precursor selected from the group consisting of and including the insulator polymer monomer is preferably an acidic precursor containing a carboxyl group.
본 발명의 상기 용매는 절연체전구체의 종류에 따라 N-Metyl-2-Pyrrolidone(NMP), 물, N-디메틸아세트아미드, 디글림(diglyme) 중에서 선택되는 하나 또는 하나이상의 혼합물을 선택할 수 있다.The solvent of the present invention may select one or more mixtures selected from N-Metyl-2-Pyrrolidone (NMP), water, N-dimethylacetamide, and diglyme according to the type of insulator precursor.
보다 더 바람직하게는, 상기 플로팅 게이트를 형성하는 단계는 반도체 기판 상부에 금속 또는 합금을 1nm에서 30nm의 두께로 증착한 다음 N-Metyl-2-Pyrrolidone(NMP)을 용매로 하여 Biphenyltetracaboxylic Dianhydide-p-Phenylenediamine(BPDA-PDA)형의 폴리아믹산을 스핀 코팅하는 단계 및 경화작용을 위해 300~400℃정도에서 약 한 시간 정도 가열하는 단계를 포함한다.Even more preferably, the forming of the floating gate may be performed by depositing a metal or an alloy on the semiconductor substrate with a thickness of 1 nm to 30 nm, and then using N-Metyl-2-Pyrrolidone (NMP) as a solvent for Biphenyltetracaboxylic Dianhydide-p-. Spin coating a polyamic acid of the phenylenediamine (BPDA-PDA) type and heating for about one hour at about 300 ~ 400 ℃ for curing.
본 발명에 의하면, 폴리이미드 박막 내에 분산된 고밀도 나노 결정체가 형성된 플로팅 게이트를 형성할 수 있으며. 상기 금속의 종류, 금속의 초기 증착된 두께, 용매와 전구체의 혼합 비율, 경화작용 과정의 조건을 변화시킴으로써 형성되는 나노 결정체의 크기 및 밀도를 제어할 수 있으므로 전체적인 소자의 특성을 제어하는 것이 용이하다. According to the present invention, a floating gate in which high-density nanocrystals dispersed in a polyimide thin film can be formed. It is easy to control the overall device characteristics because the size and density of the nanocrystals formed can be controlled by changing the type of the metal, the initial deposited thickness of the metal, the mixing ratio of the solvent and precursor, and the conditions of the curing process. .
또한, 일반적으로 폴리이미드의 유전율은 약 2.9로서 본 발명의 폴리이미드 박막은 종래의 터널 산화막을 대체하고 폴리이미드 박막 내의 나노 결정체는 플로 팅 게이트로 이용된다. 따라서 본 발명의 플래쉬 메모리 소자의 제조시 별도의 터널 산화막을 형성할 필요가 없어 전체적인 메모리 소자의 두께를 감소시킬 수 있다.In general, the dielectric constant of polyimide is about 2.9, so that the polyimide thin film of the present invention replaces the conventional tunnel oxide film and the nanocrystals in the polyimide thin film are used as floating gates. Therefore, when the flash memory device of the present invention is manufactured, it is not necessary to form a separate tunnel oxide layer, thereby reducing the thickness of the entire memory device.
실시예Example
이하, 첨부된 도면을 참조하여 본 발명의 바람직한 실시예를 보다 상세하게 설명하도록 한다Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings.
실시예 1: 플래쉬 메모리 소자의 제작Example 1 Fabrication of Flash Memory Device
도 1은 본 발명의 일 실시예에 따른 플래쉬 메모리 소자의 개략도이다. 도 1을 참조하면, 반도체 기판(100) 예를들어, P형의 불순물이 도핑된 실리콘 기판상에 금속을 코팅하고, 폴리이미드의 산성전구체를 NMP에 녹여 액상으로 만든 후, 이를 상기 코팅된 금속 상에 스핀 코팅한 후 열을 가하여 폴리이미드 박막(110)을 적층한다. 이 때 상기 폴리이미드 박막(110)의 내부에 금속 산화물 나노 결정체(111)가 전체적으로 균일한 분포로 단층 또는 다층으로 존재하며 10~100nm의 두께로 형성된다. 상기 폴리이미드 박막의 하부와 폴리이미드 박막내부의 나노 결정체와의 거리는 1~10nm이며 기판상에 코팅된 금속은 산화반응에 모두 참여하여 폴리이미드 박막내로 유입되었으므로 폴리이미드 박막의 하부와 기판 사이에는 잔여 금속이 존재하지 않는다. 상기 폴리이미드 박막을 식각한 양측에 소오스 및 드레인 영역(121, 122)을 형성하고 상기 폴리이미드 박막(110) 상부에 콘트롤 게이트(130)가 형성된다. 1 is a schematic diagram of a flash memory device according to an embodiment of the present invention. Referring to FIG. 1, a metal is coated on a
상기 메모리 소자에 쓰기를 하고자 하는 경우 VGB에 양의 전압을 인가하면 기판의 전자들은 투과를 통해 나노 결정체에 갇히게 되고 이때 셀의 문턱 전압은 양의 값을 갖는다. 소거시에는 VGB에 음의 전압을 인가하고 전자들은 역 투과를 통해 나노 결정체에서 기판으로 유입된다. 이 경우 셀의 문턱 전압은 음의 값을 갖는다. 읽기는 VDS에 음의 전압을 인가하고, VGS에 0V를 인가하여 셀의 문턱전압의 크기가 양이냐 음이냐에 따라 드레인 전류의 유무를 결정하고, 그것을 통해 드레인 전압 값으로 데이터 "1" 또는 "0"을 읽어낸다.When writing to the memory device, when a positive voltage is applied to V GB , electrons of the substrate are trapped in the nanocrystals through transmission, and the threshold voltage of the cell has a positive value. During erasing, a negative voltage is applied to V GB and electrons are introduced from the nanocrystals to the substrate through reverse transmission. In this case, the threshold voltage of the cell has a negative value. Read applies a negative voltage to V DS and 0V to V GS to determine the presence or absence of a drain current, depending on whether the threshold voltage of the cell is positive or negative, through which data "1" Or read "0".
실시예 2: 폴리이미드 박막내의 ZnO 나노 결정체의 형성Example 2: Formation of ZnO Nanocrystals in Polyimide Thin Films
실리콘 기판 상부에 Zn 필름을 10nm의 두께로 증착한 다음 그 위에 N-Metyl-2-Pyrrolidone(NMP)을 용매로 하여 전구체 Biphenyltetracaboxylic Dianhydide-p-Phenylenediamine(BPDA-PDA)형의 폴리아믹산을 1:3의 비율로 스핀 코팅하였다. 잔여 용매를 증발제거한 후, 질소분위기하에서 400℃에서 한 시간 동안 열을 가하여 상기 폴리아믹산을 폴리이미드로 경화하였다. 폴리이미드 박막 내에 나노 결정체가 형성되었으며 산화물 ZnO의 형성 및 그 크기를 투과 전자 현미경으로 확인할 수 있었으며 도 2에 나타내었다. ZnO입자의 크기는 10nm 이하였으며 제조된 고분자 막의 두께는 80nm이었으며, 고분자 박막의 두께는 surface profiler(α-step, 표면단차측정기)와 TEM을 통하여 확인하였다. 도 3은 형성된 폴리이미드 박막의 단면도를 도시한 것으로 형성된 ZnO 나노 결정체가 다층으로 균일하게 형성되어 있으며 반응 후 실리콘 기판 상부 및 폴리이미드 박막 사이에 잔여 금속은 남지 않은 것을 확인 할 수 있었다. 폴리이미드 박막 위의 층은 TEM 관찰을 위한 에폭시 수지이다. A Zn film was deposited on the silicon substrate to a thickness of 10 nm, and the precursor Biphenyltetracaboxylic Dianhydide-p-Phenylenediamine (BPDA-PDA) type polyamic acid was 1: 3 using N-Metyl-2-Pyrrolidone (NMP) as a solvent thereon. Spin coating was carried out at the ratio of. After evaporation of the residual solvent, the polyamic acid was cured with polyimide by applying heat for 1 hour at 400 ° C. under a nitrogen atmosphere. Nanocrystals were formed in the polyimide thin film and the formation and size of the oxide ZnO could be confirmed by transmission electron microscopy and are shown in FIG. 2. The size of the ZnO particles was less than 10 nm and the thickness of the prepared polymer film was 80 nm, and the thickness of the polymer thin film was confirmed by surface profiler (α-step) and TEM. 3 shows a cross-sectional view of the formed polyimide thin film, and the ZnO nanocrystals formed are uniformly formed in multiple layers, and after the reaction, residual metal was not left between the upper portion of the silicon substrate and the polyimide thin film. The layer on the polyimide thin film is an epoxy resin for TEM observation.
실시예 3: 폴리이미드 박막 내의 CuExample 3: Cu in a Polyimide Thin Film 22 O 나노 결정체의 형성 Formation of O Nanocrystals
실리콘 기판 상부에 Cu 필름을 5nm의 두께로 증착한 다음 그 위에 N-Metyl-2-Pyrrolidone(NMP)을 용매로 하여 전구체 Biphenyltetracaboxylic Dianhydide-p-Phenylenediamine(BPDA-PDA)형의 폴리아믹산을 1:3의 비율로 스핀 코팅하였다. 잔여 용매를 증발제거한 후, 질소분위기하에서 350℃에서 한 시간 동안 열을 가하여 상기 폴리아믹산을 폴리이미드로 경화하였다. 폴리이미드 박막 내에 나노 결정체가 형성되었으며 산화물 Cu2O의 형성 및 그 크기를 투과 전자 현미경으로 확인할 수 있었으며 도 4에 나타내었다. Cu2O입자의 크기는 5nm였으며 제조된 고분자 막의 두께를 surface profiler(α-step)와 TEM을 통하여 확인하였으며 약 60nm이었다. A Cu film was deposited on the silicon substrate to a thickness of 5 nm, and the precursor Biphenyltetracaboxylic Dianhydide-p-Phenylenediamine (BPDA-PDA) type polyamic acid was 1: 3 using N-Metyl-2-Pyrrolidone (NMP) as a solvent thereon. Spin coating was carried out at the ratio of. After evaporation of the residual solvent, the polyamic acid was cured with polyimide by applying heat at 350 ° C. for 1 hour under nitrogen atmosphere. Nanocrystals were formed in the polyimide thin film, and the formation and size of the oxide Cu 2 O could be confirmed by transmission electron microscopy. The size of Cu 2 O particles was 5 nm, and the thickness of the prepared polymer film was confirmed by surface profiler (α-step) and TEM, and was about 60 nm.
실시예 4: 폴리이미드 박막 내에 SnOExample 4 SnO in a Polyimide Thin Film 22 나노 결정체의 형성 Formation of Nano Crystals
실리콘 기판 상부에 Sn 필름을 5nm의 두께로 증착한 다음 그 위에 N-Metyl-2-Pyrrolidone(NMP)을 용매로 하여 전구체 Biphenyltetracaboxylic Dianhydide-p-Phenylenediamine(BPDA-PDA)형의 폴리아믹산을 1:3의 비율로 스핀 코팅하였다. 잔여 용매를 증발제거한 후, 질소분위기하에서 400℃에서 한 시간 동안 열을 가하여 상기 폴리아믹산을 폴리이미드로 경화하였다. 폴리이미드 박막 내에 나노 결정체가 형성되었으며 surface profiler(α-step)과 TEM을 통하여 확인한 제조된 고분자 막의 두께는 약 60nm이었다. A Sn film was deposited on the silicon substrate to a thickness of 5 nm, and the precursor Biphenyltetracaboxylic Dianhydide-p-Phenylenediamine (BPDA-PDA) type polyamic acid was 1: 3 using N-Metyl-2-Pyrrolidone (NMP) as a solvent thereon. Spin coating was carried out at the ratio of. After evaporation of the residual solvent, the polyamic acid was cured with polyimide by applying heat for 1 hour at 400 ° C. under a nitrogen atmosphere. Nanocrystals were formed in the polyimide thin film, and the thickness of the prepared polymer film was about 60 nm, which was confirmed by surface profiler (α-step) and TEM.
본 발명은 종래의 플래쉬 메모리 소자의 나노 결정체의 형성과정보다 매우 간단하게 나노 결정체를 형성할 수 있으며 전체적으로 균일한 분포를 가지는 결정체들이 고분자층으로 둘러쌓여있어 결정체의 응집현상 없이 나노 결정체의 크기나 밀도를 제어할 수 있으며 터널산화막을 별도로 필요로 하지 아니하므로 플래쉬 메모리 소자의 두께를 감소시켜 작동전압을 낮출 수 있다. 또한, 종래의 나노 플로팅 게이트보다 전기적으로나 화학적으로 안정성을 갖는 나노 플로팅 게이트를 이용함으로써 고효율 저비용의 나노 플로팅 게이트의 메모리 소자 및 그 제조방법을 제조하는 우수한 효과가 있으며 정보 전자 통신분야에서 매우 유용한 발명이다.The present invention can form nanocrystals much simpler than the formation of nanocrystals of a conventional flash memory device, and the crystals having a uniform distribution as a whole are surrounded by a polymer layer, so that the size or density of the nanocrystals without aggregation of crystals. Can be controlled and the tunnel oxide film is not required separately, thereby reducing the thickness of the flash memory device to lower the operating voltage. In addition, by using a nano floating gate that is more electrically and chemically stable than a conventional nano floating gate, there is an excellent effect of manufacturing a memory device and a manufacturing method of the nano floating gate having high efficiency and is very useful in the field of information electronic communication. .
Claims (11)
Priority Applications (5)
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| KR1020040021073A KR100585849B1 (en) | 2004-03-29 | 2004-03-29 | Flash Memory Device Comprising Floating Gate Utilizing Nanocrystals Embeded In Polymer Thin Film And Fabrication Method Thereof |
| PCT/KR2005/000161 WO2005093837A1 (en) | 2004-03-29 | 2005-01-18 | Flash memory device utilizing nanocrystals embeded in polymer |
| JP2007506069A JP4668981B2 (en) | 2004-03-29 | 2005-01-18 | Flash memory device using nanocrystals in polymer |
| CN2005800103469A CN1969386B (en) | 2004-03-29 | 2005-01-18 | Flash memory device utilizing nanocrystals embedded in polymer |
| US11/540,991 US7592663B2 (en) | 2004-03-29 | 2006-09-28 | Flash memory device utilizing nanocrystals embedded in polymer |
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| KR100719047B1 (en) * | 2005-12-19 | 2007-05-16 | 한양대학교 산학협력단 | Multilevel nonvolatile flash memory device using self-assembled multiple-stacked nanoparticle layers embedded in polymer thin films as floating gates, method for fabricating it and method for controlling write/read operation of it |
| US7615446B2 (en) | 2005-10-13 | 2009-11-10 | Samsung Electronics Co., Ltd. | Charge trap flash memory device, fabrication method thereof, and write/read operation control method thereof |
| KR100736850B1 (en) * | 2006-05-11 | 2007-07-10 | 한양대학교 산학협력단 | Fabrication method of nano-floating gate flash memory devices utilizing metal nanocrystals |
| KR100783188B1 (en) * | 2006-06-09 | 2007-12-11 | 한양대학교 산학협력단 | Nonvolatile flash memory device comprising floating gates utilizing both a tunneling small molecule layer and nanoparticles embedded in the polymer thin films and manufacturing method thereof |
| KR100779566B1 (en) * | 2006-12-08 | 2007-11-28 | 한양대학교 산학협력단 | Nano floating gate non-volatile memory device and a fabrication method thereof |
| KR100858085B1 (en) * | 2006-12-18 | 2008-09-10 | 삼성전자주식회사 | Charge trap memory device using nanodot as charge trap site |
| KR100888848B1 (en) * | 2007-08-14 | 2009-03-17 | 한양대학교 산학협력단 | Fullerene-based flash memory device and method of fabricating the same |
| KR100889779B1 (en) * | 2007-09-19 | 2009-03-20 | 한양대학교 산학협력단 | Memory devices and method of fabricating the same |
| KR100902313B1 (en) * | 2007-09-27 | 2009-06-12 | 국민대학교산학협력단 | Floating Gate Having Multiple Charge Storing Layers, Method for Fabricating the Floating Gate, Non-volatile Memory Device and Method for Fabricating Non-volatile Memory Device Using the Same |
| KR100909365B1 (en) | 2007-12-05 | 2009-07-24 | 한양대학교 산학협력단 | Nonvolatile Organic Bistable Memory and Manufacturing Method Thereof |
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| CN1969386A (en) | 2007-05-23 |
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