KR100581934B1 - Plasma display panel - Google Patents

Abstract

SUMMARY OF THE INVENTION An object of the present invention is to improve discharge efficiency and improve the life of a panel by applying a short pulse to an address electrode during sustain discharge in a panel having a new electrode structure using opposite discharge. In order to achieve the above object, the present invention, the front substrate and the rear substrate disposed in parallel to the front substrate; A front partition wall disposed between the front substrate and the rear substrate, defining discharge cells together with the front substrate and the rear substrate, and formed of a dielectric; Address electrode lines disposed in a front dielectric layer formed on a front substrate in a rear substrate direction and including a bus electrode disposed on the front barrier ribs and a transparent electrode disposed on the discharge cells; Scan electrode lines and sustain electrode lines that are alternately disposed in the front partition walls to face each other, and are orthogonal to the address electrode lines; Rear barrier ribs disposed between the front barrier ribs and a rear dielectric layer formed in the front substrate direction on the rear substrate; A phosphor layer disposed in a space defined by the rear partitions; And a discharge gas in the discharge cell, and driven by a drive signal having a reset section, an address section, and a sustain discharge section, and in the sustain discharge section, the first voltage has a rising slope and a falling slope. And a first sustain pulse and a second sustain pulse reaching the ground voltage are alternately applied to the scan electrode lines and the sustain electrode lines, and a short pulse is applied to the address electrode lines. Provide a panel.

Description

Plasma Display Panel {Plasma display panel}

1 is a timing diagram for explaining an example of a conventional driving signal.

2 is an exploded perspective view showing a plasma display panel of the present invention.

3 is a plan view of the plasma display panel of FIG. 2 taken along line II-II.

4 is a view schematically illustrating an electrode arrangement of the plasma display panel of FIG. 2.

FIG. 5 is a block diagram schematically illustrating an apparatus for driving a plasma display panel for implementing the method of driving the plasma display panel of FIG. 2.

FIG. 6 illustrates an address-display separation driving method for Y electrode lines as an example of the driving method of the plasma display panel of FIG. 2.

FIG. 7 is a timing diagram for describing a first embodiment of a drive signal of the panel shown in FIG. 2.

FIG. 8 is a timing diagram for describing a second embodiment of a drive signal of the panel shown in FIG. 2.

Explanation of symbols on the main parts of the drawings

1 ... plasma display panel, 110 ... front panel,

111 front substrate, 112 transparent electrode,

113 bus electrode, 114 address electrode,

115 front barrier, 116 shield,

117 front dielectric layer, 118 holding electrode,

119 scan electrode, 120 rear panel,

121 back substrate, 123 rear dielectric layer,

125 phosphor layer, Ce discharge cell,

Y1, ..., Yn ... multiple scan electrode lines,

X1, ..., Xn ... a plurality of sustain electrode lines,

A1, A2, ..., Am ... multiple address electrode lines,

Vs ... first voltage, Vset ... second voltage,

Vset + Vs ... third voltage, Vnf ... fourth voltage,

Vsch ... 5th voltage, Vscl ... 6th voltage,

Va ... 7th voltage, 400 ... image processing unit,

402 logic unit, 404 Y drive,

406 ... address drive,

Vs1, Vs2 ... the short pulse voltage of FIGS.

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a plasma display panel having a new electrode structure using opposite discharge. More particularly, the present invention relates to a plasma display panel having an electrode structure in which a sustain electrode and a scan electrode are opposed to each other. The present invention relates to a plasma display panel which improves efficiency and improves the lifetime of the panel.

Japanese Laid-Open Patent Publication No. 1999-120924 discloses a structure of a conventional plasma display panel. That is, address electrode lines, dielectric layers, scan electrode lines, sustain electrode lines, phosphor layers, barrier ribs, and magnesium monoxide (MgO) protective layers are provided between the front and back substrates of a conventional plasma display panel.

The address electrode lines are formed in a predetermined pattern on the front side of the back substrate. The back dielectric layer is applied to the front of the address electrode lines. In the front of the rear dielectric layer, barrier ribs are formed in a direction parallel to the address electrode lines. These partitions partition the discharge area of each discharge cell and serve to prevent optical interference between the discharge cells. The phosphor layer is applied in front of the rear dielectric layer on the address electrode lines between the partition walls, and a red light emitting phosphor layer, a green light emitting phosphor layer, and a blue light emitting phosphor layer are sequentially disposed.

The sustain electrode lines and the scan electrode lines are formed in a constant pattern on the rear side of the front substrate so as to be orthogonal to the address electrode lines. Each intersection sets a corresponding discharge cell. Each sustain electrode line and each scan electrode line may be formed by combining a transparent electrode line of a transparent conductive material such as indium tin oxide (ITO) and a metal electrode (bus electrode) line for increasing conductivity. The front dielectric layer is formed by coating the entire surface of the sustain electrode lines and the scan electrode lines. A protective layer for protecting the panel from a strong electric field, for example, a magnesium monoxide (MgO) layer is formed by applying the entire surface to the back of the front dielectric layer. The plasma forming gas is sealed in the discharge space.

The driving signal of FIG. 1 is used as a driving signal for driving a conventional plasma display panel. That is, one subfield SF has a reset period PR, an address period PA, and a sustain discharge period PS, and address electrode lines A1, A2, ..., Am, and sustain electrode line. Driving signals are applied to the fields X1, ..., Xn and the scan electrode lines Y1, ..., Yn, respectively.

First, the reset period PR applies a reset pulse to all the scan electrode lines Y1,..., And Yn to perform reset discharge, thereby initializing the wall charge state of all the discharge cells. The reset period PR is carried out before entering the address period PA, which is carried out over the entire screen, thus making it possible to create a fairly even and evenly distributed wall charge arrangement. To this end, as shown in FIG. 1, the ground voltage Vg is first applied to the scan electrode lines Y1,..., And Yn, and then the sustain discharge voltage Vs is applied, and the sustain discharge voltage Vs is applied. From the rising ramp function is applied to reach the highest rising voltage (Vset + Vs), which is increased by the rising voltage (Vset), and then rapidly lowered to the sustain discharge voltage (Vs), from the sustain discharge voltage (Vs) to the falling ramp function Is applied to reach the lowest falling voltage (Vnf). The ground voltage Vg is applied to the address electrode lines A1, A2, ..., Am during the reset period PR, and the rising ramp function is applied to the sustain electrode lines X1, ..., Xn. The bias voltage Vb is continuously applied from time to time.

Next, in the address period PA, in order to select a cell to be turned on, a bias voltage Vb is applied to the sustain electrode lines X1, ..., Xn, and the scan electrode lines Y1,. The scan high voltage Vsch is applied to Yn, and the scan pulses having the scan low voltage Vscl are sequentially applied to the scan electrode lines Y1, ..., Yn. A display data signal having an address voltage Va is applied to the address electrode lines A1, A2, ..., Am. As the scan pulse and the display data signal are applied, address discharge is performed in the selected discharge cell.

Next, in the sustain discharge period PS, the sustain electrode lines X1,..., Xn and the scan electrode lines Y1, so that the sustain discharge is performed in the cell to be turned on selected in the address period PA. ..., and a sustain pulse having a sustain discharge voltage Vs is applied alternately. The sustain pulse has a rising slope and reaches a sustain discharge voltage, and has a falling slope and reaches a ground voltage. The sustain discharge is performed by the wall charge accumulated in the discharge cell selected by the address discharge and the applied sustain discharge voltage Vs. Plasma is formed from the plasma forming gas of the discharge cells which perform the sustain discharge, and the phosphors of the discharge cells are excited by ultraviolet radiation from the plasma to generate light.

The conventional plasma display panel described above is a three-electrode surface discharge method in which the scan electrodes Y and the sustain electrodes X are arranged side by side behind the front substrate. For this reason, during the sustain discharge, the ion particles are accelerated by the electric field formed by the potential applied to the scan electrode Y and the sustain electrode X, and the ion particles accelerated by the electric field even when they collide with the discharge gas to cause discharge. Since the movement path of is limited to a certain range behind the front substrate and moves shortly, the collision probability with the discharge gas is extremely lowered, and the discharge is concentrated in some space inside the discharge cell, resulting in a decrease in the efficiency of the plasma display panel. I had a problem. In the case of using the plasma display panel for a long time, the scanning electrode and the sustain electrode are arranged on the rear surface of the front substrate, and the discharge is diffused toward the phosphor layer from the rear of the front dielectric layer. By causing sputtering (ion sputtering) causes a permanent afterimage, there is a problem to shorten the life of the plasma display panel.

SUMMARY OF THE INVENTION An object of the present invention is to improve discharge efficiency and improve the life of a panel by applying a short pulse to an address electrode during sustain discharge in a panel having a new electrode structure using opposite discharge.

In order to achieve the above object, the present invention, the front substrate and the rear substrate disposed in parallel to the front substrate; A front partition wall disposed between the front substrate and the rear substrate, defining discharge cells together with the front substrate and the rear substrate, and formed of a dielectric; Address electrode lines disposed in a front dielectric layer formed on a front substrate in a rear substrate direction and including a bus electrode disposed on the front barrier ribs and a transparent electrode disposed on the discharge cells; Scan electrode lines and sustain electrode lines that are alternately disposed in the front partition walls to face each other, and are orthogonal to the address electrode lines; Rear barrier ribs disposed between the front barrier ribs and a rear dielectric layer formed in the front substrate direction on the rear substrate; A phosphor layer disposed in a space defined by rear barrier ribs; And a discharge gas in the discharge cell, and driven by a drive signal having a reset period, an address period, and a sustain discharge period.

In the sustain discharge period, the first sustain pulse and the second sustain pulse having the rising slope reaching the first voltage and the falling slope reaching the ground voltage alternately in the scan electrode lines and the sustain electrode lines, respectively. The present invention provides a plasma display panel, wherein a short pulse is applied to the address electrode lines.

According to another aspect of the present invention, the plasma display panel,

In the reset period, the rising ramp signal is applied to the scan electrode lines at the first voltage to finally reach the third voltage which is increased by the second voltage, and the falling ramp signal is applied at the first voltage to finally the fourth voltage. Is reached, the fifth voltage is applied from the falling ramp signal to the sustain electrode lines, and the ground voltage is applied to the address electrode lines,

In the address period, the scan pulses having the seventh voltage are sequentially applied to the scan electrode lines while the sixth voltage is applied, and the display data signal having the eighth voltage is applied to the address electrodes according to the scan pulse. The fifth voltage may be applied to the electrode lines.

According to another feature of the invention, the short pulse may be applied at the moment when the first voltage is applied in the first sustain pulse or the second sustain pulse.

According to another feature of the present invention, a section in which the first voltage is applied in the first sustain pulse and the second sustain pulse may overlap each other.

According to another feature of the present invention, the sections in which the first voltage is applied in the first sustain pulse and the second sustain pulse may not overlap each other.

According to another feature of the invention, the pulse width of the short pulse may be less than half of the pulse width of the first sustain pulse or the second sustain pulse.

According to another feature of the invention, the short pulse has a ninth voltage, the magnitude of the ninth voltage may be smaller than the magnitude of the eighth voltage.

According to another feature of the invention, the short pulse has a ninth voltage, the magnitude of the ninth voltage may be equal to the magnitude of the eighth voltage.

Hereinafter, with reference to the accompanying drawings will be described in detail an embodiment of the present invention.

2 is an exploded perspective view showing a plasma display panel of the present invention.

3 is a plan view of the plasma display panel of FIG. 2 taken along line II-II.

A description with reference to FIGS. 2 to 3 is as follows.

The plasma display panel 1 according to the present invention includes a front panel 110 and a rear panel 120, the front panel 110 having a front substrate 111, and the rear panel 120 having a rear substrate ( 121). The plasma display panel 1 is disposed between the front substrate 111 and the rear substrate 121, and partition walls 130 defining discharge cells Ce, which are spaces for generating discharge and generating light, for realizing an image. ). The partitions 130 may be advantageously disposed in the front partitions 115 and the rear partitions 124 in the manufacturing process, but need not be formed separately.

The front panel 110 includes a front dielectric layer 117 that is disposed behind the front substrate 111, that is, on a rear surface of the front substrate, and covers the address electrode lines 114 to be described later. The address electrode lines 114 are disposed in the front dielectric layer, are disposed on the front partition wall, are disposed on the bus electrode 113 of a metallic material to increase conductivity, and are disposed on the discharge cells Ce, and are formed of ITO. A transparent electrode 112 made of a transparent conductive material such as (Indium Tin Oxide) is provided. The address electrode lines 114 extend in one direction in which the discharge cells Ce extend.

In addition, the front panel 110 is formed at the rear of the front substrate 111, that is, the rear surface of the front dielectric layer 117 to discharge the discharge cells Ce together with the front substrate 111 and the rear substrate 121. And defining forward bulkheads 115. In this case, the front partition wall 115 is disposed to define the discharge cells (Ce) together with the front substrate 111 and the rear substrate 121, the front partition wall 115 is the back of the front substrate 111 or This does not mean that the substrate is in direct contact with the front surface of the rear substrate 121, but also includes the direct dielectric layer 117 disposed on the rear surface of the front substrate 111. Meanwhile, sustain electrode lines 118 and scan electrode lines 119 are alternately disposed in the front partition walls 115, respectively. The scan electrode lines 118 and the sustain electrode lines 119 extend perpendicular to the direction in which the address electrode lines 114 extend.

On the other hand, the front panel 110 is preferably provided with a protective film 116 covering the outer surface of the front partition wall 115 that can be formed as needed. In this case, the passivation layer 116 may be provided on the outer surface of the front partition walls 116 or the front surface of the phosphor layer 125.

The rear panel 120 may include the rear substrate 121 and a rear dielectric layer 123 formed on the rear substrate 121 in the direction of the front substrate 121.

In addition, the rear panel 120 is disposed in a space defined by the rear partitions 124 disposed between the front partition walls 115 and the rear dielectric layer 123 and the rear partition walls 124. Phosphor layer 125 is provided.

The front panel 110 and the rear panel 120 are preferably coupled and sealed by a coupling member such as a frit (not shown), and need not necessarily be coupled by a coupling member such as frit, When the discharge gas in the discharge cell (Ce) is in a vacuum state, it may be combined at a pressure according to the vacuum state. On the other hand, inside the discharge cell (Ce) discharge consisting of any one or two or more of the mixed gas of neon (Ne), helium (He), or argon (Ar) including xenon (Xe) gas before and after 10% The gas is filled.

The front substrate 111 and the rear substrate 121 are generally formed of glass, and the front substrate is preferably formed of a material having high light transmittance. On the other hand, the rear substrate 121 does not necessarily need to transmit light, and a wider selection range of materials than the front substrate 111 does not necessarily require a material having a high light transmittance such as glass. Rather, it may be more desirable to use a variety of materials that have high light reflectance or that can reduce reactive power.

In order to improve the brightness of the plasma display panel, a reflective layer (not shown) is disposed on the top surface of the rear substrate 121 or the top surface of the rear dielectric layer 123 or includes a light reflective material in the rear dielectric layer 123. The visible light generated by the phosphor may be efficiently reflected forward.

Since the light transmittances of the sustain electrode lines 118 and the scan electrode lines 119 do not need to be considered, a wide selection of electrode materials is preferred, and Ag, Cu, Cr, and the like having high electrical conductivity are preferably used. . Meanwhile, the transparent electrode 112 among the address electrode lines 114 is disposed on the rear surface of the front substrate 111, that is, the upper part of the discharge cells Ce, and thus easily transmits visible light generated from the phosphor layer 125. You should be able to. As a material of the transparent electrode 112 having a good light transmittance, a material such as ITO, SnO 2, or ZnO may be used, and ITO is preferably used.

Meanwhile, the partitions 130 disposed between the front substrate 111 and the rear substrate 121 are formed to define discharge cells Ce together with the front substrate 111 and the rear substrate 121. In FIG. 2, the partition walls 130 divide the discharge cells Ce into a matrix, but are not limited thereto. The barrier ribs 130 may be partitioned into various shapes such as a honeycomb form and a delta form. In addition, although the cross section of the discharge cell Ce is illustrated in FIG. 3 as being rectangular, the present invention is not limited thereto and may be a polygon such as a triangle, a pentagon, or a circle, an ellipse, or the like.

After forming the front partition walls 115, it is preferable to form the passivation layer 116 on the outer surface of the front partition walls 115 by a deposition method or the like. The protective layer 116 protects the front partition walls 115 formed of a dielectric covering the sustain electrode lines 118 or the scan electrode lines 119 during discharge, and discharges secondary electrons to facilitate discharge. Make it happen.

The rear barrier ribs 124 may be formed on the rear dielectric layer 123, and the rear barrier ribs 124 may also include elements such as Pb, B, Si, Al, and O, such as the front barrier ribs. And the like, and may include fillers such as ZrO 2, TiO 2, and Al 2 O 3 and pigments such as Cr, Cu, Co, Fe, and TiO 2 as necessary.

The rear partitions 124 secure a space in which the phosphor layer 125 can be applied, and are discharged in the front panel 110 and the rear panel 120 together with the front partitions 115. It supports the pressure generated due to the vacuum state of the gas (for example, 0.5 atm), secures the space of the discharge cell (Ce), and prevents cross talk between the discharge cells (Ce). Can be done. In addition, the rear partitions 124 may include a reflective material so that visible light generated from the discharge cells Ce may be reflected forward. A red, green, or blue light emitting phosphor layer 125 may be disposed in a space defined by the rear partitions 124, and the phosphor layer 125 is partitioned by the rear partitions 124. do.

The phosphor layer 125 is a phosphor paste in which any one of a phosphor, a solvent, and a binder of a red light emitting phosphor, a green light emitting phosphor, and a blue light emitting phosphor is mixed is applied to the front and rear partitions 124 of the rear dielectric layer 123. After forming and drying and firing. Examples of the red light emitting phosphor include Y (V, P) O 4: Eu, and examples of the green light emitting phosphor include ZnSi 4 4: Mn, YBO 3: Tb, and the blue light emitting phosphor include BAM: Eu.

A rear passivation layer (not shown) made of MgO or the like may be formed on the front surface of the phosphor layer 125. The rear passivation layer may prevent the phosphor layer from deteriorating due to collision of discharge particles when the discharge occurs in the discharge cell Ce, and may emit secondary electrons to help the discharge easily occur. have.

4 is a view schematically illustrating an electrode arrangement of the plasma display panel of FIG. 2.

Referring to FIGS. 2 to 4, the scan electrode lines Y1,..., And Yn and the sustain electrode lines X1,..., Xn are disposed in parallel with each other. That is, only one of the scan electrode lines Y1,..., Yn or the sustain electrode lines X1,..., Xn is disposed in the front partition walls 115, respectively. Address electrode lines A1, A2, ..., Am are disposed so as to be orthogonal to the scan electrode lines Y1, ..., Yn and sustain electrode lines X1, ..., Xn. A space between the scan electrode lines Y1, ..., Yn and the sustain electrode lines X1, ..., Xn and the address electrode lines A1, A2, ..., Am cross each other. Discharge cells Ce are partitioned in the region.

FIG. 5 is a block diagram schematically illustrating an apparatus for driving a plasma display panel for implementing the method of driving the plasma display panel of FIG. 2.

Referring to FIGS. 4 and 5, the driving apparatus of the plasma display panel includes an image processor 400, a logic controller 402, a Y driver 404, an address driver 406, an X driver 408, and a plasma. The display panel 1 is provided.

The image processor 400 receives an external video signal such as a PC signal, a DVD signal, a video signal, or a TV signal from the outside, converts an analog signal into a digital signal, and processes the digital signal into an internal video signal. The internal video signals are 8-bit red (R), green (G), and blue (B) image data, clock signals, and vertical and horizontal sync signals, respectively.

The logic controller 402 receives an internal image signal from the image processor 400 and performs an gamma correction, an automatic power control (APC) step, and the like, to respectively output an address driving control signal SA and a Y driving control signal SY. Output

The Y driver 404 receives the Y drive control signal SY from the logic controller 402, and has an erase pulse having an erase voltage for initialization discharge in the reset period (PR of FIG. 7), and an address period (FIG. 7). And a scan signal having a negative scan low voltage (Vscl in FIG. 7) sequentially along the vertical direction of the panel 1 while a positive scan high voltage (Vsch in FIG. 7) is applied to PA). A sustain pulse having a positive sustain discharge voltage (Vs in FIG. 7) and a ground voltage (Vg in FIG. 7) in the PS of FIG. 7 is applied to the scan electrode lines Y1, ..., of the plasma display panel 1. Yn).

The address driver 406 receives the address drive control signal SA from the logic controller 402 and has an address voltage (Va) of FIG. 7 in a cell to be turned on among all cells in the address period (PA of FIG. 7). The display data signal is output to the address electrode lines of the plasma display panel 1. Also in connection with the present invention, a short pulse is applied in the sustain discharge period. The voltage of the short pulse may be a voltage less than or equal to the address voltage Va of FIG. 7.

The X driver 408 receives the Y drive control signal SY from the logic controller 402 and maintains the bias voltage (Vb in FIG. 7) in the reset period (PR in FIG. 7) and the address period Pa. In the discharge, a sustain pulse having a positive sustain discharge voltage (Vs in FIG. 7) and a ground voltage (Vg in FIG. 7) is applied to the sustain electrode lines X1,..., Xn of the plasma display panel 1. do.

FIG. 6 illustrates an address-display separation driving method for Y electrode lines as an example of the driving method of the plasma display panel of FIG. 2.

4 and 6, a unit frame may be divided into a predetermined number, for example, eight subfields SF1,..., SF8 to realize time division gray scale display. Further, each subfield SF1, ... SF8 is divided into a reset section (not shown), an address section A1, ..., A8, and a sustain discharge section S1, ..., S8. .

In each address section A1, ..., A8, a display data signal is applied to the address electrode lines A1, A2, ..., Am and at the same time, the scan electrode lines Y1, ..., Yn Are sequentially applied.

In each sustain discharge section S1, ..., S8, sustain pulses are alternately applied to the scan electrode lines Y1, ..., Yn and sustain electrode lines X1, ..., Xn. , Sustain discharge occurs in the discharge cells in which wall charges are formed in the address periods A1, ..., A8.

The luminance of the plasma display panel is proportional to the number of sustain discharge pulses in the sustain discharge sections S1, ..., S8 occupied in the unit frame. When one frame forming one image is represented by eight subfields and 256 gradations, each subfield is kept different at a ratio of 1, 2, 4, 8, 16, 32, 64, and 128 in turn. The number of pulses can be assigned. In order to obtain luminance of 133 gradations, cells may be addressed and sustained and discharged during the subfield 1 period, the subfield 3 period, and the subfield 8 period.

The number of sustain discharges allocated to each subfield may be variably determined according to weights of the subfields according to the APC (Automatic Power Control) step. The number of sustain discharges allocated to each subfield can be variously modified in consideration of gamma characteristics and panel characteristics. For example, the gray level assigned to subfield 4 may be lowered from 8 to 6, and the gray level assigned to subfield 6 may be increased from 32 to 34. In addition, the number of subfields forming one frame can be variously modified according to design specifications.

FIG. 7 is a timing diagram for describing a first embodiment of a drive signal of the panel shown in FIG. 2.

Referring to the drawings, the subfield SF includes a reset period PR, an address period PA, and a sustain discharge period PS.

In the reset period PR, the ground voltage Vg is first applied to the scan electrode lines Y1, ..., Yn. Next, the sustain discharge voltage Vs, which is the first voltage, is rapidly applied, and the rising ramp signal is applied from the first voltage Vs, and the highest rise is the third voltage that is raised by the rising voltage Vset, which is the second voltage. The voltage Vset + Vs is reached. The weak discharge occurs due to the application of the rising ramp signal having an inclined slope, and the negative discharge starts to accumulate in the vicinity of the scan electrode lines Y1,..., And Yn. Next, after rapidly falling to the first voltage Vs, a falling ramp signal is applied to reach the fourth falling voltage Vnf. A weak discharge occurs due to the application of a falling ramp signal having a steep slope, and the weak discharge is generated to discharge some of the negative charges accumulated near the scan electrode lines Y1, ..., Yn. As a result, a negative amount of negative charge suitable for generating an address discharge remains in the vicinity of the scan electrode lines Y1, ..., and Yn. Since the falling ramp signal is applied to the scan electrode lines Y1,..., And Yn, a bias voltage Vb, which is a fifth voltage, is applied to the sustain electrode lines X1,..., Xn. The ground voltage Vg is applied to the address electrode lines A1, A2, ..., Am during the reset period PR.

Next, in order to select a cell to be turned on in the address period PA, a scan high voltage Vsch, which is a sixth voltage, is first applied to the scan electrode lines Y1,. A scan pulse having a scan low voltage Vscl, which is a seventh voltage, is applied to each line. A display data signal having an address voltage Va, which is an eighth voltage, is applied to the address electrode lines A1, A2, ..., Am in accordance with the scan pulse. The fifth voltage Vb is continuously applied to the sustain electrode lines X1,..., And Xn. The address discharge is performed by the eighth voltage Va, the seventh voltage Vscl, the wall voltage caused by the negative charge near the scan electrode Y, and the wall voltage caused by the positive charge near the address electrode A. After the address discharge is performed, positive charges are accumulated near the scan electrode Y, and negative charges are accumulated near the sustain electrode X.

In the sustain discharge period PS, the first sustain pulse and the second sustain pulse having the rising slope reaching the first voltage Vs and having the falling slope reaching the ground voltage Vg are respectively the scan electrode lines. (Y1, ..., Yn) and sustain electrode lines (X1, ..., Xn) are alternately applied to each other. A short pulse is applied to the address electrode lines A1, A2, ..., Am.

The short pulse is to improve discharge efficiency during sustain discharge, and the short pulse is preferably applied at the moment when the first voltage Vs is applied to the first sustain pulse or the second sustain pulse. In addition, sections in which the first voltage Vs is applied in the first sustain pulse and the second sustain pulse may overlap each other. In addition, the pulse width of the short pulse may be less than half of the pulse width of the first sustain pulse or the second sustain pulse. In addition, the voltage level of the short pulse may be smaller than or equal to that of the eighth voltage Va.

The first sustain pulse and the second sustain pulse of FIG. 7 are overlapping waveforms in which sections in which the first voltage is applied overlap each other. In detail, from time t1 to t2, the first sustain pulse applied to the scan electrode lines Y1, ..., Yn has a rising slope and finally reaches the first voltage Vs. At this time, the second sustain pulse applied to the sustain electrode lines X1,..., Xn has a ground voltage Vg. From time t2 to t4, the first sustain pulse continues to have the first voltage Vs. On the other hand, the second sustain pulse continues to have the ground voltage Vg from time t2 to t3, has a rising slope from time t3 to t4, and finally reaches the first voltage Vs. As a result, the first sustain pulse and the second sustain pulse overlap the first voltage Vs at time t4. Next, from time t4 to t5, the first sustain pulse has a falling slope and reaches the ground voltage Vg. From time t4 to t7, the second sustain pulse has a first voltage Vs. From time t5 to t6, the first sustain pulse has a ground voltage Vg. From time t6 to t7, the first sustain pulse has a rising slope, reaches the first voltage, and repeats the above process. The rising and falling slopes are typically used for energy charging and recovery.

The overlapping waveform in the sustain discharge period PS is such that a section having the first voltage Vs overlaps each other in the first sustain pulse applied to the scan electrode Y and the second sustain pulse applied to the sustain electrode X. It is not limited to overlapping at time t4 as shown in FIG. 7, and may overlap for more time. The longer the overlapping section, the shorter the period between the first sustain pulse and the second sustain pulse, and the shorter the interval between the sustain discharges. In other words, when the discharge frequency is increased, the space charge can be well utilized in sustain discharge, and the luminous efficiency can be improved.

In the case where the first sustain pulse has the first voltage Vs, the first positive voltage Vs applied to the scan electrode Y, the ground voltage Vg applied to the sustain electrode X, and the scan As the sustain discharge is performed due to the wall voltage due to the positive charge accumulated near the electrode Y and the wall voltage due to the negative charge accumulated near the sustain electrode X, a negative charge is accumulated near the scan electrode Y, and the sustain electrode A positive charge builds up near (X). At the moment when the first sustain pulse reaches the first voltage Vs, a short pulse is applied to the address electrode A. FIG.

Next, when the second sustain pulse has the first voltage, the first positive voltage Vs applied to the sustain electrode X, the ground voltage Vg applied to the scan electrode Y, and the sustain voltage are applied. As the sustain discharge is performed due to the wall voltage due to the positive charge accumulated near the electrode X and the wall voltage due to the negative charge accumulated near the scan electrode Y, a positive charge is accumulated near the scan electrode Y, and the sustain electrode A negative charge builds up near (X). At the moment when the second sustain pulse reaches the first voltage Vs, a short pulse is applied to the address electrode A. FIG. The above steps are repeated continuously, which causes the sustain discharge to continue.

For example, when the first sustain pulse applied to the scan electrode Y has the first voltage Vs, the short pulse shifts a part of the negative charge accumulated on the scan electrode Y. In the plasma display panel of the present invention, since the scanning electrode (Y) and the sustain electrode (X) face each other, the sustain discharge is performed smoothly, and the discharge volume increases to the vicinity of the address electrode (A) due to the short pulse. The discharge efficiency is increased, and the brightness is also improved. In addition, since the discharge volume is increased, ion sputtering by the charged particles of the discharge gas in the phosphor can be reduced as compared with the prior art, thus improving the lifetime of the plasma display panel. However, the pulse width of the applied short pulse is preferably less than half of the pulse width of the sustain pulse, so that a large amount of negative charges are not drawn from the scan electrode Y due to the application of the short pulse, and the voltage of the short pulse of FIG. It is preferable that Vs1 is smaller than the eighth voltage Va. However, in consideration of an increase in manufacturing cost caused by supplying various powers from the power supply device, the voltage Vs1 of the short pulse of FIG. 7 may be equal to the magnitude of the eighth voltage Va.

FIG. 8 is a timing diagram for describing a second embodiment of a drive signal of the panel shown in FIG. 2.

The reset period PR and the address period PA are as described in FIG.

In the sustain discharge period PS, the first sustain pulse and the second sustain pulse having the rising slope reaching the first voltage Vs and having the falling slope reaching the ground voltage Vg are respectively the scan electrode lines. (Y1, ..., Yn) and sustain electrode lines (X1, ..., Xn) are alternately applied to each other. A short pulse is applied to the address electrode lines A1, A2, ..., Am.

The short pulse is to improve discharge efficiency during sustain discharge, and the short pulse is preferably applied at the moment when the first voltage Vs is applied to the first sustain pulse or the second sustain pulse. In addition, sections in which the first voltage Vs is applied in the first sustain pulse and the second sustain pulse may overlap each other. In addition, the pulse width of the short pulse may be less than half of the pulse width of the first sustain pulse or the second sustain pulse. In addition, the voltage level of the short pulse may be smaller than or equal to that of the eighth voltage Va.

In the first sustain pulse and the second sustain pulse of FIG. 8, sections in which the first voltage Vs is applied do not overlap each other. In detail, from time t'1 to t'2, the first sustain pulse applied to the scan electrode lines Y1, ..., Yn has a rising slope and finally reaches the first voltage Vs. do. From time t'2 to t'3, the first sustain pulse continues to have the first voltage Vs. From time t'3 to t'4, the first sustain pulse has a falling slope and finally reaches the ground voltage Vg. The second sustain pulse applied to the sustain electrode lines has a ground voltage continuously from time t'1 to t'4. From time t'4 to t'5, the second holding pulse has a rising slope and finally reaches the first voltage Vs. From time t'5 to t'6, the second sustain pulse continues to have the first voltage Vs. From time t'6 to t'7, the second holding pulse has a falling slope and finally reaches the ground voltage Vg. From time t'4 to t'7, the first sustain pulse has a ground voltage. Next, from time t'7 to t'8, the first sustain pulse has a rising slope and finally reaches the first voltage, and the above process is repeated. The rising and falling slopes are typically used for energy charging and recovery. The first sustain pulse and the second sustain pulse of FIG. 8 are in the form of a non-overlapping waveform in which no section having the first voltage Vs is common.

In the case where the first sustain pulse has the first voltage Vs, the first positive voltage Vs applied to the scan electrode Y, the ground voltage Vg applied to the sustain electrode X, and the scan As the sustain discharge is performed due to the wall voltage due to the positive charge accumulated near the electrode Y and the wall voltage due to the negative charge accumulated near the sustain electrode X, a negative charge is accumulated near the scan electrode Y, and the sustain electrode A positive charge builds up near (X). At the moment when the first sustain pulse reaches the first voltage Vs, a short pulse is applied to the address electrode A. FIG.

Next, when the second sustain pulse has the first voltage Vs, the first positive voltage Vs applied to the sustain electrode X and the ground voltage Vg applied to the scan electrode Y are applied. And the sustain discharge is performed due to the wall voltage caused by the positive charge accumulated near the sustain electrode (X) and the wall voltage caused by the negative charge accumulated near the scan electrode (Y), and a positive charge is generated near the scan electrode (Y). The negative charges are accumulated near the sustain electrode (X). At the moment when the second sustain pulse reaches the first voltage Vs, a short pulse is applied to the address electrode A. FIG. The above steps are repeated continuously, which causes the sustain discharge to continue.

For example, when the first sustain pulse applied to the scan electrode Y has the first voltage Vs, the short pulse shifts a part of the negative charge accumulated on the scan electrode Y. In the plasma display panel of the present invention, since the scanning electrode (Y) and the sustain electrode (X) face each other, the sustain discharge is performed smoothly, and the discharge volume increases to the vicinity of the address electrode (A) due to the short pulse. The discharge efficiency is increased, and the brightness and life of the panel are improved. However, the pulse width of the applied short pulse is preferably less than half of the pulse width of the sustain pulse so that a large amount of negative charges are not drawn from the scan electrode Y due to the application of the short pulse, and the voltage of the short pulse of FIG. It is preferable that Vs2 is smaller than the eighth voltage Va. However, in consideration of an increase in manufacturing cost caused by supplying various powers from the power supply device, the voltage Vs2 of the short pulse of FIG. 8 may be equal to the magnitude of the eighth voltage Va.

According to the present invention as described above, the following effects can be obtained.

First, the plasma display panel of the present invention has a structure in which the sustain electrode (X) and the scan electrode (Y) are opposed to each other. Compared with the related art, the plasma display panel has a strong discharge during sustain discharge, thereby forming a large amount of space charge, thereby causing excitation of Xe. ) And ionization increases to increase the space priming particles inside the discharge cell, the discharge volume is increased, the discharge efficiency is increased, the brightness is also improved, the charged particles of the discharge gas to the phosphor By ion sputtering (ion sputtering) is reduced compared to the conventional, the life of the plasma display panel is improved.

Second, as the discharge efficiency increases, the magnitude of the first voltage Vs applied to the scan electrode Y during the sustain discharge can be reduced, and the magnitude of the eighth voltage Va applied during the address discharge can be reduced. This leads to a reduction in the manufacturing cost of a power supply for supplying power to the plasma display panel.

Third, even when a short pulse is applied to the address electrode in the sustain discharge period, the discharge volume is increased, the discharge efficiency is increased, and the luminance is improved.

Fourth, the period of the sustain discharge is accelerated by the overlapping waveform in which the section having the first voltage in common in the first sustain pulse and the second sustain pulse is present in the sustain discharge period, thereby improving the discharge efficiency.

Although the present invention has been described with reference to the embodiments shown in the drawings, this is merely exemplary, and it will be understood by those skilled in the art that various modifications and equivalent other embodiments are possible. Therefore, the true technical protection scope of the present invention will be defined by the technical spirit of the appended claims.

Claims (8)

A rear substrate disposed in parallel with the front substrate and the front substrate; Front barrier ribs disposed between the front substrate and the rear substrate, defining discharge cells together with the front substrate and the rear substrate, and formed of a dielectric; Address electrode lines disposed in a front dielectric layer formed on the front substrate in a direction toward the rear substrate, and including bus electrodes disposed on the front partition walls and transparent electrodes disposed on the discharge cells; Scan electrode lines and sustain electrode lines that are alternately disposed in the front partition walls to face each other, and are orthogonal to the address electrode lines; Rear barrier ribs disposed between the front barrier ribs and a rear dielectric layer formed in the front substrate direction on the rear substrate; A phosphor layer disposed in a space defined by the rear partitions; And a discharge gas in the discharge cell; Driven by a drive signal having a reset section, an address section, and a sustain discharge section, In the sustain discharge period, a first sustain pulse and a second sustain pulse having a rising slope and reaching a first voltage and having a falling slope and reaching a ground voltage are respectively applied to the scan electrode lines and the sustain electrode lines. Alternately applied to each other, and a short pulse is applied to the address electrode lines. The method of claim 1, In the reset period, a rising ramp signal is applied to the scan electrode lines at a first voltage to finally reach a third voltage rising by a second voltage, and a falling ramp signal is applied at the first voltage to finally generate a first voltage. Reaches a voltage of 4, a fifth voltage is applied from the falling ramp signal to the sustain electrode lines, and a ground voltage is applied to the address electrode lines; In the address period, a scan pulse having a seventh voltage is sequentially applied to the scan electrode lines while a sixth voltage is applied, and a display data signal having an eighth voltage is applied to the address electrodes according to the scan pulse. And a fifth voltage is applied to the scan electrode lines. The method of claim 2, And the short pulse is applied at the moment when the first voltage is applied from the first sustain pulse or the second sustain pulse. The method of claim 3, wherein And a section to which the first voltage is applied in the first sustain pulse and the second sustain pulse overlap each other. The method of claim 3, wherein And the sections to which the first voltage is applied in the first sustain pulse and the second sustain pulse do not overlap each other. The method according to any one of claims 4 to 5, And the pulse width of the short pulse is less than half of the pulse width of the first sustain pulse or the second sustain pulse. The method of claim 6, The short pulse has a ninth voltage, and the magnitude of the ninth voltage is smaller than the magnitude of the eighth voltage. The method of claim 6, The short pulse has a ninth voltage, and the magnitude of the ninth voltage is the same as that of the eighth voltage.

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