KR100576654B1 - Wafer level chip scale type semiconductor package - Google Patents

Abstract

The present invention relates to a wafer-level chip scale semiconductor package. In the present invention, a test-only semiconductor chip electrically connected to each semiconductor chip is disposed on a portion of a wafer, and an electrical burn-in test process is performed through the test-only semiconductor chip. Proceed smoothly.

When the present invention is achieved, since a test-only chip dedicated to electrical testing of each semiconductor chip is separately disposed on a part of the wafer, an electrical burn-in test process in a production line is performed without using out-contact terminals of the semiconductor chip. It is possible to proceed smoothly, and eventually, the production line can obtain the effect of preventing the unpredicted contamination of the out-contact terminals.

In addition, when the present invention is achieved, the production line appropriately adjusts the design rules of the test chips, irrespective of the shortening of each semiconductor chip, so that the test contact terminals disposed on the test chips are sufficiently separated. In this way, the socket of the test fixture can be induced to make an electrical contact with the test contact terminals with sufficient clearance, thereby ensuring the accuracy of the overall burn-in test process.

Description

Wafer level chip scale type semiconductor package

1 is an exemplary view showing a wafer level chip scale semiconductor package according to the present invention.

2 is an exemplary diagram showing a wiring layer of a wafer level chip scale semiconductor package according to an embodiment of the present invention.

3 is an exemplary diagram showing a wiring layer of a wafer level chip scale semiconductor package according to another embodiment of the present invention.

The present invention relates to a wafer-level chip-scale semiconductor package, and more particularly, a test-only semiconductor chip electrically connected to each semiconductor chip is separately disposed in a portion of the wafer, and the electrical burn-in is performed through the test-only semiconductor chip. The present invention relates to a wafer-level chip scale semiconductor package that can solve the problem of "contamination of contact terminals of semiconductor chips" and "problem of burn-in test process not progressing smoothly" by smoothly proceeding the test process.

In recent years, as memory capacities of electronic and information devices have increased, semiconductor chips have become increasingly integrated. Accordingly, the size of semiconductor chips has gradually increased.

However, in contrast to the increase in size of such semiconductor chips, packaging technologies for packaging semiconductor chips are moving toward the direction of making the size of the final semiconductor chip package light and small in accordance with the trend of miniaturization and light weight of electronic and information devices.

In recent years, with the rapid development of semiconductor chip packaging technology, surface-mount semiconductor packages such as BGA type semiconductor packages have been developed that can accommodate semiconductor chips of larger sizes while minimizing their size. In addition, as the technology continues to develop, chip-scale semiconductor packages such as FBGA type semiconductor packages and μBGA type semiconductor packages are being developed in which the size of the semiconductor package approaches 120% of the semiconductor chip size.

Various structures of such conventional chip scale semiconductor packages are described, for example, in US Pat. No. 56,63593, "Ball grid array package with lead frame," US Pat. No. 5,706,178, "Pads of the package." Ball grid array integrated circuit package that has vias located within the solder pads of a package ", US Patent No. 5708567" Ball Grid with Ring Type Heat Sink " Ball grid array semiconductor package with ring-type heat sink ", US Patent No. 5729050" Semiconductor package substrate and ball grid array semiconductor package using same ", US Patent No. 5741729" Ball grid array package for an integ rated circuit), US Pat. No. 5748450, "BGA package using a dummy ball and a repairing method," US Pat. No. 5796170, "Ball grid array integrated circuit." Packages (Ball grid array integrated circuit packages) ".

Recently, with the rapid development of semiconductor packaging technology, various methods of manufacturing the above-described chip scale semiconductor package at the wafer level have been proposed. In the conventional production line, the chip scale semiconductor package manufactured at the wafer level is generally called a "wafer level chip scale semiconductor package."

The conventional wafer level chip scale semiconductor package is manufactured into a final package product by performing various package manufacturing processes in a wafer state not separated into individual semiconductor chips.

For example, the above-described wafer level chip scale semiconductor package is subjected to an electrical burn-in test process in a wafer state not separated into individual semiconductor chips. An electrical burn-in test process is performed in a state in which a socket of a test prove) is directly in contact with an out contact terminal formed on each of the semiconductor chips in a wafer state.

Subsequently, the individual chips in the wafer state that have undergone the burn-in test process are subjected to the post-processing process and separated into individual chips, thereby completing the manufacture of semiconductor devices having excellent performance.

However, there are some significant problems in operating such a conventional wafer level chip scale semiconductor package.

As described above, in the conventional production line, when the electrical burn-in test process is performed with the wafer level chip scale semiconductor package, the test socket is directly contacted with the out contact terminals formed on the individual semiconductor chips in the wafer state. The contamination source such as particles existing in the test socket is transferred to the contact terminals of the semiconductor chips, thereby causing a problem that the reliability of the finally completed semiconductor device is significantly reduced.

Moreover, with the recent rapid development of semiconductor processing technology, the size of each semiconductor chip is also shortened. In this case, the contact distance between the contact terminal and the test socket is contacted in the production line because the above-mentioned contact distance becomes very fine. It is not possible to easily secure a free space, and eventually, the production line is forced to take serious problems that the electrical burn-in test process is not performed correctly.

Accordingly, an object of the present invention is to contact a semiconductor chip by arranging a test-only semiconductor chip electrically connected to each of the semiconductor chips in a portion of the wafer, and smoothly carrying out the electrical burn-in test process through the test-only semiconductor chip. This is to prevent the problem of the terminal contamination.

Another object of the present invention is to properly adjust the design rules of the above-described test-only semiconductor chip, to secure a sufficient space for contact between the test-only semiconductor chip contact terminal and the test socket, thereby improving the accuracy of the overall burn-in test process. To secure.

Still other objects of the present invention will become more apparent from the following detailed description and the accompanying drawings.

The wafer level chip scale semiconductor package of the present invention for achieving the above object is a plurality of semiconductor chips disposed on a portion of the surface of the wafer, and arranged in a line on the surface of the semiconductor chips, the external electrical signal Metal pads for transmitting to the signal lines inside the semiconductor chips, wiring layers disposed on the metal pads in electrical connection with the metal pads, and each of the metal layers in electrical connection with the wiring layers. It consists of a combination of out contact terminals exposed to the surface of the wiring layers. At this time, a part of the wafer except for the region in which the semiconductor chips are disposed is electrically connected to the test fixtures while being electrically connected to the wiring layers described above, and is a test dedicated to conducting an electrical test of each semiconductor chip. Dedicated chips are additionally placed.

When the present invention is achieved, since the test-only chips dedicated to the electrical testing of each semiconductor chip are separately disposed in some regions of the wafer, the electrical burn-in test is performed in the production line without using the out-contact terminals of the semiconductor chip. The process can be carried out smoothly, and eventually, the production line can achieve the effect of preventing the unexpected contact of the out- contact terminals.

In addition, when the present invention is achieved, the production line appropriately adjusts the design rules of the test chips, irrespective of the shortening of each semiconductor chip, so that the test contact terminals disposed on the test chips are sufficiently separated. In this way, the socket of the test fixture can be induced to make an electrical contact with the test contact terminals with sufficient clearance, thereby ensuring the accuracy of the overall burn-in test process.

Hereinafter, a wafer level chip scale semiconductor package according to the present invention will be described in detail with reference to the accompanying drawings.

As shown in FIG. 1, the wafer level chip scale semiconductor package according to the present invention is generally a combination of a wafer 1 and a plurality of semiconductor chips 10 arranged on the surface of the wafer 1. Is done.

At this time, a plurality of metal pads 11 are arranged in a line on the surface of each of the semiconductor chips 10, the metal pads 11 is an electrical signal transmitted from the outside in the semiconductor chips 10 It plays a role of transmitting to signal lines (not shown).

Here, a plurality of wiring lines 12 are arranged on a surface of each of the semiconductor chips 10 described above, and the wiring lines 12 are electrically connected to the metal pads 11 in an external state. It serves to deliver the signal to the metal pads (11).

In this case, each of the semiconductor chips 10 is formed with a series of conductive paths consisting of "wiring line 12-metal pad 11-signal line".

At this time, as shown in the figure, a test-only chip electrically connected to the aforementioned wiring layers 12 on another surface of the wafer 1 except for the region where the semiconductor chips 10 are disposed. 20 is further arranged. The test dedicated chip 20 is in electrical contact with an external test fixture, for example, a test probe, in electrical contact with a portion of the above-described wiring layers 12 to electrically test each of the semiconductor chips 10. It is responsible for the progress.

Such a test structure of the test chip 20 constitutes the gist of the present invention. Of course, the test chip is not disposed at all in the conventional wafer level chip scale semiconductor package.

Conventionally, in the production line, the test probes are directly contacted with the sockets of the test probes to the out contact terminals formed on the individual semiconductor chips in the wafer state, and the electrical burn-in test process of the wafer level chip scale semiconductor package is performed. The contamination source such as particles existing in the test socket is transferred to the out contact terminals of the semiconductor chips, thereby causing a problem that the reliability of the finally completed semiconductor device is significantly reduced.

However, in the case of the present invention, as described above, since the test-only chip 20 dedicated to the electrical test of each of the semiconductor chips 10 is disposed on the wafer 1 separately, the semiconductor chip ( The electrical burn-in test process can be performed smoothly without using the out-contact terminals of 10). As a result, the production line can prevent the unexpected contact of the out-contact terminals.

In addition, in the conventional case, as the semiconductor chips are shortened, the separation distance of the out-contact terminals becomes minute, and in the production line, it is not easy to secure a free space for the contact between the out-contact terminals and the test probe sockets. In the end, the conventional production line was forced to take the problem that the electrical burn-in test process is not exactly made.

However, when the present invention is achieved, regardless of the shortening of each semiconductor chip 10 in the production line, by appropriately adjusting the design rules of the test-only chip 20 disposed separately from the semiconductor chips 10 To ensure sufficient separation distance between the test contact terminals 21 disposed on the test dedicated chip 20, the socket of the test probe is electrically contacted with a sufficient clearance with the test contact terminals 21. By being able to induce relationships, the accuracy of the overall burn-in test process is more flexible.

At this time, as shown in FIG. 2, the above-described out-contact terminals 16 are disposed on the surfaces of the wiring layers 12 disposed on the substrate 13 of the semiconductor chip 10. The fields 16 form a structure exposed to the surfaces of the wiring layers 12 in a state of being in electrical contact with the wiring layers 12.

The semiconductor chip 10 having such a structure is separated into two semiconductor chips 10a and 10b around the scribing line S according to a post-processing process, for example, a scribing process.

At this time, according to one embodiment of the present invention, each of the wiring layers 12 and the contact layer wiring layer 12a for electrically connecting the out-contact terminals 16 and the metal pads 11 mentioned above. And a combination of test terminal wiring layers 12b electrically contacting the test terminals 21 of the test-only chip 20 while being electrically connected to the contact terminal wiring layers 12a.

Here, the contact layer wiring layer 12a is, for example, penetrated through the insulating layer 14 in the state where its end is in contact with the out contact terminals 16, and is bent first, so that the other end thereof is the metal pad. The test terminal wiring layer 12b extends to one side of the wafer 1 in a state in which a part of the traveling line is in contact with the contact terminal wiring lead 12a. It forms a structure in which its end is brought into contact with the test terminals 21.

In this state, when the electrical burn-in test process is performed, the test terminals 21 of the test-only chip 20 are electrical signals output from the semiconductor chips 10 through the test terminal wiring layer 12b. In the production line, the test terminals 21 can be contacted with the sockets of the test fruit part, so that the electrical burn-in characteristics of the semiconductor chips 10 can be smoothly tested. .

On the other hand, as shown in Figure 3, according to another embodiment of the present invention, the wiring layers 32 in a single layer state, the electrical contact with the above-described out-contact terminals 36 and metal pads 31 At the same time, it forms a structure in electrical contact with the test terminals of the test-only chips. At this time, reference numeral 33 is a substrate of the semiconductor chip 10.

In this case, a portion of the wiring layer 32 penetrates the insulating layer 35 and further includes connection patterns 34 for electrically connecting the wiring layer 32 and the out contact terminals 36. Through the connection patterns 34, the wiring layer may electrically connect the out-contact terminals 36 and the metal pads 31 to each other at the same time. At this time, the wiring layer 32 extends to one side of the wafer 1 in a state in which a part of the traveling line is in contact with the above-described connection patterns 34 so that its end portion is in contact with the test terminal 21. Form a structure.

In this state, when the electrical burn-in test process is performed, the test terminals 21 of the test-only chip 20 may receive electrical signals output from the semiconductor chips through the wiring layer 32. In the production line, the test terminals 21 can be contacted with the sockets of the test fruit portion, thereby enabling the electrical burn-in characteristics of the semiconductor chips 10 to be smoothly tested.

When another embodiment of the present invention is applied, since there is no need to divide the wiring layer into contact layer wiring layers and test terminal wiring layers in the production line, an advantage of simplifying the overall semiconductor package manufacturing process can be obtained.

In short, when the above-described embodiments of the present invention are applied, since the electrical burn-in test process can be performed smoothly in the production line without using the out-contact terminals of the semiconductor chip, the out-contact terminals are contaminated. This can be prevented in advance.

In addition, regardless of the size of each semiconductor chip in the production line, by appropriately adjusting the design rules of the test-only chips, to ensure sufficient separation distance of the test contact terminals arranged on the test-only chips, thereby, the test probe The socket of can be induced to make an electrical contact with the test contact terminals with sufficient clearance, so that the accuracy of the overall burn-in test process can be secured more flexibly.

Subsequently, the individual chips in the wafer state that have undergone the burn-in test process are subjected to the post-processing process and separated into individual chips, thereby completing the manufacture of semiconductor devices having excellent performance.

As described above, in the present invention, by arranging a test-only semiconductor chip electrically connected to each of the semiconductor chips, and smoothly carrying out the electrical burn-in test process through the test-only semiconductor chip, the contact terminals of the semiconductor chip are contaminated. Problems "," problems that the burn-in test process is not progressing smoothly "and the like can be solved in advance.

This invention has an overall useful effect in various varieties of chip scale semiconductor packages requiring electrical test processes.

And while certain embodiments of the invention have been described and illustrated, it will be apparent that the invention may be embodied in various modifications by those skilled in the art.

Such modified embodiments should not be understood individually from the technical spirit or point of view of the present invention and such modified embodiments should fall within the scope of the appended claims of the present invention.

As described in detail above, in the wafer level chip scale semiconductor package according to the present invention, a test-only semiconductor chip electrically connected to each of the semiconductor chips is separately disposed on a portion of the wafer, and electrical burn-in is performed through the test-only semiconductor chip. Proceed smoothly with the test process.

When the present invention is achieved, since the test-only chips dedicated to the electrical test of each semiconductor chip are arranged separately, the electrical burn-in test process is smoothly performed in the production line without using the out-contact terminals of the semiconductor chip. As a result, the production line can achieve the effect of preventing the unexpected contact of the out- contact terminals.

In addition, when the present invention is achieved, the production line appropriately adjusts the design rules of the test chips, irrespective of the shortening of each semiconductor chip, so that the test contact terminals disposed on the test chips are sufficiently separated. In this way, the socket of the test fixture can be induced to make an electrical contact with the test contact terminals with sufficient clearance, thereby ensuring the accuracy of the overall burn-in test process.

Claims (3)

A plurality of semiconductor chips disposed on the wafer; Metal pads arranged in a line on the surfaces of the semiconductor chips and transferring external electrical signals to signal lines inside the semiconductor chips; Wiring layers disposed on surfaces of the semiconductor chips in electrical connection with the metal pads; An out contact terminal exposed to the surface of the wiring layers in an electrically connected state with the wiring layers; A test-only chip that is in electrical contact with an external test fixture in an electrically connected state with the wiring layers in other regions of the wafer except for the region in which the semiconductor chips are disposed, and is dedicated to conducting an electrical test of the semiconductor chips. Wafer-type chip scale semiconductor package, characterized in that the arrangement. The semiconductor device of claim 1, wherein the wiring layers comprise: a wiring layer for contact terminals electrically connecting the out contact terminals and the metal pads; A wafer level chip scale semiconductor package comprising a combination of test terminal wiring layers in electrical contact with test terminals of the test-only chips in electrical connection with the contact terminal wiring layers. The method of claim 1, wherein the wiring layers are electrically connected to the test terminals of the test-only chips while electrically connecting the out-contact terminals and the metal pads in a single layer. Wafer level chip scale semiconductor package.

Images