KR100564420B1 - Gate electrode ion implantation method - Google Patents
Gate electrode ion implantation method Download PDFInfo
- Publication number
- KR100564420B1 KR100564420B1 KR1019980063672A KR19980063672A KR100564420B1 KR 100564420 B1 KR100564420 B1 KR 100564420B1 KR 1019980063672 A KR1019980063672 A KR 1019980063672A KR 19980063672 A KR19980063672 A KR 19980063672A KR 100564420 B1 KR100564420 B1 KR 100564420B1
- Authority
- KR
- South Korea
- Prior art keywords
- dopant
- tungsten silicide
- silicide layer
- ion implantation
- gate electrode
- Prior art date
Links
- 238000000034 method Methods 0.000 title claims abstract description 28
- 238000005468 ion implantation Methods 0.000 title claims abstract description 18
- 239000002019 doping agent Substances 0.000 claims abstract description 41
- WQJQOUPTWCFRMM-UHFFFAOYSA-N tungsten disilicide Chemical compound [Si]#[W]#[Si] WQJQOUPTWCFRMM-UHFFFAOYSA-N 0.000 claims abstract description 33
- 229910021342 tungsten silicide Inorganic materials 0.000 claims abstract description 33
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims abstract description 27
- 229920005591 polysilicon Polymers 0.000 claims abstract description 27
- 229910052698 phosphorus Inorganic materials 0.000 claims abstract description 25
- 239000011574 phosphorus Substances 0.000 claims abstract description 25
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 claims abstract description 22
- 239000004065 semiconductor Substances 0.000 claims abstract description 19
- 239000000758 substrate Substances 0.000 claims abstract description 12
- 238000002347 injection Methods 0.000 claims abstract description 8
- 239000007924 injection Substances 0.000 claims abstract description 8
- 238000004140 cleaning Methods 0.000 claims description 5
- 238000007598 dipping method Methods 0.000 claims description 4
- 239000011259 mixed solution Substances 0.000 claims description 4
- 241000252506 Characiformes Species 0.000 claims description 3
- 150000002500 ions Chemical class 0.000 description 6
- 238000010438 heat treatment Methods 0.000 description 4
- -1 phosphorus ions Chemical class 0.000 description 4
- 230000005611 electricity Effects 0.000 description 3
- 230000005669 field effect Effects 0.000 description 3
- 238000005229 chemical vapour deposition Methods 0.000 description 2
- 238000009792 diffusion process Methods 0.000 description 2
- 206010010144 Completed suicide Diseases 0.000 description 1
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 1
- 239000003990 capacitor Substances 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 238000009826 distribution Methods 0.000 description 1
- 230000005685 electric field effect Effects 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 238000010030 laminating Methods 0.000 description 1
- WABPQHHGFIMREM-UHFFFAOYSA-N lead(0) Chemical compound [Pb] WABPQHHGFIMREM-UHFFFAOYSA-N 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 229910044991 metal oxide Inorganic materials 0.000 description 1
- 150000004706 metal oxides Chemical class 0.000 description 1
- 238000000926 separation method Methods 0.000 description 1
- 229910052814 silicon oxide Inorganic materials 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/26—Bombardment with radiation
- H01L21/263—Bombardment with radiation with high-energy radiation
- H01L21/265—Bombardment with radiation with high-energy radiation producing ion implantation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02041—Cleaning
- H01L21/02057—Cleaning during device manufacture
- H01L21/02068—Cleaning during device manufacture during, before or after processing of conductive layers, e.g. polysilicon or amorphous silicon layers
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
- H01L21/28008—Making conductor-insulator-semiconductor electrodes
- H01L21/28017—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon
- H01L21/28026—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor
- H01L21/28035—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor the final conductor layer next to the insulator being silicon, e.g. polysilicon, with or without impurities
- H01L21/28044—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor the final conductor layer next to the insulator being silicon, e.g. polysilicon, with or without impurities the conductor comprising at least another non-silicon conductive layer
- H01L21/28061—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor the final conductor layer next to the insulator being silicon, e.g. polysilicon, with or without impurities the conductor comprising at least another non-silicon conductive layer the conductor comprising a metal or metal silicide formed by deposition, e.g. sputter deposition, i.e. without a silicidation reaction
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Power Engineering (AREA)
- High Energy & Nuclear Physics (AREA)
- Toxicology (AREA)
- Health & Medical Sciences (AREA)
- Chemical & Material Sciences (AREA)
- Chemical Kinetics & Catalysis (AREA)
- Insulated Gate Type Field-Effect Transistor (AREA)
- Electrodes Of Semiconductors (AREA)
Abstract
본 발명은 게이트전극의 텅스텐실리사이드층에 도핑하는 방법에 관한 것으로서, 반도체기판에 게이트산화막, 도펀트가 도핑된 폴리실리콘층 및 텅스텐실리사이드층이 순차적으로 적층된 게이트전극에서, 전원으로부터 전기를 인가 받아 RF플라즈마를 발생하는 플라즈마발생수단과; 상기 플라즈마발생수단으로 부터 연결되어 일측 극성이 반도체기판에 접속되고, 타측 극성이 접속되어서 PH3 를 전기적으로 분해하여 도펀트인 인을 텅스텐실리사이드층으로 주입하도록 하는 도펀트주입수단으로 구성된 도펀트주입장치 및 그를 이용하여 도펀트인 인을 텅스텐실리사이드층에 헤비도핑으로 주입하도록 하는 게이트전극 이온주입방법인 바, 폴리실리콘층에 비하여 텅스텐실리사이드층에 인을 헤비도핑하므로 도펀트의 디플리션(Depletion)을 방지하여 인벌스 커패시턴스(Cinv)의 강하가 발생되는 것을 억제하므로 반도체장치의 전기적인 특성을 향상시키도록 하는 매우 유용하고 효과적인 발명이다.The present invention relates to a method of doping a tungsten silicide layer of a gate electrode, in which a gate oxide film, a polysilicon layer doped with a dopant, and a tungsten silicide layer are sequentially stacked on a semiconductor substrate, by receiving electric power from a power source Plasma generating means for generating a plasma; A dopant injection device comprising dopant injection means connected to the plasma generating means and having one polarity connected to the semiconductor substrate and the other polarity connected to electrically decompose PH 3 to inject a dopant phosphorus into the tungsten silicide layer; It is a gate electrode ion implantation method that injects dopant phosphorus into the tungsten silicide layer by heavy doping. As a result, heavy doping of phosphorus into the tungsten silicide layer compared to the polysilicon layer prevents depletion of the dopant. It is a very useful and effective invention to improve the electrical characteristics of the semiconductor device because it suppresses the occurrence of the drop in the volume capacitance (C inv ).
Description
본 발명은 트랜지스터에 이온을 헤비 도핑하는 것에 관한 것으로, 특히, 텅스텐실리사이드층에 도펀트인 인 이온을 폴리실리콘층에 비하여 헤비 도핑하므로 후속 열공정에서 인이 폴리실리콘층으로 확산되므로 도펀트의 디플리션(Depletion)을 방지하고 인벌스 커패시턴스(Inverse Capacitance)의 강하가 발생되는 것을 방지하도록 하는 게이트전극 이온주입방법에 관한 것이다.The present invention relates to the heavy doping of ions in a transistor, in particular, the heavy doping of phosphorus ions as a dopant in the tungsten silicide layer compared to the polysilicon layer, so that in the subsequent thermal process, phosphorus diffuses into the polysilicon layer and thus depletion of the dopant The present invention relates to a gate electrode ion implantation method which prevents depletion and prevents a drop in inverse capacitance from occurring.
일반적으로, 반도체장치의 종류에는 여러 가지가 있으며, 이 반도체장치 내에 형성되는 트랜지스터 및 커패시터등을 구성시키는 방법에는 다양한 제조기술이 사용되고 있으며, 최근에는 반도체기판 상에 산화막을 입혀 전계효과를 내도록 하는 모스형 전계효과 트랜지스터(MOS FET; metal oxide semiconductor field effect transistor)를 점차적으로 많이 사용하고 있는 실정에 있다.In general, there are many kinds of semiconductor devices, and various manufacturing techniques are used to configure transistors, capacitors, etc. formed in the semiconductor device, and in recent years, MOS is formed to apply an oxide film on a semiconductor substrate to produce an electric field effect. Background Art [0002] Metal oxide semiconductor field effect transistors (MOS FETs) are increasingly being used.
상기한 모스형 전계효과 트랜지스터는 반도체 기판상에 형성된 게이트가 반도체 층에서 얇은 산화 실리콘막에 의해 격리되어 있는 전계효과 트랜지스터로 접합형과 같이 임피던스가 저하되는 일이 없으며, 확산 공정이 1회로 간단하고, 소자간의 분리가 필요 없는 장점을 지니고 있어서, 고밀도 집적화에 적합한 특성을 지니고 있는 반도체 장치이다.The MOS type field effect transistor is a field effect transistor in which a gate formed on a semiconductor substrate is isolated by a thin silicon oxide film in a semiconductor layer, and the impedance is not lowered like a junction type, and the diffusion process is simple. The semiconductor device is advantageous in that it does not require separation between devices, and is suitable for high density integration.
도 1(a)는 종래의 트랜지스터 게이트전극의 구성을 보인 도면으로서, 반도체기판(1)에 게이트산화막(2)을 적층한 후 도핑된 폴리실리콘층(3)을 적층하고, 그 위에 연속하여 텡스텐실리사이드층(5) 및 마스크산화막(6)을 적층하고 식각하여서 게이트전극을 형성하게 된다.FIG. 1A is a view showing a conventional transistor gate electrode, in which a gate oxide film 2 is laminated on a semiconductor substrate 1, and then a doped polysilicon layer 3 is laminated and successively stacked on the semiconductor substrate 1. The stencil suicide layer 5 and the mask oxide film 6 are stacked and etched to form a gate electrode.
도 1(b)는 도1(a)의 게이트전극의 폴리실리콘층에 도핑된 인이 농도 구배를 보인 도면으로서, 폴리실리콘층(3)에 도핑된 인(Phosphorous)이 높이에 관계없이 거의 동일하게 분포된 농도구배선(8)을 갖는 상태를 보이고 있다.FIG. 1 (b) shows a concentration gradient of phosphorus doped in the polysilicon layer of the gate electrode of FIG. 1 (a), wherein phosphorus doped in the polysilicon layer 3 is almost the same regardless of height. It shows a state having a concentration gradient line (8).
그런데, 종래의 폴리실리콘층(3)에 도핑된 인은 전체적으로 균일하게 분포되어지는 관계로 후속 열처리공정에서 고온의 열이 게이트전극에 가하여지면, 도 2(a)에 도시된 바와 같이, 종래 게이트전극에 열처리를 수행하여서 폴리실리콘층(3)에 도핑된 인이 확산(Diffusion)에 의하여 상측에 인접한 텅스텐실리사이드층(5)을 이동하게 되면서, 도 2(b)에서와 같이, 폴리실리콘층(3)의 인이 도핑된 상태에서 농도구배선(8')이 전체적으로 불균일하게 분포되므로 게이트산화막(2)과 접하는 부분의 폴리실리콘층(3)의 인의 도핑농도는 상대적으로 약화되어진다However, since the phosphorus doped in the conventional polysilicon layer 3 is uniformly distributed as a whole, when a high temperature heat is applied to the gate electrode in a subsequent heat treatment process, as shown in FIG. Phosphorus doped in the polysilicon layer 3 by performing heat treatment on the electrode moves the tungsten silicide layer 5 adjacent to the upper side by diffusion, and as shown in FIG. 2 (b), the polysilicon layer ( In the doped state of 3), the concentration gradient line 8 'is unevenly distributed as a whole, so that the doping concentration of phosphorus in the polysilicon layer 3 in contact with the gate oxide film 2 is relatively weakened.
따라서, 도 3에 도시된 바와 같이, 전압과 커패시턴의 관계를 도시한 그래프인 C-V곡선에서 인벌스 커패시턴스(Inverse Capacitance)가 강하(Drop) 되어지는 현상이 발생되고, 이 현상은 전류값을 변화시킬 뿐만 아니라 Vt 값을 변화시키므로 반도체장치의 전기적인 특성을 안정화시키는 데 저해 요인으로 작용하는 문제점이 있었다.Accordingly, as shown in FIG. 3, an inverse capacitance is dropped in the CV curve, which is a graph showing the relationship between voltage and capacitance, and this phenomenon causes a current value. In addition to changing the V t value, there is a problem that acts as a deterrent to stabilize the electrical characteristics of the semiconductor device.
본 발명은 이러한 점을 감안하여 안출한 것으로서, 텅스텐실리사이드층에 도펀트인 인 이온을 폴리실리콘층에 비하여 헤비 도핑하므로 후속 열공정에서 인이 폴리실리콘층으로 확산되므로 도펀트의 디플리션(Depletion)을 방지하고 인벌스 커패시턴스(Inverse Capacitance)의 강하가 발생되는 것을 방지하도록 하는 것이 목적이다.The present invention has been made in view of this point, and since the heavy doping of the dopant phosphorus ions in the tungsten silicide layer compared to the polysilicon layer, phosphorus diffuses into the polysilicon layer in a subsequent thermal process, thereby preventing depletion of the dopant. The purpose is to prevent the occurrence of a drop in Inverse Capacitance.
이러한 목적은 반도체기판에 게이트산화막, 도펀트인 인이 균일하게 도핑된 폴리실리콘층 및 텅스텐실리사이드층을 적층하는 단계와; 상기 텅스텐실리사이드층 상에 전원으로 부터 전기를 인가 받은 도펀트주입수단으로 RF 플라즈마를 발생하여 PH3 에서 도펀트인 P을 샤워링하여 텅스텐실리사이드층에 도핑시키는 단계와; 상기 단계 후에 텅스텐실리사이드층 상에 예정된 순서로 공정을 진행하여 게이트전극을 형성하는 단계를 포함하여 이루어진 게이트전극 이온주입방법을 제공하도록 한다.This object comprises the steps of laminating a gate oxide film, a polysilicon layer doped with phosphorus as a dopant and a tungsten silicide layer on a semiconductor substrate; Generating an RF plasma with a dopant injection means applied with electricity from a power source on the tungsten silicide layer and showering P, which is a dopant at PH 3 , and doping the tungsten silicide layer; After the step is to provide a gate electrode ion implantation method comprising the step of forming a gate electrode by a process in a predetermined order on the tungsten silicide layer.
이하, 첨부한 도면에 의거하여 본 발명에 바람직한 일실시예에 대하여 상세히 설명한다.Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings.
도 3은 일반적인 전압과 커패시턴스와의 관련된 상태 그래프로서, 농도구배변화에 의하여 인벌스 커패시턴스가 강하된 상태를 보인 도면이고, 도 4는 본 발명에 따른 이온주입장치를 이용하여 포스포러스를 텅스텐실리사이드층에 주입하는 상태를 보인 도면이고, 도 5(a)는 본 발명의 이온주입장치를 이용하여 도펀트인 인을 주입한 상태를 보인 그래프이며, 도 5(b)는 본 발명의 이온주입장치를 이용하여 도펀트를 주입한 상태에서 후속 열공정을 진행한 후의 상태를 보인 그래프이다.FIG. 3 is a state graph related to a general voltage and capacitance, and shows a state in which the involes capacitance is lowered due to a concentration gradient change, and FIG. 4 is a tungsten silicide layer containing phosphorus using an ion implantation apparatus according to the present invention. 5 (a) is a graph showing a state of implanting phosphorus as a dopant using the ion implantation apparatus of the present invention, Figure 5 (b) uses the ion implantation apparatus of the present invention This is a graph showing the state after the subsequent thermal process in the dopant injected state.
본 발명의 장치 구성은 반도체기판(10)에 게이트산화막(20), 도펀트(50)가 도핑된 폴리실리콘층(30) 및 텅스텐실리사이드층(40)이 순차적으로 적층된 게이트전극에서, 전원(70)으로부터 전기를 인가 받아 RF플라즈마를 발생하는 플라즈마발생수단(90)과; 상기 플라즈마발생수단(80)으로 부터 연결되어 도선(90)의 일측 극성이 반도체기판(10)에 접속되고, 타측 극성이 접속되어서 PH3 를 플라즈마 상태로 만들어 도펀트(50)인 인을 텅스텐실리사이드층(40)으로 주입하도록 하는 도펀트주입수단(60)으로 구성된다.The device configuration of the present invention is a power source 70 in the gate electrode in which the gate oxide film 20, the polysilicon layer 30 doped with the dopant 50 and the tungsten silicide layer 40 are sequentially stacked on the semiconductor substrate 10. Plasma generating means (90) for generating an RF plasma by receiving electricity from the; The tungsten silicide layer is formed of the dopant 50 which is connected to the plasma generating means 80 and has one side polarity of the conductive line 90 connected to the semiconductor substrate 10 and the other side polarity connected to make PH 3 in a plasma state. It is composed of a dopant injection means 60 to be injected into the (40).
상기 플라즈마발생수단(80)은 RF 플라즈마를 발생하는 장치를 이용하고, 상기 도펀트주입수단(60)은 도선(90)의 일단에 연결되어 플라즈마를 공급하는 전극(62)과; 상기 전극(62)으로 전달된 플라즈마로 인하여 전리된 도펀트(50)인 인이 저장되어 텅스텐실리사이드층(40)에 공급되도록 하는 챔버(64)로 구성된다.The plasma generating means (80) uses an apparatus for generating an RF plasma, and the dopant injection means (60) is connected to one end of the conductive wire (90) for supplying a plasma; The phosphor 64, which is an ionized dopant 50 due to the plasma delivered to the electrode 62, is stored and supplied to the tungsten silicide layer 40.
이하, 본 발명의 장치를 이용하여 게이트전극에 이온을 주입하는 방법을 살펴보도록 한다.Hereinafter, a method of implanting ions into the gate electrode using the apparatus of the present invention will be described.
도 4에 도시된 바와 같이, 반도체기판(10)에 게이트산화막(20), 도펀트(50)인 인이 균일하게 도핑된 폴리실리콘층(30) 및 텅스텐실리사이드층(40)을 적층하도록 한다.As shown in FIG. 4, the gate oxide film 20, the polysilicon layer 30 and the tungsten silicide layer 40 doped with phosphorus as a dopant 50 are uniformly stacked on the semiconductor substrate 10.
그리고, 상기 텅스텐실리사이드층(40)상에 전원(70)으로 부터 전기를 인가 받은 도펀트주입수단(60)으로 RF 플라즈마를 발생하여 PH3 를 전리하고, 도펀트인 P이온을 샤워링(Showering)하여 텅스텐실리사이드층(40)에 하부의 폴리실리콘층(30)에 비하여 헤비 도핑(Heavy Dopping)시키도록 한다.Then, the plasma is generated on the tungsten silicide layer 40 by the dopant injection means 60, which is supplied with electricity from the power source 70, to ionize PH 3 , and shower the P ions, which are dopants, by showering. Heavy doping is performed on the tungsten silicide layer 40 as compared to the lower polysilicon layer 30.
이때, 상기 플라즈마발생수단(80)은 13.56MHZ를 갖는 고효율성 RF바이어스(RF Bias)를 이용한 플라즈마를 도펀트주입수단(60)에 전달하여 도펀트(50)인 인 이온을 발생하도록 한다.In this case, the plasma generating means 80 delivers a plasma using a high efficiency RF bias having 13.56MHZ to the dopant injection means 60 to generate phosphorus ions that are the dopant 50.
그리고, 상기 PH3의 양은 100sccm 이상으로 공급하고, 샤워링 처리 시간은 20 ∼ 400 초간이며, RF파워(RF Power)는 50 ∼ 200W정도로 한다.The amount of PH 3 is supplied at 100 sccm or more, the showering time is 20 to 400 seconds, and the RF power is about 50 to 200 W.
그리고, PH3의 샤워링시 웨이퍼(Wafer)는 400∼800℃의 온도에서 진행하도록 하고, 상기 PH3의 샤워링시 웨이퍼를 미리 세정공정(Pre-Cleaning)을 거쳐 이물질을 제거하도록 한다.In addition, during the showering of PH 3 , the wafer proceeds at a temperature of 400 to 800 ° C., and when the showering of the PH 3 is performed, the wafer is previously removed through a pre-cleaning process.
또한, 상기 웨이퍼를 클리닝하는 공정은 피란하(Piranha) 및 희석된 HF 혼합용액에 2초 이상 디핑(Diping)하여 이루어지거나 혹은 피란하 및 BOE 혼합용액에 10초 이상 디핑하여 이루어진다.In addition, the wafer cleaning process is performed by dipping for 2 seconds or more in Piranha and diluted HF mixed solution, or dipping for 10 seconds or more in Piranha and BOE mixed solution.
그리고, 상기 텅스텐실리사이드층(40)은 SiH4 또는 SiH2Cl4 가스와 WF6 가스를 소오스가스로 하여 CVD법(Chemical Vapor Deposition)으로 적층되도록 한다.In addition, the tungsten silicide layer 40 may be deposited by CVD (Chemical Vapor Deposition) using SiH 4 or SiH 2 Cl 4 gas and WF 6 gas as a source gas.
그리고, 상기 단계 후에 텅스텐실리사이드층(40) 상에 예정된 순서로 공정을 진행하여 게이트전극을 형성하도록 한다.After the step, the process is performed on the tungsten silicide layer 40 in a predetermined order to form a gate electrode.
한편, 도 5(a)에서와 같이, 베이스(Base)라 표시된 점선은 도펀트(50)인 인이 주입되지 않은 상태를 도시한 도면이고, 실 선으로 표시된 부분은 베이스에다 텅스텐실리사이드층(40)에 도펀트(50)인 인이 주입된 상태를 표시한 것으로서, 웨이퍼의 깊이에 대하여 도펀트(50)가 분포된 상태를 보이고 있다. On the other hand, as shown in Fig. 5 (a), the dotted line denoted as the base (Base) is a view showing a state in which the dopant 50, phosphorus is not injected, the portion indicated by the solid line is a base on the tungsten silicide layer 40 Phosphorus, which is a dopant 50, is injected into the dopant 50. The dopant 50 is distributed with respect to the depth of the wafer.
그리고, 도 5(b)는 웨이퍼를 후속 열처리공정을 진행한 후에 웨이퍼의 주요부분에 도펀트(50)가 재 분포된 상태를 도시한 것으로서, 도핑이 이루어지지 않은 경우에 비하여 도펀트주입장치로 도펀트(50)를 텅스텐실리사이드층(40)에 주입한 실 선의 경우가 베이스 상태인 점선의 경우 보다 도펀트(50)의 분포가 균일하게 나타나게 된다. 5 (b) shows a state in which the dopant 50 is redistributed to the main portion of the wafer after the wafer is subjected to a subsequent heat treatment process, and the dopant (FIG. In the case of the solid line injected 50 into the tungsten silicide layer 40, the distribution of the dopant 50 is more uniform than that of the dotted line in the base state.
이와 같이, 상기 텅스텐실리사이드층(40)에 하부의 폴리실리콘층(30)에 비하여 인이 헤비 도핑된 상태에서 후속 열공정을 진행하더라도 텅스텐실리사이드층(40)의 헤비 도핑된 인이 오히려 폴리실리콘층(30)으로 이동하므로 폴리실리콘층(30)의 인 농도가 낮아짐으로 인하여 발생되는 디플리션을 방지하게 된다. As described above, even if the tungsten silicide layer 40 is subjected to a subsequent thermal process in a state in which phosphorus is heavily doped in comparison with the lower polysilicon layer 30, the heavy doped phosphorus of the tungsten silicide layer 40 is rather polysilicon layer. Since it moves to 30 to prevent the depletion caused by the low phosphorus concentration of the polysilicon layer 30.
따라서, 상기한 바와 같이 본 발명에 따른 게이트전극 이온주입방법을 이용하게 되면, 텅스텐실리사이드층에 도펀트인 인 이온을 하부의 폴리실리콘층에 비하여 헤비 도핑하여 후속 열처리공정시 폴리실리콘층에 도핑된 도펀트들이 텅스텐실리사이드층으로 확산되지 않고 오히려 텅스텐실리사이드층에 있는 도펀트가 폴리실리콘층에 확산되므로 도펀트의 디플리션(Depletion)을 방지하고 인벌스 커패시턴스(Inverse Capacitance)의 강하가 발생되는 것을 방지하므로 반도체장치의 전기적인 특성을 향상시키도록 하는 매우 유용하고 효과적인 발명인 것이다.Therefore, when the gate electrode ion implantation method according to the present invention is used as described above, the dopant doped in the polysilicon layer during the subsequent heat treatment process by heavy doping the phosphorus ion, which is a dopant in the tungsten silicide layer, than the polysilicon layer below Do not diffuse into the tungsten silicide layer, but rather the dopant in the tungsten silicide layer diffuses into the polysilicon layer, thereby preventing depletion of the dopant and preventing a decrease in inverse capacitance. It is a very useful and effective invention to improve the electrical properties of the.
도 1(a)(b)는 종래의 트랜지스터 게이트전극의 구성과 폴리실리콘층에 주입된 도펀트의 농도구배를 보인 도면. 1 (a) and (b) show a structure of a conventional transistor gate electrode and a concentration gradient of a dopant injected into a polysilicon layer.
도 2(a)(b)는 도 1(a)(b)에 도시된 게이트전극에 열공정을 거치면서 변화된 상태를 도시한 도면. 2 (a) and 2 (b) are diagrams illustrating a state changed through thermal processing of the gate electrode illustrated in FIGS. 1 (a) and 2 (b).
도 3은 일반적인 전압과 커패시턴스와 관련된 상태 그래프로서, 농도구배변화에 의하여 인벌스 커패시턴스가 강하된 상태를 보인 도면. FIG. 3 is a state graph related to a general voltage and capacitance, in which the inverse capacitance is dropped due to a concentration gradient change. FIG.
도 4는 본 발명에 따른 이온주입장치를 이용하여 인을 텅스텐실리사이드층에 주입하는 상태를 보인 도면. 4 is a view showing a state in which phosphorus is injected into the tungsten silicide layer using the ion implantation apparatus according to the present invention.
도 5(a)는 본 발명의 이온주입장치를 이용하여 이온을 주입한 상태를 보인 그래프.Figure 5 (a) is a graph showing a state in which ions are implanted using the ion implantation apparatus of the present invention.
도 5(b)는 본 발명의 이온주입장치를 이용하여 이온을 주입한 상태에서 후속 열공정을 진행한 후의 상태를 보인 그래프.Figure 5 (b) is a graph showing a state after the subsequent thermal process in the state of implanting ions using the ion implantation apparatus of the present invention.
-도면의 주요부분에 대한 부호의 설명-Explanation of symbols on the main parts of the drawing
10 : 반도체기판 20 : 게이트산화막10: semiconductor substrate 20: gate oxide film
30 : 도핑된 폴리실리콘층 40 : 텅스텐실리사이드층 30 doped polysilicon layer 40 tungsten silicide layer
50 : 이온 60 : 이온주입수단50: ion 60: ion implantation means
70 : 전원 80 : 플라즈마발생수단70: power source 80: plasma generating means
90 : 도선 90: lead wire
Claims (9)
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR1019980063672A KR100564420B1 (en) | 1998-12-31 | 1998-12-31 | Gate electrode ion implantation method |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR1019980063672A KR100564420B1 (en) | 1998-12-31 | 1998-12-31 | Gate electrode ion implantation method |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| KR20000046942A KR20000046942A (en) | 2000-07-25 |
| KR100564420B1 true KR100564420B1 (en) | 2006-07-06 |
Family
ID=19570234
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| KR1019980063672A KR100564420B1 (en) | 1998-12-31 | 1998-12-31 | Gate electrode ion implantation method |
Country Status (1)
| Country | Link |
|---|---|
| KR (1) | KR100564420B1 (en) |
Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR100699879B1 (en) * | 2005-11-22 | 2007-03-28 | 삼성전자주식회사 | Method of fabricating MOS transistor |
Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH07202186A (en) * | 1993-12-28 | 1995-08-04 | Sony Corp | Manufacture of semiconductor device |
| KR960039207A (en) * | 1995-04-04 | 1996-11-21 | 김주용 | Method for manufacturing gate electrode of semiconductor device |
| KR960042953A (en) * | 1995-05-17 | 1996-12-21 | 김주용 | Method of forming silicide layer in manufacturing semiconductor device |
| KR980012414A (en) * | 1996-07-29 | 1998-04-30 | 김광호 | Method for forming gate electrode of semiconductor device |
| KR19980085831A (en) * | 1997-05-30 | 1998-12-05 | 김영환 | Manufacturing Method of Semiconductor Device |
-
1998
- 1998-12-31 KR KR1019980063672A patent/KR100564420B1/en not_active IP Right Cessation
Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH07202186A (en) * | 1993-12-28 | 1995-08-04 | Sony Corp | Manufacture of semiconductor device |
| KR960039207A (en) * | 1995-04-04 | 1996-11-21 | 김주용 | Method for manufacturing gate electrode of semiconductor device |
| KR960042953A (en) * | 1995-05-17 | 1996-12-21 | 김주용 | Method of forming silicide layer in manufacturing semiconductor device |
| KR980012414A (en) * | 1996-07-29 | 1998-04-30 | 김광호 | Method for forming gate electrode of semiconductor device |
| KR19980085831A (en) * | 1997-05-30 | 1998-12-05 | 김영환 | Manufacturing Method of Semiconductor Device |
Also Published As
| Publication number | Publication date |
|---|---|
| KR20000046942A (en) | 2000-07-25 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US5567638A (en) | Method for suppressing boron penetration in PMOS with nitridized polysilicon gate | |
| KR20040037569A (en) | Transistor in a semiconductor device and a method of manufacturing the same | |
| JPH11284143A (en) | Method for forming trench condenser | |
| US20060205192A1 (en) | Shallow-junction fabrication in semiconductor devices via plasma implantation and deposition | |
| JPS61131557A (en) | Precision high value mos capacitor | |
| KR102579576B1 (en) | Contact integration for reduced interface and series contact resistance | |
| KR100844957B1 (en) | Method for fabricating semiconductor device | |
| US6365473B1 (en) | Method of manufacturing a transistor in a semiconductor device | |
| KR20070055569A (en) | Reduction of source and drain parasitic capacitance in cmos devices | |
| KR100564420B1 (en) | Gate electrode ion implantation method | |
| US6342423B1 (en) | MOS-type transistor processing utilizing UV-nitride removable spacer and HF etch | |
| KR100198652B1 (en) | Method of manufacturing electrode in semiconductor device | |
| KR100308133B1 (en) | Method for fablicating a MOS transistor having dual gate | |
| KR100277564B1 (en) | Semiconductor device and manufacturing method thereof | |
| KR20000046937A (en) | Method for forming gate electrode of transistor | |
| JP2000340790A (en) | Semiconductor device, manufacture thereof, and field- effect transistor | |
| KR20010065915A (en) | A method for forming dual-implanted polysilicon gate of semiconductor device | |
| KR100671663B1 (en) | Method of manufacturing a transistor in a semiconductor device | |
| KR100327570B1 (en) | Plug line manufacturing method of semiconductor device | |
| KR100271801B1 (en) | Manufacturing Method of Semiconductor Device | |
| KR100498607B1 (en) | Polysilicon layer formation method of semiconductor device | |
| KR930011113B1 (en) | Manufacturing method of contact plug for semiconductor device | |
| KR100443517B1 (en) | Method of manufacturing bit line of semiconductor device | |
| KR930011470B1 (en) | Manufacturing method of multiple ldd transistor using double insulating spacer | |
| KR940004267B1 (en) | Manufacturing method of mos fet |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| A201 | Request for examination | ||
| E902 | Notification of reason for refusal | ||
| E701 | Decision to grant or registration of patent right | ||
| GRNT | Written decision to grant | ||
| FPAY | Annual fee payment |
Payment date: 20110222 Year of fee payment: 6 |
|
| LAPS | Lapse due to unpaid annual fee |