KR100562653B1 - Semiconductor memory device - Google Patents

Abstract

The present invention provides a semiconductor memory device capable of stably performing line precharge to protect cell data. The present invention provides a memory core block including a memory cell array and a bit line sensing amplifier; Control means for receiving a read write strobe signal to generate a column control signal; A column driver configured to receive the column control signal and generate a column selection signal to apply to the memory core block; Margin securing means for further extending the width of the activation section of the column-control signal to a time that is twice the propagation delay of the column driver; And first and second line precharge signal generating means for generating first and second line precharge signals for precharging a global line of the memory core block in response to an output signal of the margin securing means. A memory device is provided.

Environment, Fluctuations, Propagation Delay, Margin, Collision

Description

Semiconductor Memory Device {SEMICONDUCTOR MEMORY DEVICE}             

1 is a view schematically illustrating a path for transferring data of a memory cell to a global line in general.

2 is a block diagram of a semiconductor memory device according to the prior art;

3 is an operation waveform diagram of FIG. 2 illustrating a case in which cell data is failed. FIG.

4 is a block diagram illustrating a semiconductor memory device in accordance with an embodiment of the present invention.

5 is an internal block diagram of the margin securing unit of FIG.

6 is an operational waveform diagram of FIG. 4.

* Explanation of symbols for the main parts of the drawings

300: margin securing unit

400, 500: line precharge signal generator

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to semiconductor design technology, and more particularly, to a semiconductor memory device which prevents line precharge and data from colliding, thereby preventing cell data from failing.

1 is a diagram schematically illustrating a path from which memory cell data of a semiconductor memory device is transferred to a global line.

Referring to FIG. 1, a general semiconductor memory device may respond to a unit memory cell 1, bit line pairs BL and / BL for receiving data of the unit memory cell 1, and an equalization signal bleq. Sensing and amplifying the data of the bit line equalization / precharge section 3 and the bit line pairs BL and / BL to precharge and equalize the bit line pairs BL and / BL with the precharge voltage VBLP. A bit line sense amplifier (2), a data bus pair (sio, / sio) connected to the bit line pair, a global line pair (lio, / lio) for transmission of data to be input / output, and a column selection signal ( a gate 4 for connecting the data bus pairs sio and / sio and the global line pairs lio and / lio in response to yi, and a global line pair lio, in response to the line precharge signal liopcg. line precharge unit 5 for precharging / lio).

Referring to a process of reading data of a memory cell, when the word line WL is activated, the data of the memory cell 1 connected thereto is applied to the bit line pairs BL and / BL as fine voltages. Subsequently, the data of the bit line pairs BL and / BL sensed and amplified by the bit line sense amplifier 2 are applied to the data bus pairs sio and / sio and are activated by the column select signal yi. It is transmitted to the global line pair (lio, / lio) through the gate (4).

As described above, the bit line pairs BL and / BL and the global line pairs lio and / lio are provided with precharge units 3 and 5 for precharging the respective angles. Since it is shared, the bit line pairs BL and / BL and the global line pairs lio and / lio are prepared as precharge voltages in advance to read data of other memory cells.

Meanwhile, a process of generating the line precharge signal and the column selection signal supplied to the semiconductor memory device will be described with reference to the following drawings.

2 is a block diagram of a semiconductor memory device according to the prior art.

Referring to FIG. 2, a semiconductor memory device according to the related art is provided with a memory core block 10 including a memory cell array and a bit line sense amplifier, and a read write strobe signal rdwtstbp0 to receive first and second columns. A controller 20 for generating the control signals cl_ctr1 and cl_ctr2, a column driver 80 for generating the column selection signal yi in response to the first column-control signal cl_ctr1, and a second column. Generating a first line precharge signal liopcg1 in response to an output signal of the first pulse width expansion unit 30 and the first pulse width expansion unit 30 for extending the pulse width of the control signal cl_ctr2. Extends the pulse width of the first line precharge signal generation unit 60, the delay unit 40 for delaying and outputting the first column-control signal cl_ctr1, and the output signal of the delay unit 40 A second line precharge in response to an output signal of the second pulse width expansion section 50 and the second pulse width expansion section 50 for And a second line precharge signal generation unit 70 for generating an arc (liopcg2).

Next, the operation of the semiconductor memory device will be described.

First, the controller 20 generates a first column-control signal cl_ctr1 in response to a read / write strobe signal rdwtstbp0 having a logic level 'L' in a read or write operation, and then, after a predetermined time, Generate a column-control signal (cl_ctr2). As such, the reason for activating the second column-control signal cl_ctr2 after a predetermined time is that the controller 50 is located at the lower end of the memory core block 10, and the first and the second signals are formed as output signals of the controller 50. Since the two line precharge signals liopcg1 and liopcg2 are applied to the upper and lower ends of the memory core block 10, respectively, the delay due to the path difference from the controller 50 to the upper and lower ends of the memory core block 10 is reduced. In consideration of this, the first and second line precharge signals liopcg1 and liopcg2 are simultaneously activated.

Next, the second pulse width expansion unit 70 extends the pulse width of the first column-control signal cl_ctr1 to include the activation region of the column selection signal yi. The first pulse width expansion unit 30 expands the pulse width of the second column control signal cl_ctr2.

Subsequently, the first and second line precharge signal generators 60 and 70 generate first and second precharge signals in response to output signals of the first and second pulse width extension units 30 and 50, respectively. liopcg1, liopcg2) are simultaneously deactivated.

Subsequently, since the column driver 80 activates the column selection signal yi in response to the activation of the first column-control signal cl_ctr1, the gate 18 is turned on so that the data of the data bus pairs sio and / sio are turned on. To be connected as a global line (lio, / lio) pair.

As such, when a read signal or a write signal is externally applied and the read / write strobe signal rdwtstbp0 is activated, the semiconductor memory device may generate the line precharge signals liopcg1 and liopcg2 before the column select signal yi is activated. It should be deactivated so that the data of the memory cell to be output or stored is not failed.

This is because the column select signal yi is activated when the word line WL is activated and the data of the memory cell is applied to the bit line pairs BL and / BL. This is because data of the memory cell is being transmitted to the global lines lio and / lio, and thus data collision occurs when the line precharge signals liopcg1 and liopcg2 are activated.

Therefore, the section in which the line precharge signals liopcg1 and liopcg2 have a logic level 'H' and should be deactivated should include a section where the column selection signal yi becomes a logic level 'H' and become active. Of course, in order to ensure data stably, the deactivation period of the line precharge signals liopcg1 and liopcg2 should include a margin before and after the activation period of the column selection signal yi.

3 is an operation waveform diagram of FIG. 2 and illustrates a phenomenon in which cell data is failed because a margin as described above is not secured.

Referring to FIG. 3, the margin t0 between the start time of the deactivation period of the first line precharge signal liopcg1 and the activation time of the column selection signal yi is sufficient, while the second line precharge signal liopcg2 is sufficient. ) Is deactivated immediately after the column selection signal yi is activated, and it can be seen that there is no margin t0 '.

This is a path for generating first and second line precharge signals liopcg1 and lipcg2 in anticipation of a delay due to a position difference between the memory core blocks 10 to which the first and second line precharge signals liopcg1 and liopcg2 are applied. Are designed differently, which is caused by the delay of each path due to factors such as the process of making a semiconductor memory device, the level of the driving voltage, the ambient temperature, etc., and thus not having the expected delay.

Therefore, the semiconductor memory device according to the present invention described above does not have sufficient margin between the line precharge signal and the column selection signal due to PVT (Process, Voltage, Temperature) fluctuations, so that cell data is failed and the reliability of the device is deteriorated. This happens.

The present invention has been proposed to solve the above problems of the prior art, and an object thereof is to provide a semiconductor memory device capable of stably performing line precharge to protect cell data.

According to one aspect of the present invention, a semiconductor memory device includes a memory core block including a memory cell array and a bit line sensing amplifier; Control means for receiving a read write strobe signal to generate a column control signal; A column driver configured to receive the column control signal and generate a column selection signal to apply to the memory core block; Margin securing means for further extending the width of the activation section of the column-control signal to a time that is twice the propagation delay of the column driver; And first and second line precharge signal generating means for generating first and second line precharge signals for precharging a global line of the memory core block in response to an output signal of the margin securing means.

DETAILED DESCRIPTION Hereinafter, exemplary embodiments of the present invention will be described with reference to the accompanying drawings so that those skilled in the art may easily implement the technical idea of the present invention. do.

4 is a block diagram illustrating a semiconductor memory device in accordance with an embodiment of the present invention.

Referring to FIG. 4, the semiconductor memory device generates a column-control signal cl_ctr by receiving a memory core block 100 including a memory cell array and a bit line sense amplifier and a read write strobe signal rdwtstbp0. The width of the activation period of the control unit 200, the column driver 600 for generating the column selection signal yi by receiving the column control signal cl_ctr, and the column driver The margin securing unit 300 and the first and second line precharge signals liopcg1 in response to an output signal of the margin securing unit 300 for further expanding for twice the propagation delay of the 600. and first and second line precharge signal generators 400 and 500 for generating liopcg2.

For reference, the read write strobe signal rdwtstbp0 is a signal having a logic level 'L' during a read or write operation. The read write strobe signal rdwtstbp0 indicates a signal indicating an operation state of a memory device through an edge of the signal.

5 is an internal block diagram of the margin securing unit 300 of FIG. 4, wherein the margin securing unit 300 delays and outputs the column control signal cl_ctr during the propagation delay time of the column driver 600. A first unit delay element 320 for delaying, and a second unit delay element 340 for delaying and outputting an output signal of the first unit delay element 320 for the propagation delay time of the column driver 600, and a column And a NAND gate AD1 for outputting a signal by taking the control signal cl_ctr and the output signals of the first and second unit delay elements 320 and 340 as inputs.

6 is an operation waveform diagram of FIG. 4, with reference to this, the operation of a semiconductor memory device according to an exemplary embodiment will be described. FIG.

First, the controller 200 activates the column control signal cl_ctr in response to the read write strobe signal rdwtstbp0.

Subsequently, the first unit delay element 320 delays and outputs the column control signal cl_ctr by the propagation delay t1 of the column driver 600, and the second unit delay element 340 outputs the first unit delay element. The output signal of 320 is delayed by the propagation delay t1 and output. Since the NAND gate AD1 receives the output signals of the first and second unit delay elements 320 and 340 and the column-control signal cl_ctr, any one of the input signals maintains the logic level 'L'. The logic level of the output signal is kept at 'H'. Accordingly, the margin securing unit 300 expands and outputs the pulse width of the column control signal cl_ctr by twice the propagation delay t1 of the column driver 600.

Subsequently, the first and second line precharge signal generators 400 and 500 deactivate the first and second line precharge signals liopcg1 and liopcg2 in response to the output signal of the margin securing unit 300 to free the line. Terminate the charge.

Then, the column driver 600 activates the column selection signal yi in response to the column-control signal cl_ctr.

As shown in the figure, the deactivation periods of the first and second line precharge signals liopcg1 and liopcg2 include an activation period of the column selection signal yi, and before and after the column selection signal yi. It can be seen that the margin as much as t1).

Therefore, the line precharge is terminated before the data of the memory cell is applied to the global line pairs (lio and / lio), so that the line precharge and the data do not collide with each other.

Therefore, the above-described semiconductor memory device according to the present invention has a path for generating a line precharge signal and has a common margin from the application of a read write strobe signal to a margin securer for securing a margin with the column selection signal. Therefore, the activation area of the first and second line precharge signals may be distorted due to the PVT fluctuation, or the cell data may be prevented from being overlapped with the activation area of the column selection signal.

In addition, the first and second line precharge signals deactivate the line precharge signal in response to the column control signal generating the column selection signal, which is doubled for a delay time until the column selection signal is activated. Since the column selection signal is activated, line precharge is not performed while the data of the bit line pair is applied to the data bus pair, so that the data of the bit line pair does not collide with the line precharge and the cell data is protected. .

In addition, since the semiconductor memory device according to the present invention does not need a pulse width expansion unit for extending the pulse width, the area is reduced and power consumption is reduced because the current consumed by the pulse width expansion unit can be reduced.

The present invention described above is not limited to the above-described embodiments and the accompanying drawings, and various substitutions, modifications, and changes are possible in the art without departing from the technical spirit of the present invention. It will be clear to those of ordinary knowledge.

The present invention described above includes a path for generating the first and second line precharge signals in common, and the first and second line precharge signals are doubled for a delay time until the column selection signal is activated. By maintaining the deactivation interval of, cell data is prevented from failing.

Claims (4)

A memory core block having a memory cell array and a bit line sense amplifier; Control means for receiving a read write strobe signal to generate a column control signal; A column driver configured to receive the column control signal and generate a column selection signal to apply to the memory core block; Margin securing means for further extending the width of the activation section of the column-control signal to a time that is twice the propagation delay of the column driver; And First and second line precharge signal generating means for generating first and second line precharge signals for precharging a global line of the memory core block in response to an output signal of the margin securing means; A semiconductor memory device having a. The method of claim 1, The read / write strobe signal is a signal having a logic level 'L' during a read or write operation, and indicates an operation state of a memory device through an edge of the signal. The method according to claim 1 or 2, The margin securing means A first unit delay element for delaying and outputting the column control signal for the propagation delay time; A second unit delay element for delaying and outputting an output signal of the first unit delay element for the propagation delay time; NAND gate for outputting the signal by taking the column-control signal and the output signals of the first and second unit delay elements as inputs A semiconductor memory device comprising: a. The method of claim 3, The memory core block, A memory cell array block, A bit line pair for receiving data of the memory cell array block; A bit line sense amplifier array block for sensing and amplifying data of the bit line pair; A data bus pair connected to the bit line pair, A global line pair for transmission of data to be output or input, A gate for connecting the data bus pair and the global line pair in response to the column selection signal; A line precharge unit for precharging the global line pair in response to the first and second line precharge signals Semiconductor memory device comprising a.

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