KR100543636B1 - Flash memory device manufacturing method - Google Patents
Flash memory device manufacturing method Download PDFInfo
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- KR100543636B1 KR100543636B1 KR1019980059333A KR19980059333A KR100543636B1 KR 100543636 B1 KR100543636 B1 KR 100543636B1 KR 1019980059333 A KR1019980059333 A KR 1019980059333A KR 19980059333 A KR19980059333 A KR 19980059333A KR 100543636 B1 KR100543636 B1 KR 100543636B1
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- 238000004519 manufacturing process Methods 0.000 title abstract description 9
- 238000000034 method Methods 0.000 claims abstract description 39
- 238000005468 ion implantation Methods 0.000 claims abstract description 22
- 238000010438 heat treatment Methods 0.000 claims abstract description 10
- 239000004065 semiconductor Substances 0.000 claims abstract description 5
- 125000006850 spacer group Chemical group 0.000 claims abstract description 5
- 239000000758 substrate Substances 0.000 claims abstract description 5
- 238000005530 etching Methods 0.000 claims abstract description 3
- 150000002500 ions Chemical class 0.000 claims description 16
- 239000005380 borophosphosilicate glass Substances 0.000 claims description 12
- 229910052814 silicon oxide Inorganic materials 0.000 claims description 5
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 4
- 238000001505 atmospheric-pressure chemical vapour deposition Methods 0.000 claims description 3
- 229910052710 silicon Inorganic materials 0.000 claims description 3
- 239000010703 silicon Substances 0.000 claims description 3
- 238000000137 annealing Methods 0.000 claims description 2
- 238000004518 low pressure chemical vapour deposition Methods 0.000 claims description 2
- 239000000463 material Substances 0.000 claims 1
- 238000000623 plasma-assisted chemical vapour deposition Methods 0.000 claims 1
- 238000007517 polishing process Methods 0.000 claims 1
- 239000000126 substance Substances 0.000 claims 1
- 230000014759 maintenance of location Effects 0.000 abstract description 6
- 230000000694 effects Effects 0.000 description 7
- 229910052698 phosphorus Inorganic materials 0.000 description 6
- 239000011574 phosphorus Substances 0.000 description 6
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 6
- 229920005591 polysilicon Polymers 0.000 description 6
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 description 5
- 238000005247 gettering Methods 0.000 description 5
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 2
- 238000004140 cleaning Methods 0.000 description 2
- 230000007547 defect Effects 0.000 description 2
- 238000000151 deposition Methods 0.000 description 2
- 238000010586 diagram Methods 0.000 description 2
- 229910052739 hydrogen Inorganic materials 0.000 description 2
- 239000001257 hydrogen Substances 0.000 description 2
- 125000004435 hydrogen atom Chemical class [H]* 0.000 description 2
- 238000006467 substitution reaction Methods 0.000 description 2
- WQJQOUPTWCFRMM-UHFFFAOYSA-N tungsten disilicide Chemical compound [Si]#[W]#[Si] WQJQOUPTWCFRMM-UHFFFAOYSA-N 0.000 description 2
- 229910021342 tungsten silicide Inorganic materials 0.000 description 2
- 229910004298 SiO 2 Inorganic materials 0.000 description 1
- 229910004283 SiO 4 Inorganic materials 0.000 description 1
- 230000004888 barrier function Effects 0.000 description 1
- 229910001423 beryllium ion Inorganic materials 0.000 description 1
- 229910000149 boron phosphate Inorganic materials 0.000 description 1
- 230000005465 channeling Effects 0.000 description 1
- 239000013078 crystal Substances 0.000 description 1
- 230000008021 deposition Effects 0.000 description 1
- 229910052732 germanium Inorganic materials 0.000 description 1
- GNPVGFCGXDBREM-UHFFFAOYSA-N germanium atom Chemical compound [Ge] GNPVGFCGXDBREM-UHFFFAOYSA-N 0.000 description 1
- 238000002513 implantation Methods 0.000 description 1
- 239000012535 impurity Substances 0.000 description 1
- 230000000149 penetrating effect Effects 0.000 description 1
- -1 phosphorus ions Chemical class 0.000 description 1
- XLYOFNOQVPJJNP-UHFFFAOYSA-N water Substances O XLYOFNOQVPJJNP-UHFFFAOYSA-N 0.000 description 1
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- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76822—Modification of the material of dielectric layers, e.g. grading, after-treatment to improve the stability of the layers, to increase their density etc.
- H01L21/76825—Modification of the material of dielectric layers, e.g. grading, after-treatment to improve the stability of the layers, to increase their density etc. by exposing the layer to particle radiation, e.g. ion implantation, irradiation with UV light or electrons etc.
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/26—Bombardment with radiation
- H01L21/263—Bombardment with radiation with high-energy radiation
- H01L21/265—Bombardment with radiation with high-energy radiation producing ion implantation
- H01L21/26586—Bombardment with radiation with high-energy radiation producing ion implantation characterised by the angle between the ion beam and the crystal planes or the main crystal surface
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76819—Smoothing of the dielectric
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- H—ELECTRICITY
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76822—Modification of the material of dielectric layers, e.g. grading, after-treatment to improve the stability of the layers, to increase their density etc.
- H01L21/76828—Modification of the material of dielectric layers, e.g. grading, after-treatment to improve the stability of the layers, to increase their density etc. thermal treatment
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- H10B—ELECTRONIC MEMORY DEVICES
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Abstract
본 발명은 플래쉬 메모리 장치 제조 방법에 관한 것으로, 플래쉬 메모리 셀이 형성된 반도체 기판이 제공되는 단계와, 전체 구조 상부에 산화막을 형성하고 식각하여 상기 플래쉬 메모리 셀 측벽에 스페이서 산화막을 형성하는 단계와, 전체 구조 상부에 열산화막을 형성하는 단계와, 전체 구조 상부에 평탄화 절연막을 형성하는 단계와, 상기 평탄화 절연막에 이온 주입 공정을 실시한 후 열처리 공정을 실시하는 단계를 통하여, 소자의 데이터 리텐션 특성 및 스루우풋을 향상시킬 수 있는 플래쉬 메모리 장치 제조 방법이 개시된다.The present invention relates to a method of manufacturing a flash memory device, comprising: providing a semiconductor substrate on which a flash memory cell is formed; forming an oxide film on an entire structure and etching the same to form a spacer oxide film on sidewalls of the flash memory cell; Forming a thermal oxide film over the structure, forming a planarization insulating film over the entire structure, performing an ion implantation process on the planarization insulating film, and then performing a heat treatment process, thereby performing data retention characteristics and through Disclosed is a method of manufacturing a flash memory device that can improve the throughput.
Description
본 발명은 플래쉬 메모리 장치 제조 방법에 관한 것으로, 특히 이온 주입 공정과 열공정을 이용하여 데이터 리텐션 특성을 향상시킬 수 있는 플래쉬 메모리 장치 제조 방법에 관한 것이다.The present invention relates to a method of manufacturing a flash memory device, and more particularly, to a method of manufacturing a flash memory device that can improve data retention characteristics by using an ion implantation process and a thermal process.
플래쉬 메모리 장치에서 플로팅 게이트에서 저장되어 있는 차지의 손실은 데이터 리텐션 특성을 저하시키는데, 이것은 후속 공정시 발생되는 이동 차지(mobile charge)가 스페이서 산화막 및 폴리시리콘간 산화막을 통하여 플로팅 게이트로 출입하는 것에 기인한다. 또한, 저온 공정으로 형성되는 평탄화 절연막(예를 들어, SOG막)에는 수소가 함유되어 있는데, 이는 이러한 막들의 웨이퍼 리텐션 능력을 저하시킨다. 이 수소는 이동 이온으로 작용하며, 이에 의한 영향은 소자에 치명적이다.The loss of charge stored in the floating gate in the flash memory device degrades the data retention characteristics, which is due to the mobile charge generated during the subsequent process entering and exiting the floating gate through the spacer oxide and the inter-silicon oxide. Is caused. In addition, the planarization insulating film (for example, an SOG film) formed by the low temperature process contains hydrogen, which lowers the wafer retention capability of these films. This hydrogen acts as a mobile ion, and its effect is fatal to the device.
BPSG막 내의 인(P)은 게터링(Gettering) 효과가 우수하여, 이동 이온을 포획하므로써 이동 이온이 플로팅 게이트로 침투되는 것을 막는 역할을 한다. 이러한 특성을 이용하여 PSG막을 베리어막으로 사용하여 이동 차지로 인한 문제를 해결하고 있으나, 후속 클리닝 공정에서 PSG막과 BPSG막의 식각율 차이에 의해 PSG막에 언더컷 현상이 발생하는 문제점이 있다. 또한, PSG막은 흡습성이 강하므로 PSG막을 증착한 후 약간의 지연 시간이 있다면, 막 표면에 H3PO4가 생성되어 후속 공정시 결함이 발생하는 원인으로 작용한다. 그리고, 데이터 리텐션 특성을 향상시키기 위해 BPSG막에서 단순히 인 농도만을 높이고자 한다면 막 자체가 연화되어 불안정할 뿐만 아니라, 막 표면에 해이즈(haze) 현상이 발생하고 BPO4라는 크리스탈 결함이 발생하여 후속공정 진행시 소자에 치명적인 영향을 준다.Phosphorus (P) in the BPSG film is excellent in the gettering effect, and captures the mobile ions, thereby preventing the mobile ions from penetrating into the floating gate. The PSG layer is used as a barrier layer to solve the problem due to the moving charge, but there is a problem that the undercut phenomenon occurs in the PSG layer due to the difference in the etching rate between the PSG layer and the BPSG layer in the subsequent cleaning process. In addition, since the PSG film has a strong hygroscopicity, if there is a slight delay time after the deposition of the PSG film, H 3 PO 4 is generated on the surface of the film to act as a cause of defects in subsequent processes. In addition, if the phosphorus concentration is simply increased in the BPSG film to improve the data retention characteristics, the film itself is softened and unstable, and a haze phenomenon occurs on the surface of the film and a crystal defect called BPO4 occurs. The process has a fatal effect on the device.
따라서, 본 발명은 BPSG막에 인 이온을 주입하여 이동 전하에 대한 게터링 효과를 높이고, 이온 주입시 BPSG막 내의 격자의 깨짐을 이용하여 후속 열공정으로 BPSG막 내에 존재하는 수분을 제거하여 데이터 리텐션 특성을 향상시킬 수 있는 플래쉬 메모리 장치 제조 방법을 제공하는 데 그 목적이 있다.Therefore, the present invention enhances the gettering effect on the mobile charge by injecting phosphorus ions into the BPSG film, and removes the moisture present in the BPSG film by subsequent thermal process by using the crack of the lattice in the BPSG film during ion implantation. It is an object of the present invention to provide a method of manufacturing a flash memory device capable of improving tension characteristics.
상술한 목적을 달성하기 위한 본 발명에 따른 플래쉬 메모리 장치 제조 방법은 플래쉬 메모리 셀이 형성된 반도체 기판이 제공되는 단계와, 전체 구조 상부에 산화막을 형성하고 식각하여 상기 플래쉬 메모리 셀 측벽에 스페이서 산화막을 형성하는 단계와, 전체 구조 상부에 열산화막을 형성하는 단계와, 전체 구조 상부에 평탄화 절연막을 형성하는 단계와, 상기 평탄화 절연막에 이온 주입 공정을 실시한 후 열처리 공정을 실시하는 단계를 포함하여 이루어지는 것을 특징으로 한다.In accordance with an aspect of the present invention, there is provided a method of manufacturing a flash memory device, the method including: providing a semiconductor substrate on which a flash memory cell is formed; And forming a thermal oxide film over the entire structure, forming a planarization insulating film over the entire structure, and performing a heat treatment process after performing an ion implantation process on the planarization insulating film. It is done.
도 1(a) 내지 1(b)는 본 발명에 따른 플래쉬 메모리 장치 제조 방법을 설명하기 위해 도시한 소자의 단면도이고, 도 2는 본 발명에 적용되는 평탄화 절연막의 격자구조도이다.1 (a) to 1 (b) are cross-sectional views of the device shown to explain a method of manufacturing a flash memory device according to the present invention, and FIG. 2 is a lattice structure diagram of a planarization insulating film applied to the present invention.
도 1(a)에 도시된 바와 같이, 반도체 기판(11) 상에 터널 산화막(12), 플로팅 게이트용 제 1 폴리실리콘막(13), ONO 구조의 유전체막(14), 콘트롤 게이트용 제 2 폴리실리콘막(15), 탑 폴리실리콘막(16), 텅스텐 실리사이드막(17) 및 반사 방지막(18)을 순차적으로 형성하고 패터닝하여 스택 게이트형의 플래쉬 메모리 셀을 형성한다. 다음에, 전체구조 상부에 산화막을 형성한 다음 식각하여, 플래쉬 메모리 셀 측벽에 스페이서 산화막(19)을 형성하고, 전체 구조 상부에 열산화막(20)을 형성한 다음 평탄화 절연막(21)을 두껍게 형성한다. 다음에, 열공정을 통해 평탄화 절연막(21)을 플로우시켜 평탄화한다. 평탄화 절연막으로는 대표적으로 BPSG막을 이용하며, 이 이에도 실리콘 산화막을 LPCVD, APCVD, RECVD 방법으로 증착하여 사용할 수도 있다. 또한, 평탄화 절연막(21)은 3000Å 이상의 두께로 증착한다.As shown in Fig. 1 (a), the tunnel oxide film 12, the first polysilicon film 13 for the floating gate, the dielectric film 14 of the ONO structure, and the second control gate are formed on the semiconductor substrate 11. The polysilicon film 15, the top polysilicon film 16, the tungsten silicide film 17, and the antireflection film 18 are sequentially formed and patterned to form a stack gate type flash memory cell. Next, an oxide film is formed on the entire structure and then etched to form a spacer oxide film 19 on the side surface of the flash memory cell, a thermal oxide film 20 is formed on the entire structure, and then a planarization insulating film 21 is formed thick. do. Next, the planarization insulating film 21 is flowed through the thermal process and planarized. Typically, a BPSG film is used as the planarization insulating film, and a silicon oxide film may also be deposited and used by LPCVD, APCVD, and RECVD methods. Further, the planarization insulating film 21 is deposited to a thickness of 3000 GPa or more.
도 1(b)에 도시된 바와 같이, 평탄화 절연막(21)에 이온 주입 공정을 실시한다. 이때 사용되는 이온은 인(P), 아세나이드(As) 등의 5가 원소를 사용하며, 이 5가 원소가 이동 이온과의 공유결합을 유도하여 이동 이온에 대한 게터링 효과를 유발한다. 또한, 게르마늄(Ge), 실리콘(Si), 아세나이드(As) 등과 같은 질량이 큰 원소를 이용하는 경우에는 평탄화 절연막 내의 격자손상을 유도하여 외인성(extrinsic) 게터링 효과를 얻을 수 있다. 또한, 이온 주입량은 5.0E15 ions/㎠ 이상으로 하고, 평탄화 절연막(21) 두께의 1/2 정도 깊이까지 주입한다. 이온주입 에너지는 메모리 셀이나 접합영역에 영향을 주지 않는 범위 즉, 주입 불순물 농도의 RP(Projected Range)점이 평탄화 절연막 두께의 1/2이 되는 곳에 위치하도록 주입 에너지를 설정한다. 실험 데이터에 의하면 BPSG막의 두께가 9000 내지 10000Å인 경우 주입 이온의 RP점을 BPSG막 두께의 1/2 정도에 위치시키기 위한 이온 주입 에너지는 220 내지 260KeV이다. 그리고 이온 주입되는 평탄화 절연막(21)의 차지-업(charge-up) 현상을 억제하기 위하여 이온 주입시 일렉트론-샤워를 이용하며, 이온 주입 각도는 7°이상으로 하여 채널링을 방지한다.As shown in FIG. 1B, an ion implantation process is performed on the planarization insulating film 21. At this time, the ions used are pentavalent elements such as phosphorus (P) and arsenide (As), and the pentavalent elements induce covalent bonds with the mobile ions, causing a gettering effect on the mobile ions. In addition, when a large mass element such as germanium (Ge), silicon (Si), arsenide (As), or the like is used, lattice damage in the planarization insulating layer may be induced to obtain an extrinsic gettering effect. In addition, the ion implantation amount is 5.0E15 ions / cm 2 or more, and is implanted to a depth of about 1/2 the thickness of the planarization insulating film 21. Ion implantation energy is set to the memory implantation energy range that does not affect the cell or junction region that is, injecting the impurity concentration of the P R (Projected Range) points to the location where that half of the planarization insulating film thickness. According to the experimental data, when the thickness of the BPSG film is 9000 to 10000 Pa, the ion implantation energy for positioning the R P point of the implanted ion at about 1/2 of the thickness of the BPSG film is 220 to 260 KeV. In order to suppress the charge-up phenomenon of the planarization insulating layer 21 to be ion implanted, an electron-shower is used during ion implantation, and the ion implantation angle is 7 ° or more to prevent channeling.
이후, 열처리를 실시하여 이온주입시 깨진 격자를 보상하고, 주입된 이온(인, 아세나이드 등)과 BPSG막 내 SiO4, SiO2의 실리콘과의 치환결합을 유도한다. 열처리는 850 내지 1000℃ 범위에서 RTA, 퍼니스 어닐링, 익사이머 래이저 중 어느 하나를 이용하여 실시한다.Subsequently, heat treatment is performed to compensate for the broken lattice during ion implantation, and induce substitution substitution of the implanted ions (phosphorus, arsenide, etc.) with silicon of SiO 4 and SiO 2 in the BPSG film. Heat treatment is carried out using any one of RTA, furnace annealing, excimer laser in the range of 850 to 1000 ℃.
열처리 공정 후 이온 주입된 평탄화 절연막(21)의 격자구조는 도 2에 나타난다. 열처리 공정으로 인해, 막 내에 존재하여 후에 이동 차지로 될 수 있는 수분기(H+)가 증발되어 제거된다. 그리고 이온 주입에 의해 거칠어진 평탄화 절연막 표면은CMP 공정을 실시하여 평탄화한다.The lattice structure of the planarization insulating film 21 implanted with ion after the heat treatment process is shown in FIG. 2. Due to the heat treatment process, the water branch (H + ) which is present in the film and can later become a moving charge is evaporated and removed. The planarization insulating film surface roughened by ion implantation is planarized by performing a CMP process.
이와 같이 하면, 평탄화 절연막 내에 이온이 균일하게 분포되어 단일 PSG막에 BPSG막을 증착할 경우 후속 클리닝 공정시 나타나는 PSG막의 언더 컷 현상을 방지할 수 있고 PSG막의 흡습성으로 인한 H3PO4의 생성을 억제할 수 있다. 또한, 단일 PSG막을 증착하는 경우 APCVD 장비의 특성상 막의 균일성을 좋게 하기 위해 2PASS로 공정을 진행하므로 스루우풋이 저하되는데 비해, 이온 주입 공정을 실시하게 되면 스루우풋이 향상되어 공정 진행시 시간 손실을 줄일 수 있다. 그리고 이미 플로우 공정을 거친 평탄화 절연막에 이온을 주입하고 열처리 공정을 거쳐 리커버링하기 때문에 막 표면의 해이즈나 막의 연화를 방지할 수 있다.In this way, when the BPSG film is deposited on the single PSG film by uniformly distributing ions in the planarization insulating film, the undercut phenomenon of the PSG film during the subsequent cleaning process can be prevented and the generation of H 3 PO 4 due to the hygroscopicity of the PSG film is suppressed. can do. In addition, when depositing a single PSG film, the throughput is reduced to 2PASS to improve the film uniformity due to the characteristics of APCVD equipment. However, the throughput is reduced, whereas the throughput is improved by performing the ion implantation process. Can be reduced. In addition, since ion is implanted into the planarization insulating film which has already been flowed and recovered through a heat treatment process, haze on the surface of the film and softening of the film can be prevented.
상술한 바와 같이, 본 발명에 따르면 평탄화 절연막에 인이 함유된 이온을 주입하고 열처리하므로써 이동 이온에 대한 게터링 효과를 높이고, 이온 주입시 평탄화 절연막 내의 격자 깨짐을 이용하여 후속 열처리 공정시 막 내에 존재하는 수분기를 효과적으로 제거하여 소자의 데이터 리텐션 특성을 개선하 수 있으므로, 소자의 수율 및 스루우풋이 증대되는 효과가 있다.As described above, according to the present invention, the gettering effect on the mobile ions is increased by injecting and heat-treating phosphorus-containing ions into the planarization insulating film, and present in the film during the subsequent heat treatment process by using lattice cracks in the planarization insulating film during ion implantation. Since the water retention can be effectively removed to improve the data retention characteristics of the device, the yield and throughput of the device can be increased.
도 1(a) 내지 1(b)는 본 발명에 따른 플래쉬 메모리 장치 제조 방법을 설명하기 위해 도시한 소자의 단면도.1 (a) to 1 (b) are cross-sectional views of devices for explaining the method of manufacturing a flash memory device according to the present invention.
도 2는 본 발명에 적용되는 평탄화 절연막의 격자구조도.2 is a lattice diagram of a planarization insulating film applied to the present invention.
<도면의 주요 부분에 대한 부호 설명><Description of the symbols for the main parts of the drawings>
11 : 반도체 기판 12 : 터널 산화막11 semiconductor substrate 12 tunnel oxide film
13 : 제 1 폴리실리콘막(플로팅 게이트) 14 : ONO막13: 1st polysilicon film (floating gate) 14: ONO film
15 : 제 2 폴리실리콘막(콘트롤 게이트) 16 : 탑 폴리실리콘막15: second polysilicon film (control gate) 16: top polysilicon film
17 : 텅스텐 실리사이드막 18 : 반사방지막17 tungsten silicide film 18 antireflection film
19 : 스페이서 산화막 20 : 열산화막19: spacer oxide film 20: thermal oxide film
21 : 평탄화 절연막21: planarization insulating film
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| KR880010502A (en) * | 1987-02-27 | 1988-10-10 | 아오이 죠이치 | UV-erasing nonvolatile semiconductor memory device and manufacturing method |
| JPH0677493A (en) * | 1992-08-27 | 1994-03-18 | Mitsubishi Electric Corp | Semiconductor device and its manufacture |
| US5397724A (en) * | 1992-06-09 | 1995-03-14 | Sony Corporation | Method of making a nonvolatile memory device having a sidewall insulating film doped with phosphorus |
| JPH07321236A (en) * | 1994-05-25 | 1995-12-08 | Nec Corp | Nonvolatile memory device and its manufacture |
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| KR880010502A (en) * | 1987-02-27 | 1988-10-10 | 아오이 죠이치 | UV-erasing nonvolatile semiconductor memory device and manufacturing method |
| US5397724A (en) * | 1992-06-09 | 1995-03-14 | Sony Corporation | Method of making a nonvolatile memory device having a sidewall insulating film doped with phosphorus |
| JPH0677493A (en) * | 1992-08-27 | 1994-03-18 | Mitsubishi Electric Corp | Semiconductor device and its manufacture |
| JPH07321236A (en) * | 1994-05-25 | 1995-12-08 | Nec Corp | Nonvolatile memory device and its manufacture |
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