KR100247481B1 - A method for forming metal contact in semiconductor device - Google Patents

A method for forming metal contact in semiconductor device Download PDF

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KR100247481B1
KR100247481B1 KR1019960057773A KR19960057773A KR100247481B1 KR 100247481 B1 KR100247481 B1 KR 100247481B1 KR 1019960057773 A KR1019960057773 A KR 1019960057773A KR 19960057773 A KR19960057773 A KR 19960057773A KR 100247481 B1 KR100247481 B1 KR 100247481B1
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semiconductor device
forming
contact hole
metal contact
contact
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KR1019960057773A
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KR19980038844A (en
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홍상기
오세준
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김영환
현대전자산업주식회사
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76822—Modification of the material of dielectric layers, e.g. grading, after-treatment to improve the stability of the layers, to increase their density etc.
    • H01L21/76825—Modification of the material of dielectric layers, e.g. grading, after-treatment to improve the stability of the layers, to increase their density etc. by exposing the layer to particle radiation, e.g. ion implantation, irradiation with UV light or electrons etc.

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Plasma & Fusion (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)

Abstract

본 발명은 반도체 제조 기술에 관한 것으로, 특히 반도체 소자의 금속 콘택 공정에 관한 것이며, 금속막 증착전 세정 공정시 층간절연막의 일부가 콘택홀 내부로 돌출하여 턱이지는 현상을 방지하는 반도체 소자의 금속 콘택 형성방법을 제공하는데 그 목적이 있다. 본 발명은 콘택홀 내벽을 구성하는 층간절연 산화막간의 세정 용액에 대한 식각 속도 차이를 둔화시키기 위하여 콘택홀 측벽에 붕소계 불순물(B 또는 BF2)을 이온주입한다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor manufacturing technology, and more particularly, to a metal contact process of a semiconductor device, wherein a part of an interlayer insulating film protrudes into a contact hole during a cleaning process before deposition of a metal film. It is an object of the present invention to provide a method for forming a contact. In the present invention, boron-based impurities (B or BF 2 ) are ion-implanted into the contact hole sidewalls to slow the difference in etching rates of the cleaning solution between the interlayer insulating oxide films constituting the inner wall of the contact hole.

Description

반도체 소자의 금속 콘택 형성방법{A method for forming metal contact in semiconductor device}A method for forming metal contact in semiconductor device

본 발명은 반도체 제조 기술에 관한 것으로, 특히 반도체 소자의 금속 콘택 공정에 관한 것이다.TECHNICAL FIELD The present invention relates to semiconductor manufacturing technology, and more particularly, to a metal contact process of a semiconductor device.

일반적으로, 반도체 소자의 금속 콘택을 형성하기 위하여 스퍼터링(sputtering) 방식의 알루미늄막을 사용하여 왔다.Generally, sputtering aluminum films have been used to form metal contacts of semiconductor devices.

그러나, 반도체 소자의 고집적화에 따라 금속 콘택홀의 크기가 점점 감소하게 되고 종래의 일반적인 방법으로는 알루미늄 콘택의 단차 피복성을 확보하기가 힘들게 되었고, 이에 대한 대안으로 고온에서 알루미늄을 증착하거나, 플로우(flow) 시켜 콘택홀을 매립하는 방법으로 금속 콘택을 형성하고 있다.However, due to the high integration of semiconductor devices, the size of metal contact holes is gradually reduced, and it is difficult to secure step coverage of aluminum contacts using conventional methods. Alternatively, aluminum is deposited or flowed at a high temperature. Metal contacts are formed by filling the contact holes.

이하, 첨부된 도면 도 1a 내지 도 1c를 참조하여 종래의 금속 콘택 공정을 살펴본다.Hereinafter, a conventional metal contact process will be described with reference to the accompanying drawings, FIGS. 1A to 1C.

먼저, 도 1a는 실리콘 기판(10) 상에 층간절연막인 BPSG(BoroPhosphor Silicate Glass)막(11a), IPO(InterPoly Oxide)(12), BPSG막(11b)이 차례로 적층된 구조에서 콘택홀이 형성된 상태를 나타낸 것이다. 이때, IPO(12)는 다른 단면에서 본다면 게이트 전극과 전하저장 전극간의 절연을 위해 형성된 층이다.First, FIG. 1A illustrates that a contact hole is formed in a structure in which a BPSG (BoroPhosphor Silicate Glass) film 11a, an interpoly oxide (IPO) 12, and a BPSG film 11b are sequentially stacked on a silicon substrate 10. FIG. It shows the state. At this time, the IPO 12 is a layer formed for insulation between the gate electrode and the charge storage electrode, as seen from another cross section.

다음으로, 도 1b에 도시된 바와 같이 콘택홀 식각후 외기에 노출되어 형성된 자연 산화막(도시되지 않음)을 제거하기 위하여 세정 공정을 수행한다. 이때 사용되는 세정 용액은 100 : 1 BOE(Buffered Oxide Etchant)인데, 서로 다른 산화막간의 식각 속도의 차이로 인하여 IPO(12)의 일부가 콘택홀 내부로 돌출하게 된다. 즉, 도핑되지 않은 산화막인 IPO(12)에 비하여 B와 P가 도핑된 BPSG막(11a, 11b)의 식각 속도가 빠르기 때문에 상대적으로 식각 속도가 느린 IPO(12)가 돌출하게 되는 것이다.Next, as illustrated in FIG. 1B, a cleaning process is performed to remove a natural oxide film (not shown) formed after being exposed to the outside air after etching the contact hole. In this case, the cleaning solution used is 100: 1 BOE (Buffered Oxide Etchant), and part of the IPO 12 protrudes into the contact hole due to the difference in etching rates between different oxide layers. That is, since the etching speed of the BPSG films 11a and 11b doped with B and P is faster than the IPO 12 which is the undoped oxide film, the relatively slow etching speed of the IPO 12 protrudes.

이어서, 도 1c에 도시된 바와 같이 알루미늄막(13)을 매립한다. 이때, 돌출된 IPO(12)에 의하여 콘택홀 내에 턱이 짐으로써 보이드(14)를 유발한다. 즉, 알루미늄막(13)이 콘택홀 벽을 따라 흘러내리다가 돌출된 부위에서 그 흐름이 중단되어 보이드(14)를 유발하게 되는 것이다. 이러한 보이드(14)는 단선 등의 문제를 유발하게 되어 반도체 소자의 신뢰도 저하시키는 요인이 된다.Subsequently, the aluminum film 13 is embedded as shown in FIG. 1C. At this time, the jaw 14 is caused by being tucked into the contact hole by the protruding IPO 12. That is, the aluminum film 13 flows down along the contact hole wall, and the flow is stopped at the protruding portion to cause the voids 14. Such voids 14 cause problems such as disconnection, which causes deterioration of reliability of the semiconductor device.

본 발명은 금속막 증착전 세정 공정시 층간절연막의 일부가 콘택홀 내부로 돌출하여 턱이지는 현상을 방지하는 금속 콘택 형성방법을 제공하는데 그 목적이 있다.An object of the present invention is to provide a method for forming a metal contact to prevent a part of the interlayer insulating film protrudes into the contact hole during the cleaning process before the deposition of the metal film.

도 1a 내지 도 1c는 종래기술에 따른 반도체 소자의 금속 콘택 공정도,1a to 1c is a metal contact process diagram of a semiconductor device according to the prior art,

도 2a 내지 도 2c는 본 발명의 일 실시예에 따른 반도체 소자의 금속 콘택 공정도.2A to 2C are metal contact process diagrams of a semiconductor device according to an embodiment of the present invention.

* 도면의 주요 부분에 대한 부호의 설명* Explanation of symbols for the main parts of the drawings

10, 20 : 실리콘 기판 11a, 11b, 21a, 21b : BPSG막10, 20: silicon substrate 11a, 11b, 21a, 21b: BPSG film

12, 22 : IPO 13, 23 : 알루미늄막12, 22: IPO 13, 23: aluminum film

14 : 보이드(Void)14: void

상기와 같은 목적을 달성하기 위하여 본 발명은, 소정의 하부층 상에 형성된 다층 구조의 층간절연 산화막을 선택 식각하여 콘택홀을 형성하는 제1 단계; 세정 용액에 대한 상기 층간절연 산화막의 식각 속도를 낮추기 위하여 상기 콘택홀 내벽에 붕소계 불순물을 이온주입하는 제2 단계; 상기 제2 단계 수행후, 자연산화막 제거를 위한 세정을 실시하는 제3 단계; 및 상기 제3 단계를 마친 전체구조 상부에 금속막을 형성하여 상기 콘택홀을 매립하는 제4 단계를 포함하여 이루어진다.In order to achieve the above object, the present invention includes a first step of forming a contact hole by selectively etching an interlayer insulating oxide film of a multi-layer structure formed on a predetermined lower layer; A second step of ion implanting a boron-based impurity into an inner wall of the contact hole to lower an etching rate of the interlayer insulating oxide film with respect to a cleaning solution; A third step of performing cleaning to remove the native oxide film after performing the second step; And a fourth step of filling the contact hole by forming a metal film on the entire structure having completed the third step.

즉, 본 발명은 콘택홀 내벽을 구성하는 층간절연 산화막간의 세정 용액에 대한 식각 속도 차이를 둔화시키기 위하여 콘택홀 측벽에 붕소계 불순물(B 또는 BF2)을 이온주입한다.That is, in the present invention, boron-based impurities (B or BF 2 ) are ion-implanted into the sidewalls of the contact holes in order to slow the difference in etching rates for the cleaning solution between the interlayer insulating oxide films constituting the inner wall of the contact holes.

이하, 본 발명이 속한 기술분야에서 통상의 지식을 가진 자가 본 발명을 보다 용이하게 실시할 수 있도록 하기 위하여 본 발명의 바람직한 실시예를 소개하기로 한다.Hereinafter, preferred embodiments of the present invention will be introduced in order to enable those skilled in the art to more easily carry out the present invention.

첨부된 도면 도 2a 내지 도 2c는 본 발명의 일 실시예에 따른 금속 콘택 형성 공정을 도시한 것으로, 이하 이를 참조하여 그 공정을 살펴본다.2A to 2C illustrate a metal contact formation process according to an embodiment of the present invention, and the process will be described below with reference to the drawings.

먼저, 도 2a는 실리콘 기판(20) 상에 BPSG막(21a), IPO(22), BPSG막(21b)이 차례로 적층된 구조에서 콘택홀이 형성된 상태를 나타낸 것이다. 이때, IPO(22)는 다른 단면에서 본다면 게이트 전극과 전하저장 전극간의 절연을 위해 형성된 층이다.First, FIG. 2A illustrates a state in which contact holes are formed in a structure in which a BPSG film 21a, an IPO 22, and a BPSG film 21b are sequentially stacked on a silicon substrate 20. At this time, the IPO 22 is a layer formed to insulate between the gate electrode and the charge storage electrode as seen from another cross section.

다음으로, 도 2b에 도시된 바와 같이 BPSG막(21a, 21b), IPO(22)으로 구성된 콘택홀 내벽에 B 이온을 주입한다. 도면에서 빗금으로 표시된 부분이 B 이온이 이온주입된 영역이다. 일반적으로, 산화막에 P를 도핑하면 그 산화막의 습식 식각 속도가 빨라지고, B가 도핑되면 그 속도가 느려지게 된다. 그러므로, 콘택홀 내벽을 구성하는 BPSG막(21a, 21b), IPO(22)에 B를 다량 주입하게 되면 각 구성 산화막의 표면 부분의 식각 속도를 모두 감소시키게 되어 세정 공정시 BPSG막(21a,21b), IPO(22) 간의 식각 속도의 차이를 둔화시킴으로써 IPO(22)의 돌출을 최소화할 수 있게 된다.Next, as shown in FIG. 2B, B ions are implanted into the inner wall of the contact hole formed of the BPSG films 21a and 21b and the IPO 22. In the drawing, portions indicated by hatched lines are regions in which B ions are ion implanted. In general, when P is doped with an oxide film, the wet etching rate of the oxide film is increased, and when B is doped, the speed is slowed. Therefore, when a large amount of B is injected into the BPSG films 21a and 21b and the IPO 22 constituting the inner wall of the contact hole, the etching rate of the surface portion of each constituent oxide film is reduced, and the BPSG films 21a and 21b are used during the cleaning process. ), It is possible to minimize the protrusion of the IPO 22 by slowing the difference in the etching rate between the IPO (22).

이때, 콘택홀 측벽에 B 이온이 효과적으로 이온주입될 수 있도록 콘택홀 내벽을 기준으로 할 때 약 10° 내지 약 20°의 경사를 이루어 입사되도록 조절한다. 이온주입시 에너지는 약 10㎸ 내지 약 50㎸이며, 도즈(dose)는 약 1015/㎠ 이상으로 하여 BPSG막(21a,21b), IPO(22)간의 식각 속도의 감소 효과가 현저히 나타나도록 하여 이들 산화막간의 식각 속도 차이를 최소화한다. 여기서, 도펀트로 BF2를 사용해도 거의 같은 효과를 얻을 수 있다.At this time, the B ions are adjusted to be inclined at about 10 ° to about 20 ° based on the inner wall of the contact hole so that B ions can be efficiently implanted into the contact hole side wall. The ion implantation energy ranges from about 10 kW to about 50 kW, and the dose is about 10 15 / cm 2 or more so that the effect of reducing the etching rate between the BPSG films 21a and 21b and the IPO 22 is remarkable. The difference in etching rates between these oxide films is minimized. In this case, even when BF 2 is used as the dopant, almost the same effect can be obtained.

이어서, 콘택홀 식각후 외기에 노출되어 형성된 실리콘 기판(20) 상의 자연 산화막(도시되지 않음)을 제거하기 위하여 세정 공정을 수행한다. 이때, 세정 용액은 100 : 1 BOE를 사용하며, 앞에서 언급한 바와 같이 고농도의 B 이온주입을 실시하였기 때문에 BPSG(21a, 21b)와 IPO(22) 모두 그 식각 속도가 둔화되어 식각 속도의 차이 또한 작기 때문에 IPO(22)의 돌출 현상을 최소화할 수 있게 되는 것이다.Subsequently, a cleaning process is performed to remove a native oxide film (not shown) on the silicon substrate 20 formed by being exposed to the outside air after etching the contact hole. At this time, 100: 1 BOE is used as the cleaning solution, and as mentioned above, since B ion implantation at a high concentration was performed, the etching rate of both BPSGs 21a and 21b and IPO 22 was slowed, so that the difference in the etching rate was also different. Since it is small, it is possible to minimize the protrusion of the IPO (22).

끝으로, 도 1C에 도시된 바와 같이 전체구조 상부에 알루미늄막(23)을 증착하여 보이드 없이 콘택홀을 매립한다.Finally, as shown in FIG. 1C, the aluminum film 23 is deposited on the entire structure to fill the contact hole without voids.

이상에서 설명한 본 발명은 전술한 실시예 및 첨부된 도면에 의해 한정되는 것이 아니고, 본 발명의 기술적 사상을 벗어나지 않는 범위 내에서 여러 가지 치환, 변형 및 변경이 가능하다는 것이 본 발명이 속하는 기술분야에서 통상의 지식을 가진 자에게 있어 명백할 것이다.The present invention described above is not limited to the above-described embodiments and the accompanying drawings, and various substitutions, modifications, and changes can be made in the art without departing from the technical spirit of the present invention. It will be apparent to those of ordinary knowledge.

전술한 본 발명은 고농도의 B 또는 BF2이온주입을 통해 콘택홀 내벽을 구성하는 산화막들의 식각 속도가 둔화되어 식각 속도의 차이 또한 작기 때문에 콘택홀 내벽에 턱이 지는 현상을 최소화하며, 이로 인하여 이후의 알루미늄 매립 공정에서 보이드 없이 콘택홀을 매립할 수 있게 됨으로써 반도체 소자의 신뢰도를 향상시키고, 반도체 소자 제조 공정상의 수율을 향상시키는 효과가 있다.According to the present invention, the etching rate of the oxide layers constituting the inner wall of the contact hole is slowed through the high concentration of B or BF 2 ion implantation, so the difference in the etching speed is also small, thereby minimizing the jaw on the inner wall of the contact hole. Since the contact holes can be buried without voids in the aluminum filling process, the reliability of the semiconductor device can be improved and the yield in the semiconductor device manufacturing process can be improved.

Claims (6)

소정의 하부층 상에 형성된 다층 구조의 층간절연산화막을 선택 식각하여 콘택홀을 형성하는 제1 단계;Forming a contact hole by selectively etching an interlayer insulating oxide film having a multilayer structure formed on a predetermined lower layer; 세정 용액에 대한 상기 층간절연 산화막의 식각 속도를 낮추기 위하여 상기 콘택홀 내벽에 붕소계 불순물을 이온주입하는 제2 단계;A second step of ion implanting a boron-based impurity into an inner wall of the contact hole to lower an etching rate of the interlayer insulating oxide film with respect to a cleaning solution; 상기 제2 단계 수행후, 자연산화막 제거를 위한 세정을 실시하는 제3 단계; 및A third step of performing cleaning to remove the native oxide film after performing the second step; And 상기 제3 단계를 마친 전체구조 상부에 금속막을 형성하여 상기 콘택홀을 매립하는 제4 단계A fourth step of filling the contact hole by forming a metal film on the entire structure after the third step 를 포함하여 이루어진 반도체 소자의 금속 콘택 형성방법.Metal contact forming method of a semiconductor device comprising a. 제1항에 있어서,The method of claim 1, 상기 붕소계 불순물이,The boron-based impurities, B 또는 BF2인 것을 특징으로 하는 반도체 소자의 금속 콘택 형성방법.Method of forming a metal contact of a semiconductor device, characterized in that B or BF 2 . 제1항 또는 제2항에 있어서,The method according to claim 1 or 2, 상기 제3 단계에서,In the third step, BOE(buffered oxide etchant) 용액을 사용하여 세정을 실시하는 것을 특징으로 하는 반도체 소자의 금속 콘택 형성방법.A method of forming a metal contact in a semiconductor device, characterized in that the cleaning is performed using a buffered oxide etchant (BOE) solution. 제1항 또는 제2항에 있어서,The method according to claim 1 or 2, 상기 제2 단계에서,In the second step, 상기 콘택홀 내벽과 10° 내지 20°의 경사각을 이룬 상태에서 이온주입을 실시하는 것을 특징으로 하는 반도체 소자의 금속 콘택 형성방법.The method for forming a metal contact of a semiconductor device, characterized in that the ion implantation is performed in a state in which the inclined angle of 10 ° to 20 ° with the inner wall of the contact hole. 제4항에 있어서,The method of claim 4, wherein 상기 제2 단계에서,In the second step, 1015/㎠ 이상의 도즈를 사용하여 이온주입을 실시하는 것을 특징으로 하는 반도체 소자의 금속 콘택 형성방법.A method of forming a metal contact for a semiconductor device, characterized in that ion implantation is performed using a dose of 10 15 / cm 2 or more. 제4항에 있어서,The method of claim 4, wherein 상기 제2 단계에서,In the second step, 10㎸ 내지 50㎸의 이온주입 에너지를 사용하여 이온주입을 실시하는 것을 특징으로 하는 반도체 소자의 금속 콘택 형성방법.A method for forming a metal contact in a semiconductor device, characterized in that ion implantation is performed using ion implantation energy of 10 kV to 50 kV.
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JPS5494281A (en) * 1978-01-10 1979-07-25 Toshiba Corp Production of semiconductor device
JPH0239429A (en) * 1988-07-28 1990-02-08 Matsushita Electron Corp Manufacture of semiconductor device
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JPS5494281A (en) * 1978-01-10 1979-07-25 Toshiba Corp Production of semiconductor device
JPH0239429A (en) * 1988-07-28 1990-02-08 Matsushita Electron Corp Manufacture of semiconductor device
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