KR100543076B1 - A method for making self-registering non-lithographic transistors with ultrashort channel lengths - Google Patents

Abstract

In a method of manufacturing transistors having an ultra short channel length, the deposition of each source, drain and gate electrodes can be performed for the first time with the prior art of limiting electrode sizes according to appropriate design rules, whereas the subsequent process In step the second sizes of the electrodes can be adjusted as desired. The channel region is formed between the source and drain electrodes without being limited by any design rule, which allows the formation of transistor channels of extremely short channel length L, for example 10 nm or less. Thus, the width of the gate electrodes can be adjusted to obtain a wide channel width (W) and to provide the transistors with almost any large characteristic ratio (W / L) and desirable switching and current characteristics. The method can be applied to make any kind of field-effect transistors on the same substrate, and can also be adjusted for the fabrication of other kinds of transistors.

Description

A METHOD FOR MAKING SELF-REGISTERING NON-LITHOGRAPHIC TRANSISTORS WITH ULTRASHORT CHANNEL LENGTHS

The present invention relates to a method of manufacturing transistors having ultra short channel lengths.

Many efforts have been made in conjunction with attempts to increase switching speed by reducing channels length beyond conforming to design rules and lithography, to reduce the size of the circuit (on silicon or other substrates). Circuit size reduction is part of the silicon world's widespread efforts, and soon the limits for photolithography and x-ray lithography are reached, and more exotic approaches will result in line widths of approximately 0.04 μm (40 mm) in the manufacturing process in 2010. And with the purpose of reaching the line, it is being promoted. However, this is very widely attempted by preferred, for example single molecule switches, nanoswitches and the like.

Optionally, non-lithographic patterning techniques may have better alternatives, such as micropatterning or self-assembly techniques. However, these self-assembly techniques are more exotic than the most advanced lithography initiatives because they introduce completely new processes and equipment into a very conservative industry. In addition, neither of the two techniques currently have real potential or enable the design of complex circuits, partly due to registration issues and partly due to the design of multi-layer structures. Because of the problems. Other techniques (eg using hard stamps, Obducat) face the same problems.

Problems that cannot be solved by known techniques include: 1) making a very short (a few atoms long) channel length, ie the distance between source and drain electrodes, 2) standard silicon processes, fabrication techniques and equipment or Achieving this using one of the non-standard, non-lithographic techniques, 3) with a given lithography / patterning tool, using it to obtain a smaller circuit footprint, i.e. a denser circuit. 4) to achieve this using self-matching.

It is an object of the present invention to provide a method which overcomes the problems inherent in the current or prior arts listed above in a preferred manner.

A number of additional features as well as the object of the invention are achieved by the method according to the invention, which method comprises

a) depositing a conductive material on a substrate of semiconductor material,

b) patterning the conductive material into first electrodes, such as parallel strips having a pitch determined by applicable design rules, leaving exposed strip-like substrate regions between the first electrodes,

c) depositing a barrier layer covering the first electrodes down to the substrate,

d) doping the exposed areas of the substrate,

e) depositing a conductive material on the doped region of the substrate, and then forming second electrodes such as parallel strips thereon,

f) removing the barrier layer covering the first electrodes and leaving vertical channels extending down between the first and second electrodes to undoped regions of the substrate,

g) doping the exposed areas of the substrate at the bottom of the channels,

h) filling said channels with barrier material,

i) removing the first electrodes, leaving openings between the second electrodes, exposing regions of the substrate between the second electrodes,

j) doping the exposed regions of the substrate in the openings from which the first electrodes have been removed,

k) depositing a conductive material in the openings to regenerate the first electrodes, thus, such as a parallel strip of approximately equal width separated by any thin layer of barrier material alone, interfacing with the doped substrate The first electrodes of the transistor structures now constitute one of the source or drain electrodes of the transistor structures, as an electrode layer of the first and second electrodes is obtained and, as a result, depends on the dopants used in the doping steps. The second electrodes correspondingly constitute a source or a drain,

l) depositing an insulating barrier layer on the electrodes and the isolation barrier layers,

m) depositing the conductive material on top of the barrier layer, and

n) patterning the conductive materials to form gate electrodes, such as parallel strips, which are oriented clockwise relative to the source and drain electrodes, and as such are given by the patterned gate electrode. A matrix of effect transistor structures is obtained with a very short channel length and any wide channel width.

In the process according to the invention, the conductive material is preferably selected from metals or organic materials, preferably polymer or copolymer materials.

In general, photomicrolithography is preferably used in the patterning step, but non-lithography tools can equally be used in the patterning process.

In the method according to the invention, the barrier layers and / or the electrodes are preferably removed by etching.

Preferably the thin film / thin barrier layer may be formed by a selective deposition process or optionally the thin film / thin barrier layer may be formed by spraying.

In the method according to the invention, the patterning can be preferably performed by etching.

In the method according to the invention, the selection of the semiconductor substrate material as silicon can also be considered advantageously.

Finally, in the method according to the invention, the matrix or transistor structures can be appropriately divided to form more individual field-effect transistors or circuits than one transistor of this kind.

The invention may be better understood when reading the step-by-step descriptions of a method of manufacturing a transistor and in conjunction with the following figures, with exemplary embodiments of various steps.

1, 2A, 3-11A, 12 and 13 illustrate successive process steps of a method of manufacturing a transistor structure according to the present invention, as made by the cross section of structures derived from each step.

FIG. 2B shows a plan view of the structures made in the cross section of FIG. 2A.

FIG. 11B shows a plan view of the structures made in the cross section of FIG. 11A.

14a shows a plan view of a field-effect transistor made by the method according to the invention with the contours of the channels indicated by the stitch lines and the source and drain electrodes.

FIG. 14B shows a cross sectional view through the matrix of FIG. 14A taken along line A-A. FIG.

Now, the method according to the invention will be described step by step.

In FIG. 1, a substrate 1 of semiconductor material with a suitable barrier layer is shown, which can be an organic as well as an inorganic conductive material, on which a conductive material layer 2 is deposited. The substrate itself may be rigid or fluid depending on the material selected. Preferably, the substrate is silicon. The conductive layer 2 is now patterned into first electrodes, such as parallel strips, as shown in the plan views of FIGS. 2A and 2B by a suitable patterning method, for example based on photomicrolithography, and subsequent etching. The pitch w, i.e. the width w of the electrode plus the distance d to the next electrode, depends on the applicable design rules and can match the minimum process-constrained feature size f, where w and d are It is about the same, but cannot have a value of d much larger than w. The patterning leaves the recesses 3 between the first electrodes 2 as shown in FIG. 2A, and the electrodes 2, such as the parallel strips, which can be made very thin, are much larger than the width w. With a smaller height h, as shown in FIG. 3, it is covered by a thin film barrier layer 4 which extends down to the substrate of the recesses 3 with respect to the first electrodes 2. The barrier layer thickness is not limited by design rules and can therefore be made very small and actually below nanoatomic size.

The lower portions of the recesses 3 are exposed regions of the substrate 1 as shown in FIG. 3. The substrate 1 now forms the doped regions 5 of the substrate 1 with the desired conduction form, for example electron or n-type conduction or hole or p-type conduction, as shown in FIG. 4. In order to be doped into the exposed areas. In the next step, as shown in FIG. 5, the recesses 3 are conductive to the doped regions 5 of the substrate 1 to form second electrodes 6, such as a second parallel strip. Filled with material 6. 6, the barrier layer 4 is removed from the first electrodes 2 by a suitable process, for example by etching, and the first and second electrodes 2; 6. Leave vertical channels or grooves in between. The undoped regions of the substrate 1 are now exposed under the vertical channels 7, and in the second doping step shown in FIG. 7, the substrates of the regions are formed in order to form the doped regions 8. Doped. Obviously, the dopant will be selected so that if the regions 5 are doped with n-type conduction, the substrate of the regions 8 will be doped with p-type conduction or vice versa.

The vertical grooves or channels 7 are then filled with an insulating barrier layer 4, which can be deposited, for example, in a controlled spraying process or deposits a global barrier layer with continued removal of excess material, The barrier material 4 covers the regions of the substrate 1 over the doped regions 8, as shown in FIG. 8. In the next process step, the first electrodes 2 are removed with the barrier layers 4, leaving recesses or openings 3 ′ between the second electrodes 6, as shown in FIG. 9. do. Removal of the first electrodes 2 is possible, for example, by photomicrolithography and etching, followed by a third doping step, thus exposing and undoped of the substrate 1 in the openings 3 ′. The non-regions 9 are doped to form doped regions 9 in the substrate, as made in FIG. The regions 9 will be doped n-type if they have a suitable conducting form, ie the regions 5 are n-doped and p-doped regions 8. This is of course possible in the rest of the way. In a subsequent process step, the first electrodes are shown in FIG. 11A by simply filling the openings 3 'with a thin film of a suitable conductive material, which may be inorganic or organic, over the doped regions 9 of the substrate 1. Can be regenerated as if. The same conductive material can preferably be used as the first and second electrodes 2; 6. The resulting structure is shown in plan view in FIG. 11B.

The first and second electrodes 2; 6 in contact with the appropriately doped regions 5, 8, 9 of the substrate 1 are like parallel strips, each having a source and a drain separated very closely in the transistor structure. The electrodes can be formed. The channel length L under the barrier layer of the doped regions 8 spam of the substrate, i.e. the distance between the source electrode 2 and the drain electrode 4 (FIG. 11A) is very short, if desired, below 1 nm. Even the thickness of the barrier layer δ is derived from the process of depositing an ultra thin film of the barrier material, and the process need not be limited by any design rule. As mentioned above, it is known to those skilled in the art that the barrier layers can also be deposited as monoatomic layers. The channel length L of the transistor structure produced by the method according to the invention can be made almost arbitrarily small, which is a particularly desirable property, for example in field-effect transistors.

In addition, a barrier layer 4 is provided on the top surfaces of the source and drain electrodes 2 and 6, the electrodes 2 and 6 are insulated from each other, and the top surfaces are similarly insulated, as shown in FIG. It is Now another thin film global layer 10 of conductive material is deposited over the widely applied barrier layer 4, which layer 10 is patterned to form gate electrodes of transistor structures fabricated by the method according to the invention. Can be. The patterning of the actual gate electrodes can be in process steps similar to those used to form the first and second electrodes 2; 6, followed by various process steps shown in FIGS. 1, 2A, 3 and 5. Similar to the Thus, a very dense pattern of gate electrodes 10 can be obtained, and all of the second electrodes of the gate electrodes can be based on photomicrolithography and subsequent etching, for example, before depositing a suitable barrier layer. This means that the obtainable sizes of the gate electrodes depend on the same considerations as they are made in connection with the sizes of the first and second electrodes 2, 6. Thus, it is possible to make separate gate electrodes 10 having respective widths W, which in turn means that the separated transistor structures made by the method according to the invention have various channel width / channel length ratios (W /). L) means made. As is well known to those skilled in the art, it is desirable to have a large W / L, as the magnitude of the drain current I _D depends on the above ratio of effective control voltage and process parameters.

Many advantages can be obtained from transistors made by the method according to the invention. For example, the switching speed of the transistors depends on various factors, but the primary structural parameter that affects the switching speed is the distance L between the source and drain electrodes, and the charge carriers cover the distance. Need some time for In other words, the shorter the distance L, the faster the switching speed under other identical conditions. Prior art solutions and current technology are limited by current process-constrained minimum feature sizes, which means, for example, at least 180 nm channel length in the case of 0.18 μm lithography. Although lithography conforming to current standards is still used in the electrode patterning step, the method according to the invention allows for reduction of the channel length L, for example up to 10 nm or less, and the thickness of the barrier layer It is not limited by design rules.

From FIG. 14B, if the width W of the gate electrode coincident with the channel width is limited to below the design rule of the patterning process used to form the particular electrode, then the one shown in FIG. Gate electrodes formed in a similar molding step are adjusted by simply increasing the thickness of the barrier layer 4 between the gate electrodes 10 before filling with additional electrode material in the recesses between the electrodes, such as already patterned strips. It can have an actual width (W) to be. Thus, for every second gate electrode in the transistor structure matrix, it is possible to form gate electrodes to obtain transistors with varying widths W.

As a result, one of the most important characteristics of the method according to the invention is the possibility of controlling the relationship between the most important design parameter, the channel width W and the channel length L, i.e. the characteristic ratio W / L, It serves as a scale factor for drain current I _D. In addition, the present invention makes it possible to manufacture all types of field-effect transistors. It is also possible to fabricate structurally identical field-effect transistors on the same substrate, but have to have adjusted values for selected design parameters. For example, two or more MOSFETS having the same threshold voltage (V _T ) but different amounts of current can be fabricated on the same substrate since it is possible to use various values for W / L. For example, in the range of several milliamps, high values for the drain current I _D can yield transistors with a high characteristic ratio (W / L), which in the present technology means area-consuming devices. With the present invention, the characteristic ratio W / L can be selected almost arbitrarily large without occupying an excessive amount of area. The characteristic ratio W / L can be increased to provide the desired current level, but at present this means an increased increase in gate area and corresponding device capacity, which adversely affects the switching speed of the transistor, eg For example, the MOSFETs of the prior art are limited to a characteristic ratio (W / L) not much greater than 10. These disadvantageous characteristics can all be eliminated by making transistors using the method according to the invention.

Although the previously described preferred embodiment uses conventional microphotolithography and etching processes for the patterning of electrode structures, the method of the present invention is equally soft lithography and for example hard or soft stamps to produce desired patterns. It can be implemented with the use of more sophisticated patterning processes, including the use of non-lithographic tools such as. In order to obtain an additional reduction in feature sizes, it is also possible to design the electrode patterns by, for example, printing techniques. The printing techniques can be carried out depending on the so-called nanoprinting which is currently being developed, which means that for example the electrode patterns are obtained with less than 10 nm or less feature size or similar film thickness, which can be obtained by the method according to the invention. It is designed to be scaled similar to the channel length.

In addition, the method according to the invention enables the manufacture of more complex circuit structures on the same substrate by suitable post-processing or the appropriate selection of intermediate steps, the conduction forms and the design sizes can be suitably selected and the electric field It can be used in a tailor-specific form of effect transistors, and additional intermediate layers can be deposited, for example, to make transistor-based memories of a matrix addressable array or to form complementary transistor circuits. For example transistor portions or entire transistor structures may be removed in an etching step, for example, and replaced instead by various passive components formed by thin film technology, for example resistors or interconnects. As made with the method of the present invention, original transistor structures are provided for more complex circuits that are fully integrated.

Claims (11)

A method of fabricating a matrix of field effect transistor structures having an ultrashort channel length, a) depositing a conductive material on a substrate of semiconductor material, b) patterning the conductive material into first electrodes such as parallel strips, leaving exposed strip-like substrate regions between the first electrodes, c) depositing a barrier layer covering the first electrodes down to the substrate, d) doping the substrate with dopants of a first conductivity type in exposed areas of the substrate, e) depositing a conductive material on the doped region of the substrate, and then forming second electrodes such as parallel strips thereon, f) removing the barrier layer covering the first electrodes and leaving vertical channels extending down between the first and second electrodes to undoped regions of the substrate, g) doping exposed regions of the substrate at the bottom of the channels with a dopant of a second conductivity type, h) filling said channels with an insulating barrier material, i) removing the first electrodes, leaving openings between the second electrodes and the barrier materials, exposing regions of the substrate between the second electrodes, j) doping the exposed regions of the substrate with a dopant of the first conductivity type in the openings from which the first electrodes have been removed, k) depositing a conductive material in the openings to regenerate the first electrodes—thus an approximately equal width parallel strip shaped agent that interfaces with the doped substrate and is separated by any thin layer of barrier material alone. As the electrode layer of the first and second electrodes is obtained, and as a result depending on the dopants used in the doping steps, the first electrodes of the transistor structures now constitute one of the source or drain electrodes of the transistor structures, The second electrodes correspondingly constitute a source or a drain; l) depositing an insulating barrier layer on the electrodes and the isolation barrier layers, m) depositing the conductive material on top of the barrier layer, and n) patterning the conductive materials to form gate electrodes, such as parallel strips, which are oriented clockwise relative to the source and drain electrodes, wherein the matrix of field-effect transistor structures is of any shortest channel length. Obtained with a wide channel width, wherein the channel width is determined by the width of the patterned gate electrodes. The method of claim 1, And wherein said conductive material is a metal. The method of claim 1, Said conductive material is selected from an organic material, preferably a polymer or copolymer material. The method of claim 1, A method of making a matrix of field effect transistor structures characterized by using photomicrolithography in patterning steps. The method of claim 1, A method of manufacturing a matrix of field effect transistor structures characterized in using non-lithography tools in patterning steps. The method of claim 1, Removing said barrier layers and / or said electrodes by etching. The method of claim 1, Forming said thin film / thin barrier layer by a selective deposition process. The method of claim 1, Forming said thin film / thin barrier layer by spraying. The method of claim 1, And wherein said patterning is performed by etching. The method of claim 1, Selecting the semiconductor substrate material as silicon. The method of claim 1, A method of manufacturing a matrix of field effect transistor structures, characterized in that the transistor matrix structures are appropriately divided to form individual field-effect transistors or circuits of at least one transistor of the kind.

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